[AMDGPU] gfx1010 s_code_end generation

[rampitec]

Summary

Also add some missing metadata in the streamer.

[msearles]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
   if (AMDGPU::isGroupSegment(GV))
     return;
 
   AsmPrinter::EmitGlobalVariable(GV);
 }
 
 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
   CallGraphResourceInfo.clear();
+
+  if (AMDGPU::isGFX10(*getGlobalSTI())) {
+    OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
+    getTargetStreamer()->EmitCodeEnd();
+  }
+
   return AsmPrinter::doFinalization(M);
 }
 
 // Print comments that apply to both callable functions and entry points.
 void AMDGPUAsmPrinter::emitCommonFunctionComments(
   uint32_t NumVGPR,
   uint32_t NumSGPR,
   uint64_t ScratchSize,
void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
   // We need to program the hardware with the amount of scratch memory that
   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
   // scratch memory used per thread.
   ProgInfo.ScratchBlocks =
       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
               1ULL << ScratchAlignShift) >>
       ScratchAlignShift;
 
+  if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) {
+    ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
+    ProgInfo.MemOrdered = 1;
+  }
+
   ProgInfo.ComputePGMRSrc1 =
       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
       S_00B848_PRIORITY(ProgInfo.Priority) |
       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
       S_00B848_PRIV(ProgInfo.Priv) |
       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
-      S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
+      S_00B848_IEEE_MODE(ProgInfo.IEEEMode) |
+      S_00B848_WGP_MODE(ProgInfo.WgpMode) |
+      S_00B848_MEM_ORDERED(ProgInfo.MemOrdered);
 
   // 0 = X, 1 = XY, 2 = XYZ
   unsigned TIDIGCompCnt = 0;
   if (MFI->hasWorkItemIDZ())
     TIDIGCompCnt = 2;
   else if (MFI->hasWorkItemIDY())
     TIDIGCompCnt = 1;
 
void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
 
   AMDGPU::initDefaultAMDKernelCodeT(Out, &STM);
 
   Out.compute_pgm_resource_registers =
       CurrentProgramInfo.ComputePGMRSrc1 |
       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
-  Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
+  Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
 
   if (CurrentProgramInfo.DynamicCallStack)
     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
 
   AMD_HSA_BITS_SET(Out.code_properties,
                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
 

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

public:
   /// the \p HSAMetadata structure is updated with the correct types.
   ///
   /// \returns True on success, false on failure.
   virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) = 0;
 
   /// \returns True on success, false on failure.
   virtual bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) = 0;
 
+  /// \returns True on success, false on failure.
+  virtual bool EmitCodeEnd() = 0;
+
   virtual void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
       uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
       bool ReserveXNACK) = 0;
 
   static StringRef getArchNameFromElfMach(unsigned ElfMach);
   static unsigned getElfMach(StringRef GPU);
public:
   bool EmitISAVersion(StringRef IsaVersionString) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
+  /// \returns True on success, false on failure.
+  bool EmitCodeEnd() override;
+
   void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
       uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
       bool ReserveXNACK) override;
 };
 
 class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
public:
   bool EmitISAVersion(StringRef IsaVersionString) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
+  /// \returns True on success, false on failure.
+  bool EmitCodeEnd() override;
+
   void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
       uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
       bool ReserveXNACK) override;
 };
 
 }
 #endif

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
   HSAMetadataDoc.toYAML(StrOS);
 
   OS << '\t' << V3::AssemblerDirectiveBegin << '\n';
   OS << StrOS.str() << '\n';
   OS << '\t' << V3::AssemblerDirectiveEnd << '\n';
   return true;
 }
 
+bool AMDGPUTargetAsmStreamer::EmitCodeEnd() {
+  const uint32_t Encoded_s_code_end = 0xbf9f0000;
+  OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n';
+  OS << "\t.fill 32, 4, " << Encoded_s_code_end << '\n';
+  return true;
+}
+
 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
     bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
   IsaVersion IVersion = getIsaVersion(STI.getCPU());
 
   OS << "\t.amdhsa_kernel " << KernelName << '\n';
 
EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA,
            [&](MCELFStreamer &OS) {
              OS.EmitLabel(DescBegin);
              OS.EmitBytes(HSAMetadataString);
              OS.EmitLabel(DescEnd);
            });
   return true;
 }
 
+bool AMDGPUTargetELFStreamer::EmitCodeEnd() {
+  const uint32_t Encoded_s_code_end = 0xbf9f0000;
+
+  MCStreamer &OS = getStreamer();
+  OS.PushSection();
+  OS.EmitValueToAlignment(64, Encoded_s_code_end, 4);
+  for (unsigned I = 0; I < 32; ++I)
+    OS.EmitIntValue(Encoded_s_code_end, 4);
+  OS.PopSection();
+  return true;
+}
+
 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
     uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
     bool ReserveXNACK) {
   auto &Streamer = getStreamer();
   auto &Context = Streamer.getContext();
 

llvm/trunk/lib/Target/AMDGPU/SIProgramInfo.h

struct SIProgramInfo {
     uint32_t VGPRBlocks = 0;
     uint32_t SGPRBlocks = 0;
     uint32_t Priority = 0;
     uint32_t FloatMode = 0;
     uint32_t Priv = 0;
     uint32_t DX10Clamp = 0;
     uint32_t DebugMode = 0;
     uint32_t IEEEMode = 0;
+    uint32_t WgpMode = 0; // GFX10+
+    uint32_t MemOrdered = 0; // GFX10+
     uint64_t ScratchSize = 0;
 
     uint64_t ComputePGMRSrc1 = 0;
 
     // Fields set in PGM_RSRC2 pm4 packet.
     uint32_t LDSBlocks = 0;
     uint32_t ScratchBlocks = 0;
 

llvm/trunk/test/CodeGen/AMDGPU/s_code_end.ll

+; RUN: llc -march=amdgcn -mcpu=gfx1010 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GCN-ASM,GFX10,GFX10-ASM %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -filetype=obj < %s | llvm-objdump -arch=amdgcn -mcpu=gfx1010 -disassemble - | FileCheck -check-prefixes=GCN,GCN-OBJ,GFX10,GFX10-OBJ %s
+
+; GCN:            a_kernel1:
+; GCN-NEXT:               s_endpgm
+; GCN-ASM-NEXT:   [[END_LABEL1:\.Lfunc_end.*]]:
+; GCN-ASM-NEXT:           .size   a_kernel1, [[END_LABEL1]]-a_kernel1
+; GCN-ASM:                .section        .AMDGPU.config
+
+; GCN-OBJ-NEXT:           s_nop 0
+
+define amdgpu_kernel void @a_kernel1() {
+  ret void
+}
+
+; GCN:            a_kernel2:
+; GCN-NEXT:               s_endpgm
+; GCN-ASM-NEXT:   [[END_LABEL2:\.Lfunc_end.*]]:
+; GCN-ASM-NEXT:           .size   a_kernel2, [[END_LABEL2]]-a_kernel2
+; GCN-ASM:                .section        .AMDGPU.config
+
+; GCN-OBJ-NEXT:   {{^$}}
+
+define amdgpu_kernel void @a_kernel2() {
+  ret void
+}
+
+; GCN-ASM:                .text
+; GCN-ASM-NEXT:           .globl  a_function
+; GCN-ASM-NEXT:           .p2align        2
+; GCN-ASM-NEXT:           .type   a_function,@function
+
+; GCN-NEXT:       a_function:
+; GCN:                    s_setpc_b64
+; GCN-ASM-NEXT:   [[END_LABEL3:\.Lfunc_end.*]]:
+; GCN-ASM-NEXT:           .size   a_function, [[END_LABEL3]]-a_function
+; GFX10-ASM:              .p2alignl 6, 3214868480
+; GFX10-ASM-NEXT:         .fill 32, 4, 3214868480
+
+; GFX10-OBJ-NEXT:         s_code_end
+
+; GFX10-OBJ:              s_code_end // 000000000140:
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+; GFX10-OBJ-NEXT:         s_code_end
+
+define void @a_function() {
+  ret void
+}