AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand

[nhaehnle]

Summary

No test case because I don't know of a way to trigger this, but I
accidentally caused this to fail while working on a different change.

Change-Id: I8015aa447fe27163cc4e4902205a203bd44bf7e3

[arsenm]

You can write a pure verifier test

[rampitec]

LGTM

[nhaehnle]

Added a minimal verifier-only test before commit.

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
       if (!compareMachineOp(Src0, Src1) &&
           !compareMachineOp(Src0, Src2)) {
         ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
         return false;
       }
     }
   }
 
+  if (isSOP2(MI) || isSOPC(MI)) {
+    const MachineOperand &Src0 = MI.getOperand(Src0Idx);
+    const MachineOperand &Src1 = MI.getOperand(Src1Idx);
+    unsigned Immediates = 0;
+
+    if (!Src0.isReg() &&
+        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
+      Immediates++;
+    if (!Src1.isReg() &&
+        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
+      Immediates++;
+
+    if (Immediates > 1) {
+      ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
+      return false;
+    }
+  }
+
   if (isSOPK(MI)) {
     auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
     if (Desc.isBranch()) {
       if (!Op->isMBB()) {
         ErrInfo = "invalid branch target for SOPK instruction";
         return false;
       }
     } else {

llvm/trunk/test/CodeGen/AMDGPU/verify-sop.mir

+# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: S_CMP_EQ_U32
+
+# CHECK-NOT: Bad machine code
+
+---
+name: sop2_sopc
+tracksRegLiveness: true
+body: |
+  bb.0:
+    %0:sreg_32_xm0 = S_ADD_I32 2011, -113, implicit-def $scc
+    S_CMP_EQ_U32 2011, -113, implicit-def $scc
+
+    %1:sreg_32_xm0 = S_SUB_I32 2011, 10, implicit-def $scc
+    S_CMP_LG_U32 -5, 2011, implicit-def $scc
+...