[AArch64] Add an option to get the TLS pointer from software

[Thog]

Summary

This patch adds an option to get the TLS pointer via a call to aarch64_read_tp() (similar to aeabi_read_tp on AArch32).

Necessary on Nintendo Horizon OS, which puts the TLS pointer at a calculated offset from TPIDR_EL0.

[efriedma]

How did you come up with the name __aarch64_read_tp? I guess it's okay.

which puts the TLS pointer at a calculated offset from TPIDR_EL0

I don't really understand how this is different from normal ELF TLS; does the offset vary at runtime somehow?

lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

525

Is this addReg necessary? The definition of X0 is an implicit definition, so it should be copied by transferImpOps, unless I'm missing something.

RegState::Dead doesn't make any sense.

test/CodeGen/AArch64/readtp.ll

11

Would it make sense to modify one of the existing tests for this, like arm64-tls-dynamics.ll, instead of adding a separate test file?

[t.p.northover]

lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

525

It's also non-implicit (which I'm surprised MCInstrDesc doesn't complain about), and a use rather than a def.

lib/Target/AArch64/AArch64Subtarget.h

379

Functions start lower case.

[Thog]

In D61226#1485627, @efriedma wrote:

How did you come up with the name __aarch64_read_tp? I guess it's okay.

That is how devkitPro's fork of GCC calls it.
There is no standard name for it since AArch64 ABI doesn't define a soft-tp interface.

In D61226#1485627, @efriedma wrote:

I don't really understand how this is different from normal ELF TLS; does the offset vary at runtime somehow?

With HardTp model, TPIDR_EL0 points to the TLS region.
With SoftTp model, the TLS region can be anywhere (the __aarch64_read_tp function is ran to find out where it is).
Under the Horizon kernel and with devkitPro's runtime, the TLS region is at *(TPIDR_EL0 + 0x1F8).
More generally, this allows supporting non-standard TLS regions.

lib/Target/AArch64/AArch64.td

def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
     "true", "Enable Branch Target Identification" >;
 
 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
     "true", "Enable Random Number generation instructions" >;
 
 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
     "true", "Enable Memory Tagging Extension" >;
 
+// The way of reading thread pointer
+def FeatureReadTp : SubtargetFeature<"read-tp-soft", "ReadTpSoft",
+    "true", "Read thread pointer from __aarch64_read_tp" >;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
   FeaturePAN, FeatureLOR, FeatureVH]>;
 

lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

case AArch64::MOVbaseTLS: {
     else if (MF->getSubtarget<AArch64Subtarget>().useEL1ForTP())
       SysReg = AArch64SysReg::TPIDR_EL1;
     BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
         .addImm(SysReg);
     MI.eraseFromParent();
     return true;
   }
 
+  case AArch64::GETbaseTLSsoft: {
+    unsigned DstReg = MI.getOperand(0).getReg();
+    MachineInstrBuilder MIB =
+        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::BL))
+            .addExternalSymbol("__aarch64_read_tp")
+            .addReg(DstReg, RegState::Dead)
+            .cloneMemRefs(MI);
+    transferImpOps(MI, MIB, MIB);
+    MI.eraseFromParent();
+    return true;
+  }
+
   case AArch64::MOVi32imm:
     return expandMOVImm(MBB, MBBI, 32);
   case AArch64::MOVi64imm:
     return expandMOVImm(MBB, MBBI, 64);
   case AArch64::RET_ReallyLR: {
     // Hiding the LR use with RET_ReallyLR may lead to extra kills in the
     // function and missing live-ins. We are fine in practice because callee
     // saved register handling ensures the register value is restored before

lib/Target/AArch64/AArch64InstrInfo.td

 def HasBTI           : Predicate<"Subtarget->hasBTI()">,
                        AssemblerPredicate<"FeatureBranchTargetId", "bti">;
 def HasMTE           : Predicate<"Subtarget->hasMTE()">,
                        AssemblerPredicate<"FeatureMTE", "mte">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def UseAlternateSExtLoadCVTF32
     : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
+def IsReadTPHard     : Predicate<"!Subtarget->IsReadTPSoft()">;
+def IsReadTPSoft     : Predicate<"Subtarget->IsReadTPSoft()">;
 
 def UseNegativeImmediates
     : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates",
                                              "NegativeImmediates">;
 
 def AArch64LocalRecover : SDNode<"ISD::LOCAL_RECOVER",
                                   SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
                                                        SDTCisInt<1>]>>;

 def MRS    : MRSI;
 def MSR    : MSRI;
 def MSRpstateImm1 : MSRpstateImm0_1;
 def MSRpstateImm4 : MSRpstateImm0_15;
 
 // The thread pointer (on Linux, at least, where this has been implemented) is
 // TPIDR_EL0.
 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),
-                       [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>;
+                       [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>,
+                       Requires<[IsReadTPHard]>;
+
+// __aarch64_read_tp preserves the registers x1-x7.
+// This is a pseudo inst so that we can get the encoding right,
+// complete with fixup for the aarch64_read_tp function.
+let isCall = 1,
+  Defs = [X0, X16, X17, LR], Uses = [SP] in {
+  def GETbaseTLSsoft :  Pseudo<(outs), (ins),
+               [(set X0, AArch64threadpointer)]>, Sched<[WriteBr]>,
+               Requires<[IsReadTPSoft]>;
+}
 
 let Uses = [ X9 ], Defs = [ X16, X17, LR, NZCV ] in {
 def HWASAN_CHECK_MEMACCESS : Pseudo<
   (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo),
   [(int_hwasan_check_memaccess X9, GPR64noip:$ptr, (i32 imm:$accessinfo))]>,
   Sched<[]>;
 }
 

lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasSSBS = false;
   bool HasSB = false;
   bool HasPredRes = false;
   bool HasCCDP = false;
   bool HasBTI = false;
   bool HasRandGen = false;
   bool HasMTE = false;
 
+  // If true, read thread pointer from __aarch64_read_tp.
+  bool ReadTpSoft = false;
+
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
 
   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
   bool HasZeroCycleZeroing = false;
   bool HasZeroCycleZeroingGP = false;
   bool HasZeroCycleZeroingFP = false;
   bool HasZeroCycleZeroingFPWorkaround = false;
public:
   bool hasSSBS() const { return HasSSBS; }
   bool hasSB() const { return HasSB; }
   bool hasPredRes() const { return HasPredRes; }
   bool hasCCDP() const { return HasCCDP; }
   bool hasBTI() const { return HasBTI; }
   bool hasRandGen() const { return HasRandGen; }
   bool hasMTE() const { return HasMTE; }
 
+  bool IsReadTPSoft() const { return ReadTpSoft; }
+
   bool isLittleEndian() const { return IsLittle; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
   bool isTargetIOS() const { return TargetTriple.isiOS(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }

test/CodeGen/AArch64/readtp.ll

+; RUN: llc -mtriple=arm64-none-linux-gnu -O2 -mattr=+read-tp-soft %s -o - | FileCheck %s -check-prefix=CHECK-SOFT
+; RUN: llc -mtriple=arm64-none-linux-gnu -O2 %s -o - | FileCheck %s -check-prefix=CHECK-HARD
+
+
+; __thread int counter;
+;  void foo() {
+;    counter = 5;
+;  }
+
+
+@counter = thread_local local_unnamed_addr global i32 0, align 4
+
+define void @foo() local_unnamed_addr #0 {
+entry:
+  store i32 5, i32* @counter, align 4
+  ret void
+}
+
+
+; CHECK-LABEL: foo:
+; CHECK-SOFT:    bl __aarch64_read_tp
+; CHECK-HARD:    mrs  {{x[0-9]+}}, TPIDR_EL0