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Differential D61114

[SelectionDAG] Use stack load/store in PromoteIntRes_BITCAST when the input needs to be be split and the output type is a vector.
ClosedPublic

Authored by craig.topper on Apr 24 2019, 10:01 PM.

Details

Reviewers
RKSimon
spatel
efriedma
Commits
rGf9c30eddd013: [SelectionDAG][X86] Use stack load/store in PromoteIntRes_BITCAST when the…
rL359219: [SelectionDAG][X86] Use stack load/store in PromoteIntRes_BITCAST when the…
Summary

We had special case handling here, but it uses a scalar any_extend for the
promotion then bitcasts to the final type. This won't split up the input data
into multiple promoted elements like we need.

This patch falls back to doing the conversion through memory.

Fixes PR41594 which I believe was reflected in the bitcast-vector-bool.ll
changes. The changes to vector-half-conversions.ll are fixing a previously
unknown miscompile from this issue.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 24 2019, 10:01 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 24 2019, 10:01 PM
Herald added a subscriber: hiraditya. · View Herald Transcript
Harbormaster completed remote builds in B30979: Diff 196578.Apr 24 2019, 10:01 PM
RKSimon mentioned this in rL359176: [X86][SSE] combineBitcastvxi1 - add support for bitcasting to non-scalar….Apr 25 2019, 2:32 AM
RKSimon mentioned this in rG0a7d1b3ce1d2: [X86][SSE] combineBitcastvxi1 - add support for bitcasting to non-scalar….
spatel accepted this revision.Apr 25 2019, 6:31 AM

LGTM - thanks!

(looks like you'll need to rebase test diffs after rL359176)

This revision is now accepted and ready to land.Apr 25 2019, 6:31 AM
Closed by commit rL359219: [SelectionDAG][X86] Use stack load/store in PromoteIntRes_BITCAST when the… (authored by ctopper). · Explain WhyApr 25 2019, 11:20 AM
This revision was automatically updated to reflect the committed changes.
efriedma added inline comments.Apr 25 2019, 12:24 PM
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
326 ↗(On Diff #196691)

I wonder if there's anything else which would be reasonable to do on a target-independent basis...

I guess on x86, for a bitcast like bitcast <64 x i1> %1 to <2 x i32>, the optimal lowering is actually involves splitting the operation: you then have two bitcast <32 x i1> %1 to i32, which has an existing efficient custom lowering. Then you use a BUILD_VECTOR to turn the two results into a <2 x i32>. But I'm not sure that generalizes in a useful way.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
33 lines
test/
CodeGen/
X86/
1053 lines
1477 lines

Diff 196578

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Lines case TargetLowering::TypeExpandFloat:
break; break;
case TargetLowering::TypeScalarizeVector: case TargetLowering::TypeScalarizeVector:
// Convert the element to an integer and promote it by hand. // Convert the element to an integer and promote it by hand.
if (!NOutVT.isVector()) if (!NOutVT.isVector())
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
BitConvertToInteger(GetScalarizedVector(InOp))); BitConvertToInteger(GetScalarizedVector(InOp)));
break; break;
case TargetLowering::TypeSplitVector: { case TargetLowering::TypeSplitVector: {
if (!NOutVT.isVector()) {
// For example, i32 = BITCAST v2i16 on alpha. Convert the split // For example, i32 = BITCAST v2i16 on alpha. Convert the split
// pieces of the input into integers and reassemble in the final type. // pieces of the input into integers and reassemble in the final type.
SDValue Lo, Hi; SDValue Lo, Hi;
GetSplitVector(N->getOperand(0), Lo, Hi); GetSplitVector(N->getOperand(0), Lo, Hi);
Lo = BitConvertToInteger(Lo); Lo = BitConvertToInteger(Lo);
Hi = BitConvertToInteger(Hi); Hi = BitConvertToInteger(Hi);
if (DAG.getDataLayout().isBigEndian()) if (DAG.getDataLayout().isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
InOp = DAG.getNode(ISD::ANY_EXTEND, dl, InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
EVT::getIntegerVT(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(),
NOutVT.getSizeInBits()), NOutVT.getSizeInBits()),
JoinIntegers(Lo, Hi)); JoinIntegers(Lo, Hi));
return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
} }
break;
}
case TargetLowering::TypeWidenVector: case TargetLowering::TypeWidenVector:
// The input is widened to the same size. Convert to the widened value. // The input is widened to the same size. Convert to the widened value.
// Make sure that the outgoing value is not a vector, because this would // Make sure that the outgoing value is not a vector, because this would
// make us bitcast between two vectors which are legalized in different ways. // make us bitcast between two vectors which are legalized in different ways.
if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
// If the output type is also a vector and widening it to the same size // If the output type is also a vector and widening it to the same size
// as the widened input type would be a legal type, we can widen the bitcast // as the widened input type would be a legal type, we can widen the bitcast
▲ Show 20 Lines • Show All 3,668 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/bitcast-vector-bool.ll

Show First 20 Lines • Show All 1,102 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%4 = extractelement <2 x i8> %2, i32 1 %4 = extractelement <2 x i8> %2, i32 1
%5 = add i8 %3, %4 %5 = add i8 %3, %4
ret i8 %5 ret i8 %5
} }
define i16 @bitcast_v32i8_to_v2i16(<32 x i8> %a0) nounwind { define i16 @bitcast_v32i8_to_v2i16(<32 x i8> %a0) nounwind {
; SSE2-SSSE3-LABEL: bitcast_v32i8_to_v2i16: ; SSE2-SSSE3-LABEL: bitcast_v32i8_to_v2i16:
; SSE2-SSSE3: # %bb.0: ; SSE2-SSSE3: # %bb.0:
; SSE2-SSSE3-NEXT: pushq %rbp
; SSE2-SSSE3-NEXT: movq %rsp, %rbp
; SSE2-SSSE3-NEXT: andq $-32, %rsp
; SSE2-SSSE3-NEXT: subq $64, %rsp
; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm2
; SSE2-SSSE3-NEXT: pxor %xmm3, %xmm3
; SSE2-SSSE3-NEXT: pcmpgtb %xmm1, %xmm3
; SSE2-SSSE3-NEXT: movdqa %xmm3, (%rsp)
; SSE2-SSSE3-NEXT: pcmpgtb %xmm0, %xmm2
; SSE2-SSSE3-NEXT: movdqa %xmm2, {{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl (%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-SSSE3-NEXT: pextrw $0, %xmm0, %ecx
; SSE2-SSSE3-NEXT: pextrw $1, %xmm0, %eax
; SSE2-SSSE3-NEXT: addl %ecx, %eax
; SSE2-SSSE3-NEXT: # kill: def $ax killed $ax killed $eax
; SSE2-SSSE3-NEXT: movq %rbp, %rsp
; SSE2-SSSE3-NEXT: popq %rbp
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX1-LABEL: bitcast_v32i8_to_v2i16: ; AVX1-LABEL: bitcast_v32i8_to_v2i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $32, %rsp ; AVX1-NEXT: subq $32, %rsp
▲ Show 20 Lines • Show All 852 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%4 = extractelement <2 x i8> %2, i32 1 %4 = extractelement <2 x i8> %2, i32 1
%5 = add i8 %3, %4 %5 = add i8 %3, %4
ret i8 %5 ret i8 %5
} }
define i16 @bitcast_v32i16_to_v2i16(<32 x i16> %a0) nounwind { define i16 @bitcast_v32i16_to_v2i16(<32 x i16> %a0) nounwind {
; SSE2-SSSE3-LABEL: bitcast_v32i16_to_v2i16: ; SSE2-SSSE3-LABEL: bitcast_v32i16_to_v2i16:
; SSE2-SSSE3: # %bb.0: ; SSE2-SSSE3: # %bb.0:
; SSE2-SSSE3-NEXT: pushq %rbp
; SSE2-SSSE3-NEXT: movq %rsp, %rbp
; SSE2-SSSE3-NEXT: andq $-32, %rsp
; SSE2-SSSE3-NEXT: subq $64, %rsp
; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm4
; SSE2-SSSE3-NEXT: pxor %xmm5, %xmm5
; SSE2-SSSE3-NEXT: pcmpgtw %xmm3, %xmm5
; SSE2-SSSE3-NEXT: pxor %xmm3, %xmm3
; SSE2-SSSE3-NEXT: pcmpgtw %xmm2, %xmm3
; SSE2-SSSE3-NEXT: packsswb %xmm5, %xmm3
; SSE2-SSSE3-NEXT: movdqa %xmm3, (%rsp)
; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm2
; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm2
; SSE2-SSSE3-NEXT: pcmpgtw %xmm0, %xmm4
; SSE2-SSSE3-NEXT: packsswb %xmm2, %xmm4
; SSE2-SSSE3-NEXT: movdqa %xmm4, {{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl (%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-SSSE3-NEXT: pextrw $0, %xmm0, %ecx
; SSE2-SSSE3-NEXT: pextrw $1, %xmm0, %eax
; SSE2-SSSE3-NEXT: addl %ecx, %eax
; SSE2-SSSE3-NEXT: # kill: def $ax killed $ax killed $eax
; SSE2-SSSE3-NEXT: movq %rbp, %rsp
; SSE2-SSSE3-NEXT: popq %rbp
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX1-LABEL: bitcast_v32i16_to_v2i16: ; AVX1-LABEL: bitcast_v32i16_to_v2i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: pushq %rbp ; AVX1-NEXT: pushq %rbp
; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: movq %rsp, %rbp
; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: andq $-32, %rsp
; AVX1-NEXT: subq $32, %rsp ; AVX1-NEXT: subq $32, %rsp
▲ Show 20 Lines • Show All 302 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%4 = extractelement <2 x i16> %2, i32 1 %4 = extractelement <2 x i16> %2, i32 1
%5 = add i16 %3, %4 %5 = add i16 %3, %4
ret i16 %5 ret i16 %5
} }
define i32 @bitcast_v64i8_to_v2i8(<64 x i8> %a0) nounwind { define i32 @bitcast_v64i8_to_v2i8(<64 x i8> %a0) nounwind {
; SSE2-SSSE3-LABEL: bitcast_v64i8_to_v2i8: ; SSE2-SSSE3-LABEL: bitcast_v64i8_to_v2i8:
; SSE2-SSSE3: # %bb.0: ; SSE2-SSSE3: # %bb.0:
; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm4
; SSE2-SSSE3-NEXT: pxor %xmm5, %xmm5
; SSE2-SSSE3-NEXT: pcmpgtb %xmm3, %xmm5
; SSE2-SSSE3-NEXT: movdqa %xmm5, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: pxor %xmm3, %xmm3
; SSE2-SSSE3-NEXT: pcmpgtb %xmm2, %xmm3
; SSE2-SSSE3-NEXT: movdqa %xmm3, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm2
; SSE2-SSSE3-NEXT: pcmpgtb %xmm1, %xmm2
; SSE2-SSSE3-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: pcmpgtb %xmm0, %xmm4
; SSE2-SSSE3-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $4, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-SSSE3-NEXT: andl $1, %eax
; SSE2-SSSE3-NEXT: shll $5, %eax
; SSE2-SSSE3-NEXT: orl %ecx, %eax
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $6, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $7, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $8, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $9, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $10, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $11, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $12, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: andl $1, %edx
; SSE2-SSSE3-NEXT: shll $13, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-SSSE3-NEXT: andl $1, %ecx
; SSE2-SSSE3-NEXT: shll $14, %ecx
; SSE2-SSSE3-NEXT: orl %edx, %ecx
; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-SSSE3-NEXT: shll $15, %edx
; SSE2-SSSE3-NEXT: orl %ecx, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
; SSE2-SSSE3-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-SSSE3-NEXT: movd %xmm0, %ecx
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,0,1]
; SSE2-SSSE3-NEXT: movd %xmm0, %eax
; SSE2-SSSE3-NEXT: addl %ecx, %eax
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX12-LABEL: bitcast_v64i8_to_v2i8: ; AVX1-LABEL: bitcast_v64i8_to_v2i8:
; AVX12: # %bb.0: ; AVX1: # %bb.0:
; AVX12-NEXT: retq ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm3
; AVX1-NEXT: vpextrb $1, %xmm3, %eax
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: vpextrb $0, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: leal (%rcx,%rax,2), %eax
; AVX1-NEXT: vpextrb $2, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: leal (%rax,%rcx,4), %eax
; AVX1-NEXT: vpextrb $3, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: leal (%rax,%rcx,8), %eax
; AVX1-NEXT: vpextrb $4, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $4, %ecx
; AVX1-NEXT: orl %eax, %ecx
; AVX1-NEXT: vpextrb $5, %xmm3, %eax
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: shll $5, %eax
; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: vpextrb $6, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $6, %ecx
; AVX1-NEXT: vpextrb $7, %xmm3, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $7, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $8, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $8, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $9, %xmm3, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $9, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $10, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $10, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $11, %xmm3, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $11, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $12, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $12, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $13, %xmm3, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $13, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $14, %xmm3, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $14, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $15, %xmm3, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $15, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpextrb $0, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $16, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $1, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $17, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $2, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $18, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $3, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $19, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $4, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $20, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $5, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $21, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $6, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $22, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $7, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $23, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $8, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $24, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $9, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $25, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $10, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $26, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $11, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $27, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $12, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $28, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $13, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $29, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $14, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $30, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $15, %xmm1, %edx
; AVX1-NEXT: shll $31, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: orl %eax, %edx
; AVX1-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm1
; AVX1-NEXT: vpextrb $1, %xmm1, %eax
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: vpextrb $0, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: leal (%rcx,%rax,2), %eax
; AVX1-NEXT: vpextrb $2, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: leal (%rax,%rcx,4), %eax
; AVX1-NEXT: vpextrb $3, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: leal (%rax,%rcx,8), %eax
; AVX1-NEXT: vpextrb $4, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $4, %ecx
; AVX1-NEXT: orl %eax, %ecx
; AVX1-NEXT: vpextrb $5, %xmm1, %eax
; AVX1-NEXT: andl $1, %eax
; AVX1-NEXT: shll $5, %eax
; AVX1-NEXT: orl %ecx, %eax
; AVX1-NEXT: vpextrb $6, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $6, %ecx
; AVX1-NEXT: vpextrb $7, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $7, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $8, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $8, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $9, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $9, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $10, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $10, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $11, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $11, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $12, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $12, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $13, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $13, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $14, %xmm1, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $14, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $15, %xmm1, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $15, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vpextrb $0, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $16, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $1, %xmm0, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $17, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $2, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $18, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $3, %xmm0, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $19, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $4, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $20, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $5, %xmm0, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $21, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $6, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $22, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $7, %xmm0, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $23, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $8, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $24, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $9, %xmm0, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $25, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $10, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $26, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $11, %xmm0, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $27, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $12, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $28, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $13, %xmm0, %edx
; AVX1-NEXT: andl $1, %edx
; AVX1-NEXT: shll $29, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: vpextrb $14, %xmm0, %ecx
; AVX1-NEXT: andl $1, %ecx
; AVX1-NEXT: shll $30, %ecx
; AVX1-NEXT: orl %edx, %ecx
; AVX1-NEXT: vpextrb $15, %xmm0, %edx
; AVX1-NEXT: shll $31, %edx
; AVX1-NEXT: orl %ecx, %edx
; AVX1-NEXT: orl %eax, %edx
; AVX1-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: vmovd %xmm0, %ecx
; AVX1-NEXT: vpextrd $1, %xmm0, %eax
; AVX1-NEXT: addl %ecx, %eax
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: bitcast_v64i8_to_v2i8:
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vpextrb $1, %xmm1, %eax
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: vpextrb $0, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: leal (%rcx,%rax,2), %eax
; AVX2-NEXT: vpextrb $2, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: leal (%rax,%rcx,4), %eax
; AVX2-NEXT: vpextrb $3, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: leal (%rax,%rcx,8), %eax
; AVX2-NEXT: vpextrb $4, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $4, %ecx
; AVX2-NEXT: orl %eax, %ecx
; AVX2-NEXT: vpextrb $5, %xmm1, %eax
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: shll $5, %eax
; AVX2-NEXT: orl %ecx, %eax
; AVX2-NEXT: vpextrb $6, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $6, %ecx
; AVX2-NEXT: vpextrb $7, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $7, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $8, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $8, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $9, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $9, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $10, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $10, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $11, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $11, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $12, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $12, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $13, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $13, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $14, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $14, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $15, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $15, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX2-NEXT: vpextrb $0, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $16, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $1, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $17, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $2, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $18, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $3, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $19, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $4, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $20, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $5, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $21, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $6, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $22, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $7, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $23, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $8, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $24, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $9, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $25, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $10, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $26, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $11, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $27, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $12, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $28, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $13, %xmm1, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $29, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $14, %xmm1, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $30, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $15, %xmm1, %edx
; AVX2-NEXT: shll $31, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: orl %eax, %edx
; AVX2-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpextrb $1, %xmm0, %eax
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: vpextrb $0, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: leal (%rcx,%rax,2), %eax
; AVX2-NEXT: vpextrb $2, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: leal (%rax,%rcx,4), %eax
; AVX2-NEXT: vpextrb $3, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: leal (%rax,%rcx,8), %eax
; AVX2-NEXT: vpextrb $4, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $4, %ecx
; AVX2-NEXT: orl %eax, %ecx
; AVX2-NEXT: vpextrb $5, %xmm0, %eax
; AVX2-NEXT: andl $1, %eax
; AVX2-NEXT: shll $5, %eax
; AVX2-NEXT: orl %ecx, %eax
; AVX2-NEXT: vpextrb $6, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $6, %ecx
; AVX2-NEXT: vpextrb $7, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $7, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $8, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $8, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $9, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $9, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $10, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $10, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $11, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $11, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $12, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $12, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $13, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $13, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $14, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $14, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $15, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $15, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vpextrb $0, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $16, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $1, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $17, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $2, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $18, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $3, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $19, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $4, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $20, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $5, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $21, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $6, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $22, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $7, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $23, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $8, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $24, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $9, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $25, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $10, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $26, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $11, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $27, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $12, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $28, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $13, %xmm0, %edx
; AVX2-NEXT: andl $1, %edx
; AVX2-NEXT: shll $29, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: vpextrb $14, %xmm0, %ecx
; AVX2-NEXT: andl $1, %ecx
; AVX2-NEXT: shll $30, %ecx
; AVX2-NEXT: orl %edx, %ecx
; AVX2-NEXT: vpextrb $15, %xmm0, %edx
; AVX2-NEXT: shll $31, %edx
; AVX2-NEXT: orl %ecx, %edx
; AVX2-NEXT: orl %eax, %edx
; AVX2-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: vmovd %xmm0, %ecx
; AVX2-NEXT: vpextrd $1, %xmm0, %eax
; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
; ;
; AVX512-LABEL: bitcast_v64i8_to_v2i8: ; AVX512-LABEL: bitcast_v64i8_to_v2i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpmovb2m %zmm0, %k0 ; AVX512-NEXT: vpmovb2m %zmm0, %k0
; AVX512-NEXT: kmovq %k0, -{{[0-9]+}}(%rsp) ; AVX512-NEXT: kmovq %k0, -{{[0-9]+}}(%rsp)
; AVX512-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; AVX512-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX512-NEXT: vmovd %xmm0, %ecx ; AVX512-NEXT: vmovd %xmm0, %ecx
; AVX512-NEXT: vpextrd $1, %xmm0, %eax ; AVX512-NEXT: vpextrd $1, %xmm0, %eax
Show All 10 Lines

llvm/test/CodeGen/X86/vector-half-conversions.ll

Show First 20 Lines • Show All 1,573 Lines • ▼ Show 20 Lines; ALL-NEXT: retq
%1 = fptrunc float %a0 to half %1 = fptrunc float %a0 to half
%2 = bitcast half %1 to i16 %2 = bitcast half %1 to i16
ret i16 %2 ret i16 %2
} }
define <4 x i16> @cvt_4f32_to_4i16(<4 x float> %a0) nounwind { define <4 x i16> @cvt_4f32_to_4i16(<4 x float> %a0) nounwind {
; ALL-LABEL: cvt_4f32_to_4i16: ; ALL-LABEL: cvt_4f32_to_4i16:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: shll $16, %eax
; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; ALL-NEXT: vmovd %xmm1, %ecx ; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: movzwl %cx, %ecx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: orl %eax, %ecx
; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3] ; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax ; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: shll $16, %eax ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0 ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; ALL-NEXT: vmovd %xmm0, %edx ; ALL-NEXT: vmovd %xmm0, %eax
; ALL-NEXT: movzwl %dx, %edx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: orl %eax, %edx ; ALL-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; ALL-NEXT: shlq $32, %rdx
; ALL-NEXT: orq %rcx, %rdx
; ALL-NEXT: vmovq %rdx, %xmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%1 = fptrunc <4 x float> %a0 to <4 x half> %1 = fptrunc <4 x float> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
ret <4 x i16> %2 ret <4 x i16> %2
} }
define <8 x i16> @cvt_4f32_to_8i16_undef(<4 x float> %a0) nounwind { define <8 x i16> @cvt_4f32_to_8i16_undef(<4 x float> %a0) nounwind {
; ALL-LABEL: cvt_4f32_to_8i16_undef: ; ALL-LABEL: cvt_4f32_to_8i16_undef:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: shll $16, %eax
; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; ALL-NEXT: vmovd %xmm1, %ecx ; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: movzwl %cx, %ecx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: orl %eax, %ecx
; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3] ; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax ; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: shll $16, %eax ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0 ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; ALL-NEXT: vmovd %xmm0, %edx ; ALL-NEXT: vmovd %xmm0, %eax
; ALL-NEXT: movzwl %dx, %edx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: orl %eax, %edx ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; ALL-NEXT: shlq $32, %rdx
; ALL-NEXT: orq %rcx, %rdx
; ALL-NEXT: vmovq %rdx, %xmm0
; ALL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; ALL-NEXT: retq ; ALL-NEXT: retq
%1 = fptrunc <4 x float> %a0 to <4 x half> %1 = fptrunc <4 x float> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <8 x i16> @cvt_4f32_to_8i16_zero(<4 x float> %a0) nounwind { define <8 x i16> @cvt_4f32_to_8i16_zero(<4 x float> %a0) nounwind {
; AVX1-LABEL: cvt_4f32_to_8i16_zero: ; ALL-LABEL: cvt_4f32_to_8i16_zero:
; AVX1: # %bb.0: ; ALL: # %bb.0:
; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX1-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; ALL-NEXT: vmovd %xmm1, %eax
; AVX1-NEXT: vmovd %xmm1, %eax ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: shll $16, %eax ; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX1-NEXT: vcvtps2ph $4, %xmm0, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX1-NEXT: vmovd %xmm1, %ecx ; ALL-NEXT: vmovd %xmm1, %eax
; AVX1-NEXT: movzwl %cx, %ecx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: orl %eax, %ecx ; ALL-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3] ; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX1-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; ALL-NEXT: vmovd %xmm1, %eax
; AVX1-NEXT: vmovd %xmm1, %eax ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: shll $16, %eax ; ALL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX1-NEXT: vcvtps2ph $4, %xmm0, %xmm0 ; ALL-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: vmovd %xmm0, %edx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: movzwl %dx, %edx ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: orl %eax, %edx ; ALL-NEXT: retq
; AVX1-NEXT: shlq $32, %rdx
; AVX1-NEXT: orq %rcx, %rdx
; AVX1-NEXT: vmovq %rdx, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX1-NEXT: retq
;
; AVX2-SLOW-LABEL: cvt_4f32_to_8i16_zero:
; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-SLOW-NEXT: vmovd %xmm1, %eax
; AVX2-SLOW-NEXT: shll $16, %eax
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX2-SLOW-NEXT: vmovd %xmm1, %ecx
; AVX2-SLOW-NEXT: movzwl %cx, %ecx
; AVX2-SLOW-NEXT: orl %eax, %ecx
; AVX2-SLOW-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-SLOW-NEXT: vmovd %xmm1, %eax
; AVX2-SLOW-NEXT: shll $16, %eax
; AVX2-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX2-SLOW-NEXT: vmovd %xmm0, %edx
; AVX2-SLOW-NEXT: movzwl %dx, %edx
; AVX2-SLOW-NEXT: orl %eax, %edx
; AVX2-SLOW-NEXT: shlq $32, %rdx
; AVX2-SLOW-NEXT: orq %rcx, %rdx
; AVX2-SLOW-NEXT: vmovq %rdx, %xmm0
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-SLOW-NEXT: retq
;
; AVX2-FAST-LABEL: cvt_4f32_to_8i16_zero:
; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-FAST-NEXT: vmovd %xmm1, %eax
; AVX2-FAST-NEXT: shll $16, %eax
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX2-FAST-NEXT: vmovd %xmm1, %ecx
; AVX2-FAST-NEXT: movzwl %cx, %ecx
; AVX2-FAST-NEXT: orl %eax, %ecx
; AVX2-FAST-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-FAST-NEXT: vmovd %xmm1, %eax
; AVX2-FAST-NEXT: shll $16, %eax
; AVX2-FAST-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX2-FAST-NEXT: vmovd %xmm0, %edx
; AVX2-FAST-NEXT: movzwl %dx, %edx
; AVX2-FAST-NEXT: orl %eax, %edx
; AVX2-FAST-NEXT: shlq $32, %rdx
; AVX2-FAST-NEXT: orq %rcx, %rdx
; AVX2-FAST-NEXT: vmovq %rdx, %xmm0
; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-FAST-NEXT: retq
;
; AVX512F-LABEL: cvt_4f32_to_8i16_zero:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX512F-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512F-NEXT: vmovd %xmm1, %eax
; AVX512F-NEXT: shll $16, %eax
; AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX512F-NEXT: vmovd %xmm1, %ecx
; AVX512F-NEXT: movzwl %cx, %ecx
; AVX512F-NEXT: orl %eax, %ecx
; AVX512F-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX512F-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512F-NEXT: vmovd %xmm1, %eax
; AVX512F-NEXT: shll $16, %eax
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX512F-NEXT: vmovd %xmm0, %edx
; AVX512F-NEXT: movzwl %dx, %edx
; AVX512F-NEXT: orl %eax, %edx
; AVX512F-NEXT: shlq $32, %rdx
; AVX512F-NEXT: orq %rcx, %rdx
; AVX512F-NEXT: vmovq %rdx, %xmm0
; AVX512F-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: cvt_4f32_to_8i16_zero:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX512VL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512VL-NEXT: vmovd %xmm1, %eax
; AVX512VL-NEXT: shll $16, %eax
; AVX512VL-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX512VL-NEXT: vmovd %xmm1, %ecx
; AVX512VL-NEXT: movzwl %cx, %ecx
; AVX512VL-NEXT: orl %eax, %ecx
; AVX512VL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX512VL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512VL-NEXT: vmovd %xmm1, %eax
; AVX512VL-NEXT: shll $16, %eax
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX512VL-NEXT: vmovd %xmm0, %edx
; AVX512VL-NEXT: movzwl %dx, %edx
; AVX512VL-NEXT: orl %eax, %edx
; AVX512VL-NEXT: shlq $32, %rdx
; AVX512VL-NEXT: orq %rcx, %rdx
; AVX512VL-NEXT: vmovq %rdx, %xmm0
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX512VL-NEXT: retq
%1 = fptrunc <4 x float> %a0 to <4 x half> %1 = fptrunc <4 x float> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <8 x i16> @cvt_8f32_to_8i16(<8 x float> %a0) nounwind { define <8 x i16> @cvt_8f32_to_8i16(<8 x float> %a0) nounwind {
; ALL-LABEL: cvt_8f32_to_8i16: ; ALL-LABEL: cvt_8f32_to_8i16:
▲ Show 20 Lines • Show All 294 Lines • ▼ Show 20 Lines; ALL-NEXT: retq
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* %a1 store <4 x i16> %2, <4 x i16>* %a1
ret void ret void
} }
define void @store_cvt_4f32_to_8i16_undef(<4 x float> %a0, <8 x i16>* %a1) nounwind { define void @store_cvt_4f32_to_8i16_undef(<4 x float> %a0, <8 x i16>* %a1) nounwind {
; ALL-LABEL: store_cvt_4f32_to_8i16_undef: ; ALL-LABEL: store_cvt_4f32_to_8i16_undef:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: shll $16, %eax
; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; ALL-NEXT: vmovd %xmm1, %ecx ; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: movzwl %cx, %ecx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: orl %eax, %ecx
; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3] ; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax ; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: shll $16, %eax ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; ALL-NEXT: vmovd %xmm1, %eax
; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0 ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; ALL-NEXT: vmovd %xmm0, %edx ; ALL-NEXT: vmovd %xmm0, %eax
; ALL-NEXT: movzwl %dx, %edx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; ALL-NEXT: orl %eax, %edx ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; ALL-NEXT: shlq $32, %rdx ; ALL-NEXT: vmovaps %xmm0, (%rdi)
; ALL-NEXT: orq %rcx, %rdx
; ALL-NEXT: vmovq %rdx, %xmm0
; ALL-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; ALL-NEXT: vmovdqa %xmm0, (%rdi)
; ALL-NEXT: retq ; ALL-NEXT: retq
%1 = fptrunc <4 x float> %a0 to <4 x half> %1 = fptrunc <4 x float> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i16> %3, <8 x i16>* %a1 store <8 x i16> %3, <8 x i16>* %a1
ret void ret void
} }
define void @store_cvt_4f32_to_8i16_zero(<4 x float> %a0, <8 x i16>* %a1) nounwind { define void @store_cvt_4f32_to_8i16_zero(<4 x float> %a0, <8 x i16>* %a1) nounwind {
; AVX1-LABEL: store_cvt_4f32_to_8i16_zero: ; ALL-LABEL: store_cvt_4f32_to_8i16_zero:
; AVX1: # %bb.0: ; ALL: # %bb.0:
; AVX1-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX1-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; ALL-NEXT: vmovd %xmm1, %eax
; AVX1-NEXT: vmovd %xmm1, %eax ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: shll $16, %eax ; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX1-NEXT: vcvtps2ph $4, %xmm0, %xmm1 ; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX1-NEXT: vmovd %xmm1, %ecx ; ALL-NEXT: vmovd %xmm1, %eax
; AVX1-NEXT: movzwl %cx, %ecx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: orl %eax, %ecx ; ALL-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3] ; ALL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX1-NEXT: vcvtps2ph $4, %xmm1, %xmm1 ; ALL-NEXT: vmovd %xmm1, %eax
; AVX1-NEXT: vmovd %xmm1, %eax ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: shll $16, %eax ; ALL-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX1-NEXT: vcvtps2ph $4, %xmm0, %xmm0 ; ALL-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: vmovd %xmm0, %edx ; ALL-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; AVX1-NEXT: movzwl %dx, %edx ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: orl %eax, %edx ; ALL-NEXT: vmovaps %xmm0, (%rdi)
; AVX1-NEXT: shlq $32, %rdx ; ALL-NEXT: retq
; AVX1-NEXT: orq %rcx, %rdx
; AVX1-NEXT: vmovq %rdx, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX1-NEXT: vmovdqa %xmm0, (%rdi)
; AVX1-NEXT: retq
;
; AVX2-SLOW-LABEL: store_cvt_4f32_to_8i16_zero:
; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-SLOW-NEXT: vmovd %xmm1, %eax
; AVX2-SLOW-NEXT: shll $16, %eax
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX2-SLOW-NEXT: vmovd %xmm1, %ecx
; AVX2-SLOW-NEXT: movzwl %cx, %ecx
; AVX2-SLOW-NEXT: orl %eax, %ecx
; AVX2-SLOW-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-SLOW-NEXT: vmovd %xmm1, %eax
; AVX2-SLOW-NEXT: shll $16, %eax
; AVX2-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-SLOW-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX2-SLOW-NEXT: vmovd %xmm0, %edx
; AVX2-SLOW-NEXT: movzwl %dx, %edx
; AVX2-SLOW-NEXT: orl %eax, %edx
; AVX2-SLOW-NEXT: shlq $32, %rdx
; AVX2-SLOW-NEXT: orq %rcx, %rdx
; AVX2-SLOW-NEXT: vmovq %rdx, %xmm0
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-SLOW-NEXT: vmovdqa %xmm0, (%rdi)
; AVX2-SLOW-NEXT: retq
;
; AVX2-FAST-LABEL: store_cvt_4f32_to_8i16_zero:
; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-FAST-NEXT: vmovd %xmm1, %eax
; AVX2-FAST-NEXT: shll $16, %eax
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX2-FAST-NEXT: vmovd %xmm1, %ecx
; AVX2-FAST-NEXT: movzwl %cx, %ecx
; AVX2-FAST-NEXT: orl %eax, %ecx
; AVX2-FAST-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX2-FAST-NEXT: vmovd %xmm1, %eax
; AVX2-FAST-NEXT: shll $16, %eax
; AVX2-FAST-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-FAST-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX2-FAST-NEXT: vmovd %xmm0, %edx
; AVX2-FAST-NEXT: movzwl %dx, %edx
; AVX2-FAST-NEXT: orl %eax, %edx
; AVX2-FAST-NEXT: shlq $32, %rdx
; AVX2-FAST-NEXT: orq %rcx, %rdx
; AVX2-FAST-NEXT: vmovq %rdx, %xmm0
; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-FAST-NEXT: vmovdqa %xmm0, (%rdi)
; AVX2-FAST-NEXT: retq
;
; AVX512F-LABEL: store_cvt_4f32_to_8i16_zero:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX512F-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512F-NEXT: vmovd %xmm1, %eax
; AVX512F-NEXT: shll $16, %eax
; AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX512F-NEXT: vmovd %xmm1, %ecx
; AVX512F-NEXT: movzwl %cx, %ecx
; AVX512F-NEXT: orl %eax, %ecx
; AVX512F-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX512F-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512F-NEXT: vmovd %xmm1, %eax
; AVX512F-NEXT: shll $16, %eax
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX512F-NEXT: vmovd %xmm0, %edx
; AVX512F-NEXT: movzwl %dx, %edx
; AVX512F-NEXT: orl %eax, %edx
; AVX512F-NEXT: shlq $32, %rdx
; AVX512F-NEXT: orq %rcx, %rdx
; AVX512F-NEXT: vmovq %rdx, %xmm0
; AVX512F-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512F-NEXT: vmovdqa %xmm0, (%rdi)
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: store_cvt_4f32_to_8i16_zero:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX512VL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512VL-NEXT: vmovd %xmm1, %eax
; AVX512VL-NEXT: shll $16, %eax
; AVX512VL-NEXT: vcvtps2ph $4, %xmm0, %xmm1
; AVX512VL-NEXT: vmovd %xmm1, %ecx
; AVX512VL-NEXT: movzwl %cx, %ecx
; AVX512VL-NEXT: orl %eax, %ecx
; AVX512VL-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX512VL-NEXT: vcvtps2ph $4, %xmm1, %xmm1
; AVX512VL-NEXT: vmovd %xmm1, %eax
; AVX512VL-NEXT: shll $16, %eax
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX512VL-NEXT: vmovd %xmm0, %edx
; AVX512VL-NEXT: movzwl %dx, %edx
; AVX512VL-NEXT: orl %eax, %edx
; AVX512VL-NEXT: shlq $32, %rdx
; AVX512VL-NEXT: orq %rcx, %rdx
; AVX512VL-NEXT: vmovq %rdx, %xmm0
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX512VL-NEXT: vmovdqa %xmm0, (%rdi)
; AVX512VL-NEXT: retq
%1 = fptrunc <4 x float> %a0 to <4 x half> %1 = fptrunc <4 x float> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i16> %3, <8 x i16>* %a1 store <8 x i16> %3, <8 x i16>* %a1
ret void ret void
} }
define void @store_cvt_8f32_to_8i16(<8 x float> %a0, <8 x i16>* %a1) nounwind { define void @store_cvt_8f32_to_8i16(<8 x float> %a0, <8 x i16>* %a1) nounwind {
▲ Show 20 Lines • Show All 257 Lines • ▼ Show 20 Lines; ALL-NEXT: jmp __truncdfhf2 # TAILCALL
%1 = fptrunc double %a0 to half %1 = fptrunc double %a0 to half
%2 = bitcast half %1 to i16 %2 = bitcast half %1 to i16
ret i16 %2 ret i16 %2
} }
define <2 x i16> @cvt_2f64_to_2i16(<2 x double> %a0) nounwind { define <2 x i16> @cvt_2f64_to_2i16(<2 x double> %a0) nounwind {
; ALL-LABEL: cvt_2f64_to_2i16: ; ALL-LABEL: cvt_2f64_to_2i16:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: pushq %rbx ; ALL-NEXT: subq $40, %rsp
; ALL-NEXT: subq $16, %rsp ; ALL-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; ALL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; ALL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; ALL-NEXT: callq __truncdfhf2 ; ALL-NEXT: callq __truncdfhf2
; ALL-NEXT: movl %eax, %ebx ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; ALL-NEXT: shll $16, %ebx ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; ALL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; ALL-NEXT: # xmm0 = mem[1,0]
; ALL-NEXT: callq __truncdfhf2 ; ALL-NEXT: callq __truncdfhf2
; ALL-NEXT: movzwl %ax, %eax ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; ALL-NEXT: orl %ebx, %eax ; ALL-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
; ALL-NEXT: vmovd %eax, %xmm0 ; ALL-NEXT: addq $40, %rsp
; ALL-NEXT: addq $16, %rsp
; ALL-NEXT: popq %rbx
; ALL-NEXT: retq ; ALL-NEXT: retq
%1 = fptrunc <2 x double> %a0 to <2 x half> %1 = fptrunc <2 x double> %a0 to <2 x half>
%2 = bitcast <2 x half> %1 to <2 x i16> %2 = bitcast <2 x half> %1 to <2 x i16>
ret <2 x i16> %2 ret <2 x i16> %2
} }
define <4 x i16> @cvt_4f64_to_4i16(<4 x double> %a0) nounwind { define <4 x i16> @cvt_4f64_to_4i16(<4 x double> %a0) nounwind {
; AVX1-LABEL: cvt_4f64_to_4i16: ; ALL-LABEL: cvt_4f64_to_4i16:
; AVX1: # %bb.0: ; ALL: # %bb.0:
; AVX1-NEXT: pushq %r14 ; ALL-NEXT: subq $88, %rsp
; AVX1-NEXT: pushq %rbx ; ALL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX1-NEXT: subq $40, %rsp ; ALL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; ALL-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vzeroupper
; AVX1-NEXT: vzeroupper ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: movl %eax, %ebx ; ALL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; AVX1-NEXT: shll $16, %ebx ; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: vzeroupper
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: movzwl %ax, %r14d ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: orl %ebx, %r14d ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; AVX1-NEXT: movl %eax, %ebx ; ALL-NEXT: addq $88, %rsp
; AVX1-NEXT: shll $16, %ebx ; ALL-NEXT: retq
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebx, %eax
; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %r14, %rax
; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: addq $40, %rsp
; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14
; AVX1-NEXT: retq
;
; AVX2-LABEL: cvt_4f64_to_4i16:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $40, %rsp
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r14d
; AVX2-NEXT: orl %ebx, %r14d
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebx, %eax
; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: addq $40, %rsp
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14
; AVX2-NEXT: retq
;
; AVX512-LABEL: cvt_4f64_to_4i16:
; AVX512: # %bb.0:
; AVX512-NEXT: pushq %r14
; AVX512-NEXT: pushq %rbx
; AVX512-NEXT: subq $40, %rsp
; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %r14d
; AVX512-NEXT: orl %ebx, %r14d
; AVX512-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %eax
; AVX512-NEXT: orl %ebx, %eax
; AVX512-NEXT: shlq $32, %rax
; AVX512-NEXT: orq %r14, %rax
; AVX512-NEXT: vmovq %rax, %xmm0
; AVX512-NEXT: addq $40, %rsp
; AVX512-NEXT: popq %rbx
; AVX512-NEXT: popq %r14
; AVX512-NEXT: retq
%1 = fptrunc <4 x double> %a0 to <4 x half> %1 = fptrunc <4 x double> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
ret <4 x i16> %2 ret <4 x i16> %2
} }
define <8 x i16> @cvt_4f64_to_8i16_undef(<4 x double> %a0) nounwind { define <8 x i16> @cvt_4f64_to_8i16_undef(<4 x double> %a0) nounwind {
; AVX1-LABEL: cvt_4f64_to_8i16_undef: ; ALL-LABEL: cvt_4f64_to_8i16_undef:
; AVX1: # %bb.0: ; ALL: # %bb.0:
; AVX1-NEXT: pushq %r14 ; ALL-NEXT: subq $88, %rsp
; AVX1-NEXT: pushq %rbx ; ALL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX1-NEXT: subq $40, %rsp ; ALL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; ALL-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vzeroupper
; AVX1-NEXT: vzeroupper ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: movl %eax, %ebx ; ALL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; AVX1-NEXT: shll $16, %ebx ; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: vzeroupper
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: movzwl %ax, %r14d ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: orl %ebx, %r14d ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: movl %eax, %ebx ; ALL-NEXT: addq $88, %rsp
; AVX1-NEXT: shll $16, %ebx ; ALL-NEXT: retq
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebx, %eax
; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %r14, %rax
; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX1-NEXT: addq $40, %rsp
; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14
; AVX1-NEXT: retq
;
; AVX2-LABEL: cvt_4f64_to_8i16_undef:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $40, %rsp
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %r14d
; AVX2-NEXT: orl %ebx, %r14d
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movl %eax, %ebx
; AVX2-NEXT: shll $16, %ebx
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebx, %eax
; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %r14, %rax
; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX2-NEXT: addq $40, %rsp
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14
; AVX2-NEXT: retq
;
; AVX512-LABEL: cvt_4f64_to_8i16_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: pushq %r14
; AVX512-NEXT: pushq %rbx
; AVX512-NEXT: subq $40, %rsp
; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %r14d
; AVX512-NEXT: orl %ebx, %r14d
; AVX512-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movl %eax, %ebx
; AVX512-NEXT: shll $16, %ebx
; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %eax
; AVX512-NEXT: orl %ebx, %eax
; AVX512-NEXT: shlq $32, %rax
; AVX512-NEXT: orq %r14, %rax
; AVX512-NEXT: vmovq %rax, %xmm0
; AVX512-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX512-NEXT: addq $40, %rsp
; AVX512-NEXT: popq %rbx
; AVX512-NEXT: popq %r14
; AVX512-NEXT: retq
%1 = fptrunc <4 x double> %a0 to <4 x half> %1 = fptrunc <4 x double> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <8 x i16> @cvt_4f64_to_8i16_zero(<4 x double> %a0) nounwind { define <8 x i16> @cvt_4f64_to_8i16_zero(<4 x double> %a0) nounwind {
; AVX1-LABEL: cvt_4f64_to_8i16_zero: ; ALL-LABEL: cvt_4f64_to_8i16_zero:
; AVX1: # %bb.0: ; ALL: # %bb.0:
; AVX1-NEXT: pushq %r14 ; ALL-NEXT: subq $88, %rsp
; AVX1-NEXT: pushq %rbx ; ALL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX1-NEXT: subq $40, %rsp ; ALL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; ALL-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vzeroupper
; AVX1-NEXT: vzeroupper ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: movl %eax, %ebx ; ALL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; AVX1-NEXT: shll $16, %ebx ; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: vzeroupper
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: movzwl %ax, %r14d ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: orl %ebx, %r14d ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: movl %eax, %ebx ; ALL-NEXT: addq $88, %rsp
; AVX1-NEXT: shll $16, %ebx ; ALL-NEXT: retq
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX1-NEXT: callq __truncdfhf2
; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebx, %eax
; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %r14, %rax
; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX1-NEXT: addq $40, %rsp
; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14
; AVX1-NEXT: retq
;
; AVX2-SLOW-LABEL: cvt_4f64_to_8i16_zero:
; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: pushq %r14
; AVX2-SLOW-NEXT: pushq %rbx
; AVX2-SLOW-NEXT: subq $40, %rsp
; AVX2-SLOW-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movl %eax, %ebx
; AVX2-SLOW-NEXT: shll $16, %ebx
; AVX2-SLOW-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-SLOW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movzwl %ax, %r14d
; AVX2-SLOW-NEXT: orl %ebx, %r14d
; AVX2-SLOW-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-SLOW-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movl %eax, %ebx
; AVX2-SLOW-NEXT: shll $16, %ebx
; AVX2-SLOW-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movzwl %ax, %eax
; AVX2-SLOW-NEXT: orl %ebx, %eax
; AVX2-SLOW-NEXT: shlq $32, %rax
; AVX2-SLOW-NEXT: orq %r14, %rax
; AVX2-SLOW-NEXT: vmovq %rax, %xmm0
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-SLOW-NEXT: addq $40, %rsp
; AVX2-SLOW-NEXT: popq %rbx
; AVX2-SLOW-NEXT: popq %r14
; AVX2-SLOW-NEXT: retq
;
; AVX2-FAST-LABEL: cvt_4f64_to_8i16_zero:
; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: pushq %r14
; AVX2-FAST-NEXT: pushq %rbx
; AVX2-FAST-NEXT: subq $40, %rsp
; AVX2-FAST-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-FAST-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movl %eax, %ebx
; AVX2-FAST-NEXT: shll $16, %ebx
; AVX2-FAST-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-FAST-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movzwl %ax, %r14d
; AVX2-FAST-NEXT: orl %ebx, %r14d
; AVX2-FAST-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-FAST-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-FAST-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-FAST-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movl %eax, %ebx
; AVX2-FAST-NEXT: shll $16, %ebx
; AVX2-FAST-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movzwl %ax, %eax
; AVX2-FAST-NEXT: orl %ebx, %eax
; AVX2-FAST-NEXT: shlq $32, %rax
; AVX2-FAST-NEXT: orq %r14, %rax
; AVX2-FAST-NEXT: vmovq %rax, %xmm0
; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-FAST-NEXT: addq $40, %rsp
; AVX2-FAST-NEXT: popq %rbx
; AVX2-FAST-NEXT: popq %r14
; AVX2-FAST-NEXT: retq
;
; AVX512F-LABEL: cvt_4f64_to_8i16_zero:
; AVX512F: # %bb.0:
; AVX512F-NEXT: pushq %r14
; AVX512F-NEXT: pushq %rbx
; AVX512F-NEXT: subq $40, %rsp
; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movl %eax, %ebx
; AVX512F-NEXT: shll $16, %ebx
; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %r14d
; AVX512F-NEXT: orl %ebx, %r14d
; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movl %eax, %ebx
; AVX512F-NEXT: shll $16, %ebx
; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %eax
; AVX512F-NEXT: orl %ebx, %eax
; AVX512F-NEXT: shlq $32, %rax
; AVX512F-NEXT: orq %r14, %rax
; AVX512F-NEXT: vmovq %rax, %xmm0
; AVX512F-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512F-NEXT: addq $40, %rsp
; AVX512F-NEXT: popq %rbx
; AVX512F-NEXT: popq %r14
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: cvt_4f64_to_8i16_zero:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: pushq %r14
; AVX512VL-NEXT: pushq %rbx
; AVX512VL-NEXT: subq $40, %rsp
; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movl %eax, %ebx
; AVX512VL-NEXT: shll $16, %ebx
; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %r14d
; AVX512VL-NEXT: orl %ebx, %r14d
; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movl %eax, %ebx
; AVX512VL-NEXT: shll $16, %ebx
; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %eax
; AVX512VL-NEXT: orl %ebx, %eax
; AVX512VL-NEXT: shlq $32, %rax
; AVX512VL-NEXT: orq %r14, %rax
; AVX512VL-NEXT: vmovq %rax, %xmm0
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX512VL-NEXT: addq $40, %rsp
; AVX512VL-NEXT: popq %rbx
; AVX512VL-NEXT: popq %r14
; AVX512VL-NEXT: retq
%1 = fptrunc <4 x double> %a0 to <4 x half> %1 = fptrunc <4 x double> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind { define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind {
; AVX1-LABEL: cvt_8f64_to_8i16: ; AVX1-LABEL: cvt_8f64_to_8i16:
▲ Show 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = fptrunc <4 x double> %a0 to <4 x half> %1 = fptrunc <4 x double> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* %a1 store <4 x i16> %2, <4 x i16>* %a1
ret void ret void
} }
define void @store_cvt_4f64_to_8i16_undef(<4 x double> %a0, <8 x i16>* %a1) nounwind { define void @store_cvt_4f64_to_8i16_undef(<4 x double> %a0, <8 x i16>* %a1) nounwind {
; AVX1-LABEL: store_cvt_4f64_to_8i16_undef: ; ALL-LABEL: store_cvt_4f64_to_8i16_undef:
; AVX1: # %bb.0: ; ALL: # %bb.0:
; AVX1-NEXT: pushq %rbp ; ALL-NEXT: pushq %rbx
; AVX1-NEXT: pushq %r14 ; ALL-NEXT: subq $80, %rsp
; AVX1-NEXT: pushq %rbx ; ALL-NEXT: movq %rdi, %rbx
; AVX1-NEXT: subq $32, %rsp ; ALL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX1-NEXT: movq %rdi, %r14 ; ALL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; ALL-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vzeroupper
; AVX1-NEXT: vzeroupper ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: movl %eax, %ebp ; ALL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; AVX1-NEXT: shll $16, %ebp ; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: vzeroupper
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: movzwl %ax, %ebx ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: orl %ebp, %ebx ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: movl %eax, %ebp ; ALL-NEXT: vmovaps %xmm0, (%rbx)
; AVX1-NEXT: shll $16, %ebp ; ALL-NEXT: addq $80, %rsp
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; ALL-NEXT: popq %rbx
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: retq
; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebp, %eax
; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %rbx, %rax
; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX1-NEXT: vmovdqa %xmm0, (%r14)
; AVX1-NEXT: addq $32, %rsp
; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14
; AVX1-NEXT: popq %rbp
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_cvt_4f64_to_8i16_undef:
; AVX2: # %bb.0:
; AVX2-NEXT: pushq %rbp
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $32, %rsp
; AVX2-NEXT: movq %rdi, %r14
; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movl %eax, %ebp
; AVX2-NEXT: shll $16, %ebp
; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %ebx
; AVX2-NEXT: orl %ebp, %ebx
; AVX2-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movl %eax, %ebp
; AVX2-NEXT: shll $16, %ebp
; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-NEXT: callq __truncdfhf2
; AVX2-NEXT: movzwl %ax, %eax
; AVX2-NEXT: orl %ebp, %eax
; AVX2-NEXT: shlq $32, %rax
; AVX2-NEXT: orq %rbx, %rax
; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX2-NEXT: vmovdqa %xmm0, (%r14)
; AVX2-NEXT: addq $32, %rsp
; AVX2-NEXT: popq %rbx
; AVX2-NEXT: popq %r14
; AVX2-NEXT: popq %rbp
; AVX2-NEXT: retq
;
; AVX512-LABEL: store_cvt_4f64_to_8i16_undef:
; AVX512: # %bb.0:
; AVX512-NEXT: pushq %rbp
; AVX512-NEXT: pushq %r14
; AVX512-NEXT: pushq %rbx
; AVX512-NEXT: subq $32, %rsp
; AVX512-NEXT: movq %rdi, %r14
; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movl %eax, %ebp
; AVX512-NEXT: shll $16, %ebp
; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %ebx
; AVX512-NEXT: orl %ebp, %ebx
; AVX512-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movl %eax, %ebp
; AVX512-NEXT: shll $16, %ebp
; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512-NEXT: callq __truncdfhf2
; AVX512-NEXT: movzwl %ax, %eax
; AVX512-NEXT: orl %ebp, %eax
; AVX512-NEXT: shlq $32, %rax
; AVX512-NEXT: orq %rbx, %rax
; AVX512-NEXT: vmovq %rax, %xmm0
; AVX512-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX512-NEXT: vmovdqa %xmm0, (%r14)
; AVX512-NEXT: addq $32, %rsp
; AVX512-NEXT: popq %rbx
; AVX512-NEXT: popq %r14
; AVX512-NEXT: popq %rbp
; AVX512-NEXT: retq
%1 = fptrunc <4 x double> %a0 to <4 x half> %1 = fptrunc <4 x double> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i16> %3, <8 x i16>* %a1 store <8 x i16> %3, <8 x i16>* %a1
ret void ret void
} }
define void @store_cvt_4f64_to_8i16_zero(<4 x double> %a0, <8 x i16>* %a1) nounwind { define void @store_cvt_4f64_to_8i16_zero(<4 x double> %a0, <8 x i16>* %a1) nounwind {
; AVX1-LABEL: store_cvt_4f64_to_8i16_zero: ; ALL-LABEL: store_cvt_4f64_to_8i16_zero:
; AVX1: # %bb.0: ; ALL: # %bb.0:
; AVX1-NEXT: pushq %rbp ; ALL-NEXT: pushq %rbx
; AVX1-NEXT: pushq %r14 ; ALL-NEXT: subq $80, %rsp
; AVX1-NEXT: pushq %rbx ; ALL-NEXT: movq %rdi, %rbx
; AVX1-NEXT: subq $32, %rsp ; ALL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX1-NEXT: movq %rdi, %r14 ; ALL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill ; ALL-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: vzeroupper
; AVX1-NEXT: vzeroupper ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: movl %eax, %ebp ; ALL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; AVX1-NEXT: shll $16, %ebp ; ALL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: vzeroupper
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: movzwl %ax, %ebx ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: orl %ebp, %ebx ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; ALL-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill ; ALL-NEXT: # xmm0 = mem[1,0]
; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] ; ALL-NEXT: callq __truncdfhf2
; AVX1-NEXT: vzeroupper ; ALL-NEXT: movw %ax, {{[0-9]+}}(%rsp)
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: movl %eax, %ebp ; ALL-NEXT: vmovaps %xmm0, (%rbx)
; AVX1-NEXT: shll $16, %ebp ; ALL-NEXT: addq $80, %rsp
; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; ALL-NEXT: popq %rbx
; AVX1-NEXT: callq __truncdfhf2 ; ALL-NEXT: retq
; AVX1-NEXT: movzwl %ax, %eax
; AVX1-NEXT: orl %ebp, %eax
; AVX1-NEXT: shlq $32, %rax
; AVX1-NEXT: orq %rbx, %rax
; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX1-NEXT: vmovdqa %xmm0, (%r14)
; AVX1-NEXT: addq $32, %rsp
; AVX1-NEXT: popq %rbx
; AVX1-NEXT: popq %r14
; AVX1-NEXT: popq %rbp
; AVX1-NEXT: retq
;
; AVX2-SLOW-LABEL: store_cvt_4f64_to_8i16_zero:
; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: pushq %rbp
; AVX2-SLOW-NEXT: pushq %r14
; AVX2-SLOW-NEXT: pushq %rbx
; AVX2-SLOW-NEXT: subq $32, %rsp
; AVX2-SLOW-NEXT: movq %rdi, %r14
; AVX2-SLOW-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movl %eax, %ebp
; AVX2-SLOW-NEXT: shll $16, %ebp
; AVX2-SLOW-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-SLOW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movzwl %ax, %ebx
; AVX2-SLOW-NEXT: orl %ebp, %ebx
; AVX2-SLOW-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-SLOW-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-SLOW-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movl %eax, %ebp
; AVX2-SLOW-NEXT: shll $16, %ebp
; AVX2-SLOW-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-SLOW-NEXT: callq __truncdfhf2
; AVX2-SLOW-NEXT: movzwl %ax, %eax
; AVX2-SLOW-NEXT: orl %ebp, %eax
; AVX2-SLOW-NEXT: shlq $32, %rax
; AVX2-SLOW-NEXT: orq %rbx, %rax
; AVX2-SLOW-NEXT: vmovq %rax, %xmm0
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-SLOW-NEXT: vmovdqa %xmm0, (%r14)
; AVX2-SLOW-NEXT: addq $32, %rsp
; AVX2-SLOW-NEXT: popq %rbx
; AVX2-SLOW-NEXT: popq %r14
; AVX2-SLOW-NEXT: popq %rbp
; AVX2-SLOW-NEXT: retq
;
; AVX2-FAST-LABEL: store_cvt_4f64_to_8i16_zero:
; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: pushq %rbp
; AVX2-FAST-NEXT: pushq %r14
; AVX2-FAST-NEXT: pushq %rbx
; AVX2-FAST-NEXT: subq $32, %rsp
; AVX2-FAST-NEXT: movq %rdi, %r14
; AVX2-FAST-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX2-FAST-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movl %eax, %ebp
; AVX2-FAST-NEXT: shll $16, %ebp
; AVX2-FAST-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX2-FAST-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movzwl %ax, %ebx
; AVX2-FAST-NEXT: orl %ebp, %ebx
; AVX2-FAST-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX2-FAST-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-FAST-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX2-FAST-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movl %eax, %ebp
; AVX2-FAST-NEXT: shll $16, %ebp
; AVX2-FAST-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX2-FAST-NEXT: callq __truncdfhf2
; AVX2-FAST-NEXT: movzwl %ax, %eax
; AVX2-FAST-NEXT: orl %ebp, %eax
; AVX2-FAST-NEXT: shlq $32, %rax
; AVX2-FAST-NEXT: orq %rbx, %rax
; AVX2-FAST-NEXT: vmovq %rax, %xmm0
; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-FAST-NEXT: vmovdqa %xmm0, (%r14)
; AVX2-FAST-NEXT: addq $32, %rsp
; AVX2-FAST-NEXT: popq %rbx
; AVX2-FAST-NEXT: popq %r14
; AVX2-FAST-NEXT: popq %rbp
; AVX2-FAST-NEXT: retq
;
; AVX512F-LABEL: store_cvt_4f64_to_8i16_zero:
; AVX512F: # %bb.0:
; AVX512F-NEXT: pushq %rbp
; AVX512F-NEXT: pushq %r14
; AVX512F-NEXT: pushq %rbx
; AVX512F-NEXT: subq $32, %rsp
; AVX512F-NEXT: movq %rdi, %r14
; AVX512F-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movl %eax, %ebp
; AVX512F-NEXT: shll $16, %ebp
; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %ebx
; AVX512F-NEXT: orl %ebp, %ebx
; AVX512F-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512F-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movl %eax, %ebp
; AVX512F-NEXT: shll $16, %ebp
; AVX512F-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512F-NEXT: callq __truncdfhf2
; AVX512F-NEXT: movzwl %ax, %eax
; AVX512F-NEXT: orl %ebp, %eax
; AVX512F-NEXT: shlq $32, %rax
; AVX512F-NEXT: orq %rbx, %rax
; AVX512F-NEXT: vmovq %rax, %xmm0
; AVX512F-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX512F-NEXT: vmovdqa %xmm0, (%r14)
; AVX512F-NEXT: addq $32, %rsp
; AVX512F-NEXT: popq %rbx
; AVX512F-NEXT: popq %r14
; AVX512F-NEXT: popq %rbp
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: store_cvt_4f64_to_8i16_zero:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: pushq %rbp
; AVX512VL-NEXT: pushq %r14
; AVX512VL-NEXT: pushq %rbx
; AVX512VL-NEXT: subq $32, %rsp
; AVX512VL-NEXT: movq %rdi, %r14
; AVX512VL-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movl %eax, %ebp
; AVX512VL-NEXT: shll $16, %ebp
; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %ebx
; AVX512VL-NEXT: orl %ebp, %ebx
; AVX512VL-NEXT: vmovupd (%rsp), %ymm0 # 32-byte Reload
; AVX512VL-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; AVX512VL-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movl %eax, %ebp
; AVX512VL-NEXT: shll $16, %ebp
; AVX512VL-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX512VL-NEXT: callq __truncdfhf2
; AVX512VL-NEXT: movzwl %ax, %eax
; AVX512VL-NEXT: orl %ebp, %eax
; AVX512VL-NEXT: shlq $32, %rax
; AVX512VL-NEXT: orq %rbx, %rax
; AVX512VL-NEXT: vmovq %rax, %xmm0
; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,4,5,6,7],zero,zero,zero,zero,zero,zero,zero,zero
; AVX512VL-NEXT: vmovdqa %xmm0, (%r14)
; AVX512VL-NEXT: addq $32, %rsp
; AVX512VL-NEXT: popq %rbx
; AVX512VL-NEXT: popq %r14
; AVX512VL-NEXT: popq %rbp
; AVX512VL-NEXT: retq
%1 = fptrunc <4 x double> %a0 to <4 x half> %1 = fptrunc <4 x double> %a0 to <4 x half>
%2 = bitcast <4 x half> %1 to <4 x i16> %2 = bitcast <4 x half> %1 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <4 x i16> %2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i16> %3, <8 x i16>* %a1 store <8 x i16> %3, <8 x i16>* %a1
ret void ret void
} }
define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind { define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind {
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