[AMDGPU] Fixed addReg() in SIOptimizeExecMaskingPreRA.cpp

[rampitec]

Summary

The second argument is flags, not subreg.

[msearles]

LGTM

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB,
   LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t'
                     << *Cmp << '\t' << *And);
 
   unsigned CCReg = CC->getReg();
   LIS->RemoveMachineInstrFromMaps(*And);
   MachineInstr *Andn2 = BuildMI(MBB, *And, And->getDebugLoc(),
                                 TII->get(Andn2Opc), And->getOperand(0).getReg())
                             .addReg(ExecReg)
-                            .addReg(CCReg, CC->getSubReg());
+                            .addReg(CCReg, 0, CC->getSubReg());
   And->eraseFromParent();
   LIS->InsertMachineInstrInMaps(*Andn2);
 
   LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
 
   // Try to remove compare. Cmp value should not used in between of cmp
   // and s_and_b64 if VCC or just unused if any other register.
   if ((TargetRegisterInfo::isVirtualRegister(CmpReg) &&

test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

bb.2:
     S_BRANCH %bb.3
 
   bb.3:
     S_BRANCH %bb.2
 
   bb.4:
     S_ENDPGM 0
 ...
+
+# GCN: name: negated_cond_subreg
+# GCN:      %0.sub0_sub1:sreg_128 = IMPLICIT_DEF
+# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0.sub0_sub1, implicit-def $scc
+# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
+---
+name:            negated_cond_subreg
+body:             |
+  bb.0:
+    %0.sub0_sub1:sreg_128 = IMPLICIT_DEF
+    %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0.sub0_sub1, implicit $exec
+    %2.sub0_sub1:sreg_128 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
+    $vcc = S_AND_B64 $exec, killed %2.sub0_sub1:sreg_128, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
+    S_BRANCH %bb.1
+
+  bb.1:
+    S_BRANCH %bb.0
+
+  bb.2:
+    S_ENDPGM 0
+...