[WebAssembly] Bail out of fastisel earlier when computing PIC addresses

[sbc100]

Summary

This change partially reverts https://reviews.llvm.org/D54647 in favor
of bailing out during computeAddress instead.

This catches the condition earlier and handles more cases.

[sbc100]

I have a test case that this fixes, that I'm currently trying to reduce.

[dschuff]

LGTM

llvm/trunk/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

case MVT::v2f64:
         return VT;
       break;
     default:
       break;
     }
     return MVT::INVALID_SIMPLE_VALUE_TYPE;
   }
   bool computeAddress(const Value *Obj, Address &Addr);
-  bool materializeLoadStoreOperands(Address &Addr);
+  void materializeLoadStoreOperands(Address &Addr);
   void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
                             MachineMemOperand *MMO);
   unsigned maskI1Value(unsigned Reg, const Value *V);
   unsigned getRegForI1Value(const Value *V, bool &Not);
   unsigned zeroExtendToI32(unsigned Reg, const Value *V,
                            MVT::SimpleValueType From);
   unsigned signExtendToI32(unsigned Reg, const Value *V,
                            MVT::SimpleValueType From);
public:
   bool fastSelectInstruction(const Instruction *I) override;
 
 #include "WebAssemblyGenFastISel.inc"
 };
 
 } // end anonymous namespace
 
 bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
-
   const User *U = nullptr;
   unsigned Opcode = Instruction::UserOp1;
   if (const auto *I = dyn_cast<Instruction>(Obj)) {
     // Don't walk into other basic blocks unless the object is an alloca from
     // another block, otherwise it may not have a virtual register assigned.
     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
         FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
       Opcode = I->getOpcode();
       U = I;
     }
   } else if (const auto *C = dyn_cast<ConstantExpr>(Obj)) {
     Opcode = C->getOpcode();
     U = C;
   }
 
   if (auto *Ty = dyn_cast<PointerType>(Obj->getType()))
     if (Ty->getAddressSpace() > 255)
       // Fast instruction selection doesn't support the special
       // address spaces.
       return false;
 
   if (const auto *GV = dyn_cast<GlobalValue>(Obj)) {
+    if (TLI.isPositionIndependent())
+      return false;
     if (Addr.getGlobalValue())
       return false;
     Addr.setGlobalValue(GV);
     return true;
   }
 
   switch (Opcode) {
   default:
bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
   }
   unsigned Reg = getRegForValue(Obj);
   if (Reg == 0)
     return false;
   Addr.setReg(Reg);
   return Addr.getReg() != 0;
 }
 
-bool WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
+void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
   if (Addr.isRegBase()) {
     unsigned Reg = Addr.getReg();
     if (Reg == 0) {
-      const GlobalValue *GV = Addr.getGlobalValue();
-      if (GV && TLI.isPositionIndependent())
-        return false;
       Reg = createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
                                                    : &WebAssembly::I32RegClass);
       unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
                                             : WebAssembly::CONST_I32;
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
           .addImm(0);
       Addr.setReg(Reg);
     }
   }
-  return true;
 }
 
 void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
                                                const MachineInstrBuilder &MIB,
                                                MachineMemOperand *MMO) {
   // Set the alignment operand (this is rewritten in SetP2AlignOperands).
   // TODO: Disable SetP2AlignOperands for FastISel and just do it here.
   MIB.addImm(0);
bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
   case MVT::f64:
     Opc = WebAssembly::LOAD_F64;
     RC = &WebAssembly::F64RegClass;
     break;
   default:
     return false;
   }
 
-  if (!materializeLoadStoreOperands(Addr))
-    return false;
+  materializeLoadStoreOperands(Addr);
 
   unsigned ResultReg = createResultReg(RC);
   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
                      ResultReg);
 
   addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load));
 
   updateValueMap(Load, ResultReg);
case MVT::f32:
     break;
   case MVT::f64:
     Opc = WebAssembly::STORE_F64;
     break;
   default:
     return false;
   }
 
-  if (!materializeLoadStoreOperands(Addr))
-    return false;
+  materializeLoadStoreOperands(Addr);
 
   unsigned ValueReg = getRegForValue(Store->getValueOperand());
   if (ValueReg == 0)
     return false;
   if (VTIsi1)
     ValueReg = maskI1Value(ValueReg, Store->getValueOperand());
 
   auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));