Add a getSizeInBits() accessor to MachineMemOperand. NFC.

[aemerson]

Summary

Cleans up a bunch of places where we do getSize() * 8.

[dsanders]

LGTM

[arsenm]

llvm/lib/CodeGen/MachineVerifier.cpp

1028 ↗

(On Diff #195472)

The +7 / 8 trick should probably be moved into a ValTy.getSizeInBytes()

[aemerson]

llvm/lib/CodeGen/MachineVerifier.cpp

1028 ↗

(On Diff #195472)

I'll do this when I commit.

llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

case GIM_CheckMemorySizeGreaterThanLLT: {
           return false;
         break;
       }
 
       MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
 
       unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
       if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
-          MMO->getSize() * 8 != Size) {
+          MMO->getSizeInBits() != Size) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
-                 MMO->getSize() * 8 >= Size) {
+                 MMO->getSizeInBits() >= Size) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
-                 MMO->getSize() * 8 <= Size)
+                 MMO->getSizeInBits() <= Size)
         if (handleReject() == RejectAndGiveUp)
           return false;
 
       break;
     }
     case GIM_CheckType: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];

llvm/trunk/include/llvm/CodeGen/MachineMemOperand.h

public:
   /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
   int64_t getOffset() const { return PtrInfo.Offset; }
 
   unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
 
   /// Return the size in bytes of the memory reference.
   uint64_t getSize() const { return Size; }
 
+  /// Return the size in bits of the memory reference.
+  uint64_t getSizeInBits() const { return Size * 8; }
+
   /// Return the minimum known alignment in bytes of the actual memory
   /// reference.
   uint64_t getAlignment() const;
 
   /// Return the minimum known alignment in bytes of the base address, without
   /// the offset.
   uint64_t getBaseAlignment() const { return (1u << BaseAlignLog2) >> 1; }
 

llvm/trunk/include/llvm/Support/LowLevelTypeImpl.h

public:
 
   /// Returns the total size of the type. Must only be called on sized types.
   unsigned getSizeInBits() const {
     if (isPointer() || isScalar())
       return getScalarSizeInBits();
     return getScalarSizeInBits() * getNumElements();
   }
 
+  /// Returns the total size of the type in bytes, i.e. number of whole bytes
+  /// needed to represent the size in bits. Must only be called on sized types.
+  unsigned getSizeInBytes() const {
+    return (getSizeInBits() + 7) / 8;
+  }
+
   LLT getScalarType() const {
     return isVector() ? getElementType() : *this;
   }
 
   /// If this type is a vector, return a vector with the same number of elements
   /// but the new element type. Otherwise, return the new element type.
   LLT changeElementType(LLT NewEltTy) const {
     return isVector() ? LLT::vector(getNumElements(), NewEltTy) : NewEltTy;

llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
   case TargetOpcode::G_ZEXTLOAD:
   case TargetOpcode::G_SEXTLOAD: {
     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
     unsigned DstReg = MI.getOperand(0).getReg();
     unsigned PtrReg = MI.getOperand(1).getReg();
 
     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
     auto &MMO = **MI.memoperands_begin();
-    if (MMO.getSize() * 8 == NarrowSize) {
+    if (MMO.getSizeInBits() == NarrowSize) {
       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
     } else {
       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
         : TargetOpcode::G_SEXTLOAD;
       MIRBuilder.buildInstr(ExtLoad)
         .addDef(TmpReg)
         .addUse(PtrReg)
         .addMemOperand(&MMO);
LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD: {
     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
     unsigned DstReg = MI.getOperand(0).getReg();
     unsigned PtrReg = MI.getOperand(1).getReg();
     LLT DstTy = MRI.getType(DstReg);
     auto &MMO = **MI.memoperands_begin();
 
-    if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
+    if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
         // This load needs splitting into power of 2 sized loads.
         if (DstTy.isVector())
           return UnableToLegalize;
         if (isPowerOf2_32(DstTy.getSizeInBits()))
           return UnableToLegalize; // Don't know what we're being asked to do.
 
         // Our strategy here is to generate anyextending loads for the smaller
if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
         return Legalized;
       }
       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
       MI.eraseFromParent();
       return Legalized;
     }
 
     if (DstTy.isScalar()) {
-      unsigned TmpReg = MRI.createGenericVirtualRegister(
-          LLT::scalar(MMO.getSize() /* in bytes */ * 8));
+      unsigned TmpReg =
+          MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
       switch (MI.getOpcode()) {
       default:
         llvm_unreachable("Unexpected opcode");
       case TargetOpcode::G_LOAD:
         MIRBuilder.buildAnyExt(DstReg, TmpReg);
         break;
       case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_STORE: {
     // We do this by first extending the stored value to the next largest power
     // of 2 type, and then using truncating stores to store the components.
     // By doing this, likewise with G_LOAD, generate an extend that can be
     // artifact-combined away instead of leaving behind extracts.
     unsigned SrcReg = MI.getOperand(0).getReg();
     unsigned PtrReg = MI.getOperand(1).getReg();
     LLT SrcTy = MRI.getType(SrcReg);
     MachineMemOperand &MMO = **MI.memoperands_begin();
-    if (SrcTy.getSizeInBits() != MMO.getSize() /* in bytes */ * 8)
+    if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
       return UnableToLegalize;
     if (SrcTy.isVector())
       return UnableToLegalize;
     if (isPowerOf2_32(SrcTy.getSizeInBits()))
       return UnableToLegalize; // Don't know what we're being asked to do.
 
     // Extend to the next pow-2.
     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

case TargetOpcode::G_SEXTLOAD: {
     // describing that access.
     if (!MI->hasOneMemOperand()) {
       report("Generic instruction accessing memory must have one mem operand",
              MI);
     } else {
       const MachineMemOperand &MMO = **MI->memoperands_begin();
       if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
           MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
-        if (MMO.getSize() * 8 >= ValTy.getSizeInBits())
+        if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
           report("Generic extload must have a narrower memory type", MI);
       } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
-        if (MMO.getSize() > (ValTy.getSizeInBits() + 7) / 8)
+        if (MMO.getSize() > ValTy.getSizeInBytes())
           report("load memory size cannot exceed result size", MI);
       } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
-        if ((ValTy.getSizeInBits() + 7) / 8 < MMO.getSize())
+        if (ValTy.getSizeInBytes() < MMO.getSize())
           report("store memory size cannot exceed value size", MI);
       }
     }
 
     break;
   }
   case TargetOpcode::G_PHI: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());