[ARM] Don't replicate instructions in Ifcvt at minsize

[dmgreen]

Summary

Ifcvt can replicate instructions as it converts them to be predicated. This stops that from happening at minsize.

Test is new, just showing the differences here for clarity.

[efriedma]

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

1939 ↗

(On Diff #193148)

Maybe explain why this increases codesize in a comment. I guess the issue here is that if a block has multiple predecessors, you essentially have to clone it, then if-convert the clone? (Theoretically, if we if-convert all the predecessors, it could actually save codesize, but I guess that's unlikely to come up in practice.)

llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll

17 ↗

(On Diff #193148)

The testcases don't really seem to demonstrate the point of this... yes, you're saving two bytes, but only because we can use cbz here.

48 ↗

(On Diff #193148)

I guess this is sort of orthogonal to your patch, but why aren't we generating "pop {r7, pc}" here?

[dmgreen]

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

1939 ↗

(On Diff #193148)

I kind of forgot about A32 code. I've made this T32 only and updated the comment.

From what I've seen, we usually trade a branch for a IT block, so the cloning comes out as a negative.

llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll

17 ↗

(On Diff #193148)

Oh yeah. Block placement is duplicating certain instructions it shouldn't too. It gets a taildup limit of 1, which in these situations where you don't get a fallthrough makes things worse.

I tried just turning that off, (putting the limit down to 0 at minsize) but that makes things larger in places.

CBZ's are a part of what makes this better, but I've added a new test that compares against 1

48 ↗

(On Diff #193148)

Yet another things that isn't tuned for minsize...

[dmgreen]

ping

[efriedma]

LGTM

[dmgreen]

Thanks Eli

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

 isProfitableToIfCvt(MachineBasicBlock &TBB,
                     unsigned TCycles, unsigned TExtra,
                     MachineBasicBlock &FBB,
                     unsigned FCycles, unsigned FExtra,
                     BranchProbability Probability) const {
   if (!TCycles)
     return false;
 
+  // In thumb code we often end up trading one branch for a IT block, and
+  // if we are cloning the instruction can increase code size. Prevent
+  // blocks with multiple predecesors from being ifcvted to prevent this
+  // cloning.
+  if (Subtarget.isThumb2() && TBB.getParent()->getFunction().hasMinSize()) {
+    if (TBB.pred_size() != 1 || FBB.pred_size() != 1)
+      return false;
+  }
+
   // Attempt to estimate the relative costs of predication versus branching.
   // Here we scale up each component of UnpredCost to avoid precision issue when
   // scaling TCycles/FCycles by Probability.
   const unsigned ScalingUpFactor = 1024;
 
   unsigned PredCost = (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor;
   unsigned UnpredCost;
   if (!Subtarget.hasBranchPredictor()) {

llvm/trunk/test/CodeGen/Thumb2/ifcvt-minsize.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8m.main-none-none-eabi %s -o - -verify-machineinstrs | FileCheck %s
+
+declare i32 @fn(i32) #0
+
+define i32 @f1(i32 %a) #0 {
+; CHECK-LABEL: f1:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    bl fn
+; CHECK-NEXT:    movs r0, #0
+; CHECK-NEXT:    cbz r4, .LBB0_2
+; CHECK-NEXT:  @ %bb.1: @ %return
+; CHECK-NEXT:    pop {r4, pc}
+; CHECK-NEXT:  .LBB0_2: @ %if.end
+; CHECK-NEXT:    bl fn
+; CHECK-NEXT:    adds r0, #1
+; CHECK-NEXT:    pop {r4, pc}
+entry:
+  %call = tail call i32 @fn(i32 %a) #2
+  %tobool = icmp eq i32 %a, 0
+  br i1 %tobool, label %if.end, label %return
+
+if.end:                                           ; preds = %entry
+  %call1 = tail call i32 @fn(i32 0) #2
+  %add = add nsw i32 %call1, 1
+  br label %return
+
+return:                                           ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add, %if.end ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define i32 @f2(i32 %a) #0 {
+; CHECK-LABEL: f2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    mov r4, r0
+; CHECK-NEXT:    bl fn
+; CHECK-NEXT:    movs r0, #0
+; CHECK-NEXT:    cmp r4, #1
+; CHECK-NEXT:    bne .LBB1_2
+; CHECK-NEXT:  @ %bb.1: @ %if.end
+; CHECK-NEXT:    bl fn
+; CHECK-NEXT:    adds r0, #1
+; CHECK-NEXT:  .LBB1_2: @ %return
+; CHECK-NEXT:    pop {r4, pc}
+entry:
+  %call = tail call i32 @fn(i32 %a) #2
+  %tobool = icmp eq i32 %a, 1
+  br i1 %tobool, label %if.end, label %return
+
+if.end:                                           ; preds = %entry
+  %call1 = tail call i32 @fn(i32 0) #2
+  %add = add nsw i32 %call1, 1
+  br label %return
+
+return:                                           ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add, %if.end ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define void @f3(i32 %x) #0 {
+; CHECK-LABEL: f3:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    cmp r0, #1
+; CHECK-NEXT:    bne .LBB2_2
+; CHECK-NEXT:  @ %bb.1: @ %t
+; CHECK-NEXT:    .save {r7, lr}
+; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    movs r0, #0
+; CHECK-NEXT:    bl fn
+; CHECK-NEXT:    pop.w {r7, lr}
+; CHECK-NEXT:  .LBB2_2: @ %f
+; CHECK-NEXT:    bx lr
+entry:
+  %p = icmp eq i32 %x, 1
+  br i1 %p, label %t, label %f
+
+t:
+  call i32 @fn(i32 0)
+  br label %f
+
+f:
+  ret void
+}
+
+attributes #0 = { minsize nounwind optsize }
+