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Differential D60071

[AMDGPU] Add more test cases of D59608.
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Authored by hliao on Apr 1 2019, 9:10 AM.

Details

Reviewers
arsenm
Commits
rG9bef688bc29f: [AMDGPU] Add more test cases of D59608.
rL357442: [AMDGPU] Add more test cases of D59608.
Summary
  • Add more test cases.

Diff Detail

Event Timeline

hliao created this revision.Apr 1 2019, 9:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 1 2019, 9:10 AM
Herald added subscribers: llvm-commits, t-tye, tpr and 6 others. · View Herald Transcript
Harbormaster completed remote builds in B29899: Diff 193104.Apr 1 2019, 9:10 AM
arsenm added a comment.Apr 1 2019, 9:19 AM

Missing the DS addressing mode ones

hliao updated this revision to Diff 193153.Apr 1 2019, 12:40 PM

Add tests for DS addressing mode.

Harbormaster completed remote builds in B29926: Diff 193153.Apr 1 2019, 12:45 PM
arsenm added inline comments.Apr 1 2019, 1:11 PM
llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
3

You can just use the same run line. +unsafe-ds-offset-folding is only needed for SI

hliao updated this revision to Diff 193166.Apr 1 2019, 1:21 PM

revise more

Harbormaster completed remote builds in B29927: Diff 193166.Apr 1 2019, 1:21 PM
hliao updated this revision to Diff 193167.Apr 1 2019, 1:23 PM

more revising

Harbormaster completed remote builds in B29928: Diff 193167.Apr 1 2019, 1:25 PM
arsenm added inline comments.Apr 1 2019, 5:03 PM
llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
25–27

You don't need the new, special label for this

hliao marked an inline comment as done.Apr 1 2019, 5:18 PM
hliao added inline comments.
llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
25–27

Won't be better to give more clear hint on why that test is added?

arsenm added inline comments.Apr 1 2019, 5:24 PM
llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
25–27

That's what a comment is for. Adding more labels just complicates the test

hliao updated this revision to Diff 193207.Apr 1 2019, 5:29 PM

revise again

Harbormaster completed remote builds in B29935: Diff 193207.Apr 1 2019, 5:30 PM
arsenm accepted this revision.Apr 1 2019, 5:33 PM

LGTM

This revision is now accepted and ready to land.Apr 1 2019, 5:33 PM
Closed by commit rL357442: [AMDGPU] Add more test cases of D59608. (authored by hliao). · Explain WhyApr 1 2019, 5:35 PM
This revision was automatically updated to reflect the committed changes.
hliao added a comment.Apr 1 2019, 5:35 PM
In D60071#1450787, @arsenm wrote:

LGTM

don't forget accept the original review, :)

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
33 lines
27 lines
51 lines

Diff 193153

llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+unsafe-ds-offset-folding -verify-machineinstrs < %s | FileCheck -check-prefixes=CLAMPBIT %s
arsenmUnsubmitted
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You can just use the same run line. +unsafe-ds-offset-folding is only needed for SI

arsenm: You can just use the same run line. +unsafe-ds-offset-folding is only needed for SI
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
@lds.obj = addrspace(3) global [256 x i32] undef, align 4 @lds.obj = addrspace(3) global [256 x i32] undef, align 4
; GCN-LABEL: {{^}}write_ds_sub0_offset0_global: ; GCN-LABEL: {{^}}write_ds_sub0_offset0_global:
; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0
; CI: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]] ; CI: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]]
; GFX9: v_sub_u32_e32 [[BASEPTR:v[0-9]+]], 0, [[SHL]] ; GFX9: v_sub_u32_e32 [[BASEPTR:v[0-9]+]], 0, [[SHL]]
; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b ; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b
; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12 ; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12
define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 { define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 {
entry: entry:
%x.i = call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
%sub1 = sub i32 0, %x.i %sub1 = sub i32 0, %x.i
%tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1 %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
%arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3 %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
store i32 123, i32 addrspace(3)* %arrayidx store i32 123, i32 addrspace(3)* %arrayidx
ret void ret void
} }
; CLAMPBIT-LABEL: {{^}}write_ds_sub0_offset0_global_clamp_bit:
; CLAMPBIT: v_sub_u32
; CLAMPBIT: s_endpgm
arsenmUnsubmitted
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You don't need the new, special label for this

arsenm: You don't need the new, special label for this
hliaoAuthorUnsubmitted
Done
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Won't be better to give more clear hint on why that test is added?

hliao: Won't be better to give more clear hint on why that test is added?
arsenmUnsubmitted
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That's what a comment is for. Adding more labels just complicates the test

arsenm: That's what a comment is for. Adding more labels just complicates the test
define amdgpu_kernel void @write_ds_sub0_offset0_global_clamp_bit(float %dummy.val) #0 {
entry:
%x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
%sub1 = sub i32 0, %x.i
%tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
%arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
store i32 123, i32 addrspace(3)* %arrayidx
%fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
store volatile float %fmas, float addrspace(1)* null
ret void
}
; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset: ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]]
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535 ; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535
define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 { define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 {
%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 {
%neg = sub i32 0, %x.i %neg = sub i32 0, %x.i
%shl = shl i32 %neg, 2 %shl = shl i32 %neg, 2
%add = add i32 1019, %shl %add = add i32 1019, %shl
%ptr = inttoptr i32 %add to i64 addrspace(3)* %ptr = inttoptr i32 %add to i64 addrspace(3)*
store i64 123, i64 addrspace(3)* %ptr, align 4 store i64 123, i64 addrspace(3)* %ptr, align 4
ret void ret void
} }
; CLAMPBIT-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset:
; CLAMPBIT: v_sub_u32
; CLAMPBIT: s_endpgm
define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit(float %dummy.val) #1 {
%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
%neg = sub i32 0, %x.i
%shl = shl i32 %neg, 2
%add = add i32 1019, %shl
%ptr = inttoptr i32 %add to i64 addrspace(3)*
store i64 123, i64 addrspace(3)* %ptr, align 4
%fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
store volatile float %fmas, float addrspace(1)* null
ret void
}
; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1: ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]] ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]] ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]]
; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}} ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}
define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 { define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 {
%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
%neg = sub i32 0, %x.i %neg = sub i32 0, %x.i
%shl = shl i32 %neg, 2 %shl = shl i32 %neg, 2
%add = add i32 1020, %shl %add = add i32 1020, %shl
%ptr = inttoptr i32 %add to i64 addrspace(3)* %ptr = inttoptr i32 %add to i64 addrspace(3)*
store i64 123, i64 addrspace(3)* %ptr, align 4 store i64 123, i64 addrspace(3)* %ptr, align 4
ret void ret void
} }
declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1)
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }
attributes #2 = { nounwind convergent } attributes #2 = { nounwind convergent }

llvm/test/CodeGen/AMDGPU/uaddo.ll

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
exit: exit:
%cout = phi i1 [false, %entry], [%c2, %if] %cout = phi i1 [false, %entry], [%c2, %if]
store i32 %val, i32 addrspace(1)* %out, align 4 store i32 %val, i32 addrspace(1)* %out, align 4
store i1 %cout, i1 addrspace(1)* %carryout store i1 %cout, i1 addrspace(1)* %carryout
ret void ret void
} }
; FUNC-LABEL: {{^}}v_uaddo_clamp_bit:
; GCN: v_add_{{i|u|co_u}}32_e64
; GCN: s_endpgm
define amdgpu_kernel void @v_uaddo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
%a = load i32, i32 addrspace(1)* %a.gep
%b = load i32, i32 addrspace(1)* %b.gep
%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue { i32, i1 } %uadd, 0
%carry = extractvalue { i32, i1 } %uadd, 1
%c2 = icmp eq i1 %carry, false
%cc = icmp eq i32 %a, %b
br i1 %cc, label %exit, label %if
if:
br label %exit
exit:
%cout = phi i1 [false, %entry], [%c2, %if]
store i32 %val, i32 addrspace(1)* %out, align 4
store i1 %cout, i1 addrspace(1)* %carryout
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1 declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #1 declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #1
declare { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32>, <2 x i32>) nounwind readnone declare { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

llvm/test/CodeGen/AMDGPU/usubo.ll

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_usubo_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %carryout, <2 x i32> addrspace(1)* %aptr, <2 x i32> addrspace(1)* %bptr) nounwind {
%val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0 %val = extractvalue { <2 x i32>, <2 x i1> } %sadd, 0
%carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1 %carry = extractvalue { <2 x i32>, <2 x i1> } %sadd, 1
store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4 store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4
%carry.ext = zext <2 x i1> %carry to <2 x i32> %carry.ext = zext <2 x i1> %carry to <2 x i32>
store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout store <2 x i32> %carry.ext, <2 x i32> addrspace(1)* %carryout
ret void ret void
} }
; FUNC-LABEL: {{^}}s_usubo_clamp_bit:
; GCN: v_sub_{{i|u|co_u}}32_e32
; GCN: s_endpgm
define amdgpu_kernel void @s_usubo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
entry:
%usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue { i32, i1 } %usub, 0
%carry = extractvalue { i32, i1 } %usub, 1
%c2 = icmp eq i1 %carry, false
%cc = icmp eq i32 %a, %b
br i1 %cc, label %exit, label %if
if:
br label %exit
exit:
%cout = phi i1 [false, %entry], [%c2, %if]
store i32 %val, i32 addrspace(1)* %out, align 4
store i1 %cout, i1 addrspace(1)* %carryout
ret void
}
; FUNC-LABEL: {{^}}v_usubo_clamp_bit:
; GCN: v_sub_{{i|u|co_u}}32_e64
; GCN: s_endpgm
define amdgpu_kernel void @v_usubo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
%a = load i32, i32 addrspace(1)* %a.gep, align 4
%b = load i32, i32 addrspace(1)* %b.gep, align 4
%usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue { i32, i1 } %usub, 0
%carry = extractvalue { i32, i1 } %usub, 1
%c2 = icmp eq i1 %carry, false
%cc = icmp eq i32 %a, %b
br i1 %cc, label %exit, label %if
if:
br label %exit
exit:
%cout = phi i1 [false, %entry], [%c2, %if]
store i32 %val, i32 addrspace(1)* %out, align 4
store i1 %cout, i1 addrspace(1)* %carryout
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare { i16, i1 } @llvm.usub.with.overflow.i16(i16, i16) #1 declare { i16, i1 } @llvm.usub.with.overflow.i16(i16, i16) #1
declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #1 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #1
declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) #1 declare { i64, i1 } @llvm.usub.with.overflow.i64(i64, i64) #1
declare { <2 x i32>, <2 x i1> } @llvm.usub.with.overflow.v2i32(<2 x i32>, <2 x i32>) nounwind readnone declare { <2 x i32>, <2 x i1> } @llvm.usub.with.overflow.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }