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Differential D59933

[MIPS GlobalISel] Select float constants
ClosedPublic

Authored by Petar.Avramovic on Mar 28 2019, 7:34 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG1af05df3de60: [MIPS GlobalISel] Select float constants
rL357183: [MIPS GlobalISel] Select float constants
Summary

Select 32 and 64 bit float constants for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Mar 28 2019, 7:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 28 2019, 7:34 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 3 others. · View Herald Transcript
atanasyan accepted this revision.Mar 28 2019, 9:31 AM

LGTM

This revision is now accepted and ready to land.Mar 28 2019, 9:31 AM
Closed by commit rL357183: [MIPS GlobalISel] Select float constants (authored by Petar.Avramovic). · Explain WhyMar 28 2019, 9:56 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
35 lines
3 lines
37 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
64 lines
legalizer/
49 lines
llvm-ir/
41 lines
regbankselect/
50 lines

Diff 192667

llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 314 Lines • ▼ Show 20 Lines case G_CONSTANT: {
MachineIRBuilder B(I); MachineIRBuilder B(I);
if (!materialize32BitImm(I.getOperand(0).getReg(), if (!materialize32BitImm(I.getOperand(0).getReg(),
I.getOperand(1).getCImm()->getValue(), B)) I.getOperand(1).getCImm()->getValue(), B))
return false; return false;
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
case G_FCONSTANT: {
const APFloat &FPimm = I.getOperand(1).getFPImm()->getValueAPF();
APInt APImm = FPimm.bitcastToAPInt();
unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
if (Size == 32) {
unsigned GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
MachineIRBuilder B(I);
if (!materialize32BitImm(GPRReg, APImm, B))
return false;
MachineInstrBuilder MTC1 =
B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});
if (!MTC1.constrainAllUses(TII, TRI, RBI))
return false;
}
if (Size == 64) {
unsigned GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
unsigned GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
MachineIRBuilder B(I);
if (!materialize32BitImm(GPRRegHigh, APImm.getHiBits(32).trunc(32), B))
return false;
if (!materialize32BitImm(GPRRegLow, APImm.getLoBits(32).trunc(32), B))
return false;
MachineInstrBuilder PairF64 = B.buildInstr(
STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64,
{I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh});
if (!PairF64.constrainAllUses(TII, TRI, RBI))
return false;
}
I.eraseFromParent();
return true;
}
case G_GLOBAL_VALUE: { case G_GLOBAL_VALUE: {
if (MF.getTarget().isPositionIndependent()) if (MF.getTarget().isPositionIndependent())
return false; return false;
const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
MachineInstr *LUi, *ADDiu; MachineInstr *LUi, *ADDiu;
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder(G_ICMP) getActionDefinitionsBuilder(G_ICMP)
.legalFor({{s32, s32}}) .legalFor({{s32, s32}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_CONSTANT) getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({s32}) .legalFor({s32})
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({s32, s64});
getActionDefinitionsBuilder(G_GEP) getActionDefinitionsBuilder(G_GEP)
.legalFor({{p0, s32}}); .legalFor({{p0, s32}});
getActionDefinitionsBuilder(G_FRAME_INDEX) getActionDefinitionsBuilder(G_FRAME_INDEX)
.legalFor({p0}); .legalFor({p0});
getActionDefinitionsBuilder(G_GLOBAL_VALUE) getActionDefinitionsBuilder(G_GLOBAL_VALUE)
.legalFor({p0}); .legalFor({p0});
Show All 16 Lines

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show All 18 Lines
#define DEBUG_TYPE "registerbankinfo" #define DEBUG_TYPE "registerbankinfo"
#include "MipsGenRegisterBank.inc" #include "MipsGenRegisterBank.inc"
namespace llvm { namespace llvm {
namespace Mips { namespace Mips {
enum PartialMappingIdx { enum PartialMappingIdx {
PMI_GPR, PMI_GPR,
PMI_SPR,
PMI_DPR,
PMI_Min = PMI_GPR, PMI_Min = PMI_GPR,
}; };
RegisterBankInfo::PartialMapping PartMappings[]{ RegisterBankInfo::PartialMapping PartMappings[]{
{0, 32, GPRBRegBank} {0, 32, GPRBRegBank},
{0, 32, FPRBRegBank},
{0, 64, FPRBRegBank}
}; };
enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 }; enum ValueMappingIdx {
InvalidIdx = 0,
GPRIdx = 1,
SPRIdx = 4,
DPRIdx = 7
};
RegisterBankInfo::ValueMapping ValueMappings[] = { RegisterBankInfo::ValueMapping ValueMappings[] = {
// invalid // invalid
{nullptr, 0}, {nullptr, 0},
// 3 operands in GPRs // up to 3 operands in GPRs
{&PartMappings[PMI_GPR - PMI_Min], 1},
{&PartMappings[PMI_GPR - PMI_Min], 1}, {&PartMappings[PMI_GPR - PMI_Min], 1},
{&PartMappings[PMI_GPR - PMI_Min], 1}, {&PartMappings[PMI_GPR - PMI_Min], 1},
{&PartMappings[PMI_GPR - PMI_Min], 1}}; // up to 3 ops operands FPRs - single precission
{&PartMappings[PMI_SPR - PMI_Min], 1},
{&PartMappings[PMI_SPR - PMI_Min], 1},
{&PartMappings[PMI_SPR - PMI_Min], 1},
// up to 3 ops operands FPRs - double precission
{&PartMappings[PMI_DPR - PMI_Min], 1},
{&PartMappings[PMI_DPR - PMI_Min], 1},
{&PartMappings[PMI_DPR - PMI_Min], 1}
};
} // end namespace Mips } // end namespace Mips
} // end namespace llvm } // end namespace llvm
using namespace llvm; using namespace llvm;
MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
: MipsGenRegisterBankInfo() {} : MipsGenRegisterBankInfo() {}
Show All 20 Lines default:
llvm_unreachable("Register class not supported"); llvm_unreachable("Register class not supported");
} }
} }
const RegisterBankInfo::InstructionMapping & const RegisterBankInfo::InstructionMapping &
MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
unsigned Opc = MI.getOpcode(); unsigned Opc = MI.getOpcode();
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI); const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
if (Mapping.isValid()) if (Mapping.isValid())
return Mapping; return Mapping;
using namespace TargetOpcode; using namespace TargetOpcode;
unsigned NumOperands = MI.getNumOperands(); unsigned NumOperands = MI.getNumOperands();
Show All 17 LinesMipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_ASHR: case G_ASHR:
case G_LSHR: case G_LSHR:
case G_SDIV: case G_SDIV:
case G_UDIV: case G_UDIV:
case G_SREM: case G_SREM:
case G_UREM: case G_UREM:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
break; break;
case G_FCONSTANT: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
unsigned Size = Ty.getSizeInBits();
const RegisterBankInfo::ValueMapping *FPRValueMapping =
Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
: &Mips::ValueMappings[Mips::DPRIdx];
OperandsMapping = getOperandsMapping({FPRValueMapping, nullptr});
break;
}
case G_CONSTANT: case G_CONSTANT:
case G_FRAME_INDEX: case G_FRAME_INDEX:
case G_GLOBAL_VALUE: case G_GLOBAL_VALUE:
case G_BRCOND: case G_BRCOND:
OperandsMapping = OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr}); getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
break; break;
case G_ICMP: case G_ICMP:
Show All 19 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/float_constants.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @e_single_precision() {entry: ret void}
define void @e_double_precision() {entry: ret void}
...
---
name: e_single_precision
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_single_precision
; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
; FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
; FP32: $f0 = COPY [[MTC1_]]
; FP32: RetRA implicit $f0
; FP64-LABEL: name: e_single_precision
; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
; FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
; FP64: $f0 = COPY [[MTC1_]]
; FP64: RetRA implicit $f0
%0:fprb(s32) = G_FCONSTANT float 0x4005BF0A80000000
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: e_double_precision
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_double_precision
; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906
; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604
; FP32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 22377
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[ORi1]], [[ORi]]
; FP32: $d0 = COPY [[BuildPairF64_]]
; FP32: RetRA implicit $d0
; FP64-LABEL: name: e_double_precision
; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906
; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604
; FP64: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 22377
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64 = BuildPairF64_64 [[ORi1]], [[ORi]]
; FP64: $d0 = COPY [[BuildPairF64_64_]]
; FP64: RetRA implicit $d0
%0:fprb(s64) = G_FCONSTANT double 0x4005BF0A8B145769
$d0 = COPY %0(s64)
RetRA implicit $d0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @e_single_precision() {entry: ret void}
define void @e_double_precision() {entry: ret void}
...
---
name: e_single_precision
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_single_precision
; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
; FP32: $f0 = COPY [[C]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: e_single_precision
; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
; FP64: $f0 = COPY [[C]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: e_double_precision
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_double_precision
; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
; FP32: $d0 = COPY [[C]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: e_double_precision
; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
; FP64: $d0 = COPY [[C]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
$d0 = COPY %0(s64)
RetRA implicit $d0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
define float @e_single_precision() {
; MIPS32-LABEL: e_single_precision:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 16429
; MIPS32-NEXT: ori $1, $1, 63572
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret float 0x4005BF0A80000000
}
define double @e_double_precision() {
; FP32-LABEL: e_double_precision:
; FP32: # %bb.0: # %entry
; FP32-NEXT: lui $1, 16389
; FP32-NEXT: ori $1, $1, 48906
; FP32-NEXT: lui $2, 35604
; FP32-NEXT: ori $2, $2, 22377
; FP32-NEXT: mtc1 $2, $f0
; FP32-NEXT: mtc1 $1, $f1
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: e_double_precision:
; FP64: # %bb.0: # %entry
; FP64-NEXT: lui $1, 16389
; FP64-NEXT: ori $1, $1, 48906
; FP64-NEXT: lui $2, 35604
; FP64-NEXT: ori $2, $2, 22377
; FP64-NEXT: mtc1 $2, $f0
; FP64-NEXT: mthc1 $1, $f0
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
ret double 0x4005BF0A8B145769
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @e_single_precision() {entry: ret void}
define void @e_double_precision() {entry: ret void}
...
---
name: e_single_precision
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_single_precision
; FP32: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0x4005BF0A80000000
; FP32: $f0 = COPY [[C]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: e_single_precision
; FP64: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0x4005BF0A80000000
; FP64: $f0 = COPY [[C]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = G_FCONSTANT float 0x4005BF0A80000000
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: e_double_precision
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; FP32-LABEL: name: e_double_precision
; FP32: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0x4005BF0A8B145769
; FP32: $d0 = COPY [[C]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: e_double_precision
; FP64: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0x4005BF0A8B145769
; FP64: $d0 = COPY [[C]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = G_FCONSTANT double 0x4005BF0A8B145769
$d0 = COPY %0(s64)
RetRA implicit $d0
...