[AArch64] Prefer "mov" over "orr" to materialize constants.

[efriedma]

Summary

This is generally more readable due to the way the assembler aliases work.

(This causes a lot of test changes, but it's not really as scary as it looks at first glance. It's just mechanically changing a bunch of checks for orr to check for mov instead.)

[t.p.northover]

Looks fine to me.

lib/Target/AArch64/AArch64ExpandImm.cpp

void expandMOVImm(uint64_t Imm, unsigned BitSize,
   for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
     const unsigned Chunk = (Imm >> Shift) & Mask;
     if (Chunk == Mask)
       OneChunks++;
     else if (Chunk == 0)
       ZeroChunks++;
   }
 
-  // FIXME: Prefer MOVZ/MOVN over ORR because of the rules for the "mov"
-  // alias.
+  // Prefer MOVZ/MOVN over ORR because of the rules for the "mov" alias.
+  if ((BitSize / 16) - OneChunks <= 1 || (BitSize / 16) - ZeroChunks <= 1) {
+    expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
+    return;
+  }
 
   // Try a single ORR.
   uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
   uint64_t Encoding;
   if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
     unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
     Insn.push_back({ Opc, 0, Encoding });
     return;

test/CodeGen/AArch64/arm64-aapcs.ll

 
 declare void @variadic(i32 %a, ...)
 
   ; Under AAPCS variadic functions have the same calling convention as
   ; others. The extra arguments should go in registers rather than on the stack.
 define void @test_variadic() {
   call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)
 ; CHECK: fmov d0, #2.0
-; CHECK: orr w1, wzr, #0x1
+; CHECK: mov w1, #1
 ; CHECK: bl variadic
   ret void
 }
 
 ; We weren't marking x7 as used after deciding that the i128 didn't fit into
 ; registers and putting the first half on the stack, so the *second* half went
 ; into x7. Yuck!
 define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {

test/CodeGen/AArch64/arm64-abi.ll

 declare double @args_vec_2i(double, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>,
                <2 x i32>, <2 x i32>, <2 x i32>, float, <2 x i32>, i8 signext)
 
 define double @test4(double* nocapture %in) nounwind {
 entry:
 ; CHECK-LABEL: test4
 ; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
 ; CHECK: str [[REG_2:w[0-9]+]], [sp]
-; CHECK: orr w0, wzr, #0x3
+; CHECK: mov w0, #3
   %0 = load double, double* %in, align 8
   %call = tail call double @args_f64(double 3.000000e+00, double %0, double %0,
           double %0, double %0, double %0, double %0, double %0,
           float 3.000000e+00, double %0, i8 signext 3)
   ret double %call
 }
 declare double @args_f64(double, double, double, double, double, double, double,
                double, float, double, i8 signext)

test/CodeGen/AArch64/arm64-abi_align.ll

 ; Space for s1 is allocated at sp+32
 ; Space for s2 is allocated at sp
 
 ; FAST-LABEL: caller42
 ; FAST: sub sp, sp, #96
 ; Space for s1 is allocated at fp-24 = sp+56
 ; FAST: sub x[[A:[0-9]+]], x29, #24
 ; Call memcpy with size = 24 (0x18)
-; FAST: orr {{x[0-9]+}}, xzr, #0x18
+; FAST: mov {{x[0-9]+}}, #24
 ; Space for s2 is allocated at sp+32
 ; FAST: add x[[A:[0-9]+]], sp, #32
 ; FAST: bl _memcpy
   %tmp = alloca %struct.s42, align 4
   %tmp1 = alloca %struct.s42, align 4
   %0 = bitcast %struct.s42* %tmp to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 bitcast (%struct.s42* @g42 to i8*), i64 24, i1 false), !tbaa.struct !4
   %1 = bitcast %struct.s42* %tmp1 to i8*

 ; CHECK: str x[[A]], [sp, #8]
 ; CHECK: mov w[[C:[0-9]+]], #9
 ; CHECK: str w[[C]], [sp]
 
 ; FAST-LABEL: caller42_stack
 ; Space for s1 is allocated at fp-24
 ; FAST: sub x[[A:[0-9]+]], x29, #24
 ; Call memcpy with size = 24 (0x18)
-; FAST: orr {{x[0-9]+}}, xzr, #0x18
+; FAST: mov {{x[0-9]+}}, #24
 ; FAST: bl _memcpy
 ; Space for s2 is allocated at fp-48
 ; FAST: sub x[[B:[0-9]+]], x29, #48
 ; Call memcpy again
 ; FAST: bl _memcpy
 ; Address of s1 is passed on stack at sp+8
 ; FAST: str {{w[0-9]+}}, [sp]
 ; FAST: str {{x[0-9]+}}, [sp, #8]

 ; CHECK-LABEL: i64_split
 ; "i64 %0" should be in register x7.
 ; "i32 8" should be on stack at [sp].
 ; CHECK: ldr x7, [{{x[0-9]+}}]
 ; CHECK: str {{w[0-9]+}}, [sp]
 ; FAST-LABEL: i64_split
 ; FAST: ldr x7, [{{x[0-9]+}}]
 ; FAST: mov x[[R0:[0-9]+]], sp
-; FAST: orr w[[R1:[0-9]+]], wzr, #0x8
+; FAST: mov w[[R1:[0-9]+]], #8
 ; FAST: str w[[R1]], {{\[}}x[[R0]]{{\]}}
   %0 = load i64, i64* bitcast (%struct.s41* @g41 to i64*), align 16
   %call = tail call i32 @callee_i64(i32 1, i32 2, i32 3, i32 4, i32 5,
                                     i32 6, i32 7, i64 %0, i32 8) #5
   ret i32 %call
 }
 
 attributes #0 = { noinline nounwind readnone "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" }

test/CodeGen/AArch64/arm64-addrmode.ll

 define void @t3(i64* %object) {
   %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4095
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + unsigned offset (> imm12 * size of type in bytes)
 ; CHECK: @t4
-; CHECK: orr w[[NUM:[0-9]+]], wzr, #0x8000
+; CHECK: mov w[[NUM:[0-9]+]], #32768
 ; CHECK: ldr xzr, [x0, x[[NUM]]]
 ; CHECK: ret
 define void @t4(i64* %object) {
   %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4096
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + reg
 ; CHECK: @t5
 ; CHECK: ldr xzr, [x{{[0-9]+}}, x{{[0-9]+}}, lsl #3]
 ; CHECK: ret
 define void @t5(i64 %a) {
   %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 %a
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + reg + imm
 ; CHECK: @t6
 ; CHECK: add [[ADDREG:x[0-9]+]], x1, x0, lsl #3
-; CHECK-NEXT: orr w[[NUM:[0-9]+]], wzr, #0x8000
+; CHECK-NEXT: mov w[[NUM:[0-9]+]], #32768
 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
 ; CHECK: ret
 define void @t6(i64 %a, i64* %object) {
   %tmp1 = getelementptr inbounds i64, i64* %object, i64 %a
   %incdec.ptr = getelementptr inbounds i64, i64* %tmp1, i64 4096
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; Test base + wide immediate
 define void @t7(i64 %a) {
 ; CHECK-LABEL: t7:
-; CHECK: orr w[[NUM:[0-9]+]], wzr, #0xffff
+; CHECK: mov w[[NUM:[0-9]+]], #65535
 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
   %1 = add i64 %a, 65535   ;0xffff
   %2 = inttoptr i64 %1 to i64*
   %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
 define void @t8(i64 %a) {

test/CodeGen/AArch64/arm64-build-vector.ll

; CHECK-NEXT:    ret
   store <2 x half> <half 0xH33EE, half 0xH33EE>, <2 x half>* %1, align 2
   ret void
 }
 
 ; Check that a single element vector is constructed with a mov
 define <1 x i64> @single_element_vector_i64(<1 x i64> %arg) {
 ; CHECK-LABEL: single_element_vector_i64:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    fmov d1, x8
 ; CHECK-NEXT:    add d0, d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %add = add <1 x i64> %arg, <i64 1>
   ret <1 x i64> %add
 }
 

test/CodeGen/AArch64/arm64-ccmp.ll

 ; safe to speculate.
 ; CHECK-LABEL: speculate_division:
 ; CHECK: cmp w0, #1
 ; CHECK: sdiv [[DIVRES:w[0-9]+]], w1, w0
 ; CHECK: ccmp [[DIVRES]], #16, #0, ge
 ; CHECK: b.le [[BLOCK:LBB[0-9_]+]]
 ; CHECK: [[BLOCK]]:
 ; CHECK: bl _foo
-; CHECK: orr w0, wzr, #0x7
+; CHECK: mov w0, #7
 define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %land.lhs.true, label %if.end
 
 land.lhs.true:
   %div = sdiv i32 %b, %a
   %cmp1 = icmp slt i32 %div, 17
; CHECK-NEXT: ret
   ret i64 %sel
 }
 
 ; CHECK-LABEL: gccbug
 define i64 @gccbug(i64 %x0, i64 %x1) {
 ; CHECK: cmp x0, #2
 ; CHECK-NEXT: ccmp x0, #4, #4, ne
 ; CHECK-NEXT: ccmp x1, #0, #0, eq
-; CHECK-NEXT: orr w[[REGNUM:[0-9]+]], wzr, #0x1
+; CHECK-NEXT: mov w[[REGNUM:[0-9]+]], #1
 ; CHECK-NEXT: cinc x0, x[[REGNUM]], eq
 ; CHECK-NEXT: ret
   %cmp0 = icmp eq i64 %x1, 0
   %cmp1 = icmp eq i64 %x0, 2
   %cmp2 = icmp eq i64 %x0, 4
 
   %or = or i1 %cmp2, %cmp1
   %and = and i1 %or, %cmp0

test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll

 ; RUN: llc < %s | FileCheck %s
 
-; CHECK:       orr     w0, wzr, #0x1
+; CHECK:       mov     w0, #1
 ; CHECK-NEXT:  bl      foo
-; CHECK-NEXT:  orr     w0, wzr, #0x1
+; CHECK-NEXT:  mov     w0, #1
 ; CHECK-NEXT:  bl      foo
 
 target triple = "aarch64--linux-android"
 declare i32 @foo(i32)
 
 ; Function Attrs: nounwind uwtable
 define i32 @main() {
 entry:
   %call = tail call i32 @foo(i32 1)
   %call1 = tail call i32 @foo(i32 1)
   ret i32 0
 }

test/CodeGen/AArch64/arm64-csel.ll

; CHECK: csinv w0, w1, w2, ne
   %cond = select i1 %tobool, i32 %neg, i32 %a
   ret i32 %cond
 }
 
 define i32 @foo9(i32 %v) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo9:
 ; CHECK: cmp w0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
+; CHECK: mov w[[REG:[0-9]+]], #4
 ; CHECK: cinv w0, w[[REG]], eq
   %tobool = icmp ne i32 %v, 0
   %cond = select i1 %tobool, i32 4, i32 -5
   ret i32 %cond
 }
 
 define i64 @foo10(i64 %v) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo10:
 ; CHECK: cmp x0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
+; CHECK: mov w[[REG:[0-9]+]], #4
 ; CHECK: cinv x0, x[[REG]], eq
   %tobool = icmp ne i64 %v, 0
   %cond = select i1 %tobool, i64 4, i64 -5
   ret i64 %cond
 }
 
 define i32 @foo11(i32 %v) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo11:
 ; CHECK: cmp w0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
+; CHECK: mov w[[REG:[0-9]+]], #4
 ; CHECK: cneg w0, w[[REG]], eq
   %tobool = icmp ne i32 %v, 0
   %cond = select i1 %tobool, i32 4, i32 -4
   ret i32 %cond
 }
 
 define i64 @foo12(i64 %v) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo12:
 ; CHECK: cmp x0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
+; CHECK: mov w[[REG:[0-9]+]], #4
 ; CHECK: cneg x0, x[[REG]], eq
   %tobool = icmp ne i64 %v, 0
   %cond = select i1 %tobool, i64 4, i64 -4
   ret i64 %cond
 }
 
 define i32 @foo13(i32 %v, i32 %a, i32 %b) nounwind readnone optsize ssp {
 entry:
; CHECK: csneg x0, x1, x2, ne
   %cond = select i1 %tobool, i64 %sub, i64 %a
   ret i64 %cond
 }
 
 define i32 @foo15(i32 %a, i32 %b) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo15:
 ; CHECK: cmp w0, w1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[REG:[0-9]+]], #1
 ; CHECK: cinc w0, w[[REG]], gt
   %cmp = icmp sgt i32 %a, %b
   %. = select i1 %cmp, i32 2, i32 1
   ret i32 %.
 }
 
 define i32 @foo16(i32 %a, i32 %b) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo16:
 ; CHECK: cmp w0, w1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[REG:[0-9]+]], #1
 ; CHECK: cinc w0, w[[REG]], le
   %cmp = icmp sgt i32 %a, %b
   %. = select i1 %cmp, i32 1, i32 2
   ret i32 %.
 }
 
 define i64 @foo17(i64 %a, i64 %b) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo17:
 ; CHECK: cmp x0, x1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[REG:[0-9]+]], #1
 ; CHECK: cinc x0, x[[REG]], gt
   %cmp = icmp sgt i64 %a, %b
   %. = select i1 %cmp, i64 2, i64 1
   ret i64 %.
 }
 
 define i64 @foo18(i64 %a, i64 %b) nounwind readnone optsize ssp {
 entry:
 ; CHECK-LABEL: foo18:
 ; CHECK: cmp x0, x1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[REG:[0-9]+]], #1
 ; CHECK: cinc x0, x[[REG]], le
   %cmp = icmp sgt i64 %a, %b
   %. = select i1 %cmp, i64 1, i64 2
   ret i64 %.
 }
 
 define i64 @foo19(i64 %a, i64 %b, i64 %c) {
 entry:
 ; CHECK-LABEL: foo19:
 ; CHECK: cinc x0, x2
 ; CHECK-NOT: add
   %cmp = icmp ult i64 %a, %b
   %inc = zext i1 %cmp to i64
   %inc.c = add i64 %inc, %c
   ret i64 %inc.c
 }
 
 define i32 @foo20(i32 %x) {
 ; CHECK-LABEL: foo20:
 ; CHECK: cmp w0, #5
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: mov w[[REG:[0-9]+]], #6
 ; CHECK: csinc w0, w[[REG]], wzr, eq
   %cmp = icmp eq i32 %x, 5
   %res = select i1 %cmp, i32 6, i32 1
   ret i32 %res
 }
 
 define i64 @foo21(i64 %x) {
 ; CHECK-LABEL: foo21:
 ; CHECK: cmp x0, #5
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: mov w[[REG:[0-9]+]], #6
 ; CHECK: csinc x0, x[[REG]], xzr, eq
   %cmp = icmp eq i64 %x, 5
   %res = select i1 %cmp, i64 6, i64 1
   ret i64 %res
 }
 
 define i32 @foo22(i32 %x) {
 ; CHECK-LABEL: foo22:
 ; CHECK: cmp w0, #5
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: mov w[[REG:[0-9]+]], #6
 ; CHECK: csinc w0, w[[REG]], wzr, ne
   %cmp = icmp eq i32 %x, 5
   %res = select i1 %cmp, i32 1, i32 6
   ret i32 %res
 }
 
 define i64 @foo23(i64 %x) {
 ; CHECK-LABEL: foo23:
 ; CHECK: cmp x0, #5
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK: mov w[[REG:[0-9]+]], #6
 ; CHECK: csinc x0, x[[REG]], xzr, ne
   %cmp = icmp eq i64 %x, 5
   %res = select i1 %cmp, i64 1, i64 6
   ret i64 %res
 }

test/CodeGen/AArch64/arm64-fast-isel-call.ll

 declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext)
 
 ; Test materialization of integers.  Target-independent selector handles this.
 define i32 @t2() {
 entry:
 ; CHECK-LABEL: t2
 ; CHECK:       mov [[REG1:x[0-9]+]], xzr
 ; CHECK:       mov x0, [[REG1]]
-; CHECK:       orr w1, wzr, #0xfffffff8
-; CHECK:       orr [[REG2:w[0-9]+]], wzr, #0x3ff
+; CHECK:       mov w1, #-8
+; CHECK:       mov [[REG2:w[0-9]+]], #1023
 ; CHECK:       uxth w2, [[REG2]]
-; CHECK:       orr [[REG3:w[0-9]+]], wzr, #0x2
+; CHECK:       mov [[REG3:w[0-9]+]], #2
 ; CHECK:       sxtb w3, [[REG3]]
 ; CHECK:       mov [[REG4:w[0-9]+]], wzr
 ; CHECK:       and w4, [[REG4]], #0x1
-; CHECK:       orr [[REG5:w[0-9]+]], wzr, #0x1
+; CHECK:       mov [[REG5:w[0-9]+]], #1
 ; CHECK:       and w5, [[REG5]], #0x1
 ; CHECK:       bl _func2
   %call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)
   ret i32 0
 }
 
 declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 signext, i1 zeroext, i1 zeroext)
 

test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll

 ; CHECK:       fcmp s0, s1
 ; CHECK-NEXT:  cset {{w[0-9]+}}, ne
   %1 = fcmp une float %a, %b
   ret i1 %1
 }
 
 define zeroext i1 @fcmp_true(float %a) {
 ; CHECK-LABEL: fcmp_true
-; CHECK:       orr {{w[0-9]+}}, wzr, #0x1
+; CHECK:       mov {{w[0-9]+}}, #1
   %1 = fcmp ueq float %a, %a
   ret i1 %1
 }

test/CodeGen/AArch64/arm64-fast-isel.ll

; CHECK: brk #0x1
   ret void
 }
 
 declare void @llvm.trap() nounwind
 
 define void @ands(i32* %addr) {
 ; CHECK-LABEL: ands:
 ; CHECK: tst [[COND:w[0-9]+]], #0x1
-; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x2
-; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x1
+; CHECK-NEXT: mov w{{[0-9]+}}, #2
+; CHECK-NEXT: mov w{{[0-9]+}}, #1
 ; CHECK-NEXT: csel [[COND]],
 entry:
   %cond91 = select i1 undef, i32 1, i32 2
   store i32 %cond91, i32* %addr, align 4
   ret void
 }
 
 define i64 @mul_umul(i64 %arg) {

test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

; CHECK: st1.b { v0 }[3], [x0], #1
   store i8 %elt, i8* %addr
 
   %newaddr = getelementptr i8, i8* %addr, i32 1
   ret i8* %newaddr
 }
 
 define i8* @test_v16i8_post_reg_st1_lane(<16 x i8> %in, i8* %addr) {
 ; CHECK-LABEL: test_v16i8_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2
+; CHECK: mov w[[OFFSET:[0-9]+]], #2
 ; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]]
   %elt = extractelement <16 x i8> %in, i32 3
   store i8 %elt, i8* %addr
 
   %newaddr = getelementptr i8, i8* %addr, i32 2
   ret i8* %newaddr
 }
 
 
 define i16* @test_v8i16_post_imm_st1_lane(<8 x i16> %in, i16* %addr) {
 ; CHECK-LABEL: test_v8i16_post_imm_st1_lane:
 ; CHECK: st1.h { v0 }[3], [x0], #2
   %elt = extractelement <8 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
   %newaddr = getelementptr i16, i16* %addr, i32 1
   ret i16* %newaddr
 }
 
 define i16* @test_v8i16_post_reg_st1_lane(<8 x i16> %in, i16* %addr) {
 ; CHECK-LABEL: test_v8i16_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4
+; CHECK: mov w[[OFFSET:[0-9]+]], #4
 ; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]]
   %elt = extractelement <8 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
   %newaddr = getelementptr i16, i16* %addr, i32 2
   ret i16* %newaddr
 }
 
 define i32* @test_v4i32_post_imm_st1_lane(<4 x i32> %in, i32* %addr) {
 ; CHECK-LABEL: test_v4i32_post_imm_st1_lane:
 ; CHECK: st1.s { v0 }[3], [x0], #4
   %elt = extractelement <4 x i32> %in, i32 3
   store i32 %elt, i32* %addr
 
   %newaddr = getelementptr i32, i32* %addr, i32 1
   ret i32* %newaddr
 }
 
 define i32* @test_v4i32_post_reg_st1_lane(<4 x i32> %in, i32* %addr) {
 ; CHECK-LABEL: test_v4i32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
+; CHECK: mov w[[OFFSET:[0-9]+]], #8
 ; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]]
   %elt = extractelement <4 x i32> %in, i32 3
   store i32 %elt, i32* %addr
 
   %newaddr = getelementptr i32, i32* %addr, i32 2
   ret i32* %newaddr
 }
 
 define float* @test_v4f32_post_imm_st1_lane(<4 x float> %in, float* %addr) {
 ; CHECK-LABEL: test_v4f32_post_imm_st1_lane:
 ; CHECK: st1.s { v0 }[3], [x0], #4
   %elt = extractelement <4 x float> %in, i32 3
   store float %elt, float* %addr
 
   %newaddr = getelementptr float, float* %addr, i32 1
   ret float* %newaddr
 }
 
 define float* @test_v4f32_post_reg_st1_lane(<4 x float> %in, float* %addr) {
 ; CHECK-LABEL: test_v4f32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
+; CHECK: mov w[[OFFSET:[0-9]+]], #8
 ; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]]
   %elt = extractelement <4 x float> %in, i32 3
   store float %elt, float* %addr
 
   %newaddr = getelementptr float, float* %addr, i32 2
   ret float* %newaddr
 }
 
 define i64* @test_v2i64_post_imm_st1_lane(<2 x i64> %in, i64* %addr) {
 ; CHECK-LABEL: test_v2i64_post_imm_st1_lane:
 ; CHECK: st1.d { v0 }[1], [x0], #8
   %elt = extractelement <2 x i64> %in, i64 1
   store i64 %elt, i64* %addr
 
   %newaddr = getelementptr i64, i64* %addr, i64 1
   ret i64* %newaddr
 }
 
 define i64* @test_v2i64_post_reg_st1_lane(<2 x i64> %in, i64* %addr) {
 ; CHECK-LABEL: test_v2i64_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10
+; CHECK: mov w[[OFFSET:[0-9]+]], #16
 ; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]]
   %elt = extractelement <2 x i64> %in, i64 1
   store i64 %elt, i64* %addr
 
   %newaddr = getelementptr i64, i64* %addr, i64 2
   ret i64* %newaddr
 }
 
 define double* @test_v2f64_post_imm_st1_lane(<2 x double> %in, double* %addr) {
 ; CHECK-LABEL: test_v2f64_post_imm_st1_lane:
 ; CHECK: st1.d { v0 }[1], [x0], #8
   %elt = extractelement <2 x double> %in, i32 1
   store double %elt, double* %addr
 
   %newaddr = getelementptr double, double* %addr, i32 1
   ret double* %newaddr
 }
 
 define double* @test_v2f64_post_reg_st1_lane(<2 x double> %in, double* %addr) {
 ; CHECK-LABEL: test_v2f64_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10
+; CHECK: mov w[[OFFSET:[0-9]+]], #16
 ; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]]
   %elt = extractelement <2 x double> %in, i32 1
   store double %elt, double* %addr
 
   %newaddr = getelementptr double, double* %addr, i32 2
   ret double* %newaddr
 }
 
 define i8* @test_v8i8_post_imm_st1_lane(<8 x i8> %in, i8* %addr) {
 ; CHECK-LABEL: test_v8i8_post_imm_st1_lane:
 ; CHECK: st1.b { v0 }[3], [x0], #1
   %elt = extractelement <8 x i8> %in, i32 3
   store i8 %elt, i8* %addr
 
   %newaddr = getelementptr i8, i8* %addr, i32 1
   ret i8* %newaddr
 }
 
 define i8* @test_v8i8_post_reg_st1_lane(<8 x i8> %in, i8* %addr) {
 ; CHECK-LABEL: test_v8i8_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2
+; CHECK: mov w[[OFFSET:[0-9]+]], #2
 ; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]]
   %elt = extractelement <8 x i8> %in, i32 3
   store i8 %elt, i8* %addr
 
   %newaddr = getelementptr i8, i8* %addr, i32 2
   ret i8* %newaddr
 }
 
 define i16* @test_v4i16_post_imm_st1_lane(<4 x i16> %in, i16* %addr) {
 ; CHECK-LABEL: test_v4i16_post_imm_st1_lane:
 ; CHECK: st1.h { v0 }[3], [x0], #2
   %elt = extractelement <4 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
   %newaddr = getelementptr i16, i16* %addr, i32 1
   ret i16* %newaddr
 }
 
 define i16* @test_v4i16_post_reg_st1_lane(<4 x i16> %in, i16* %addr) {
 ; CHECK-LABEL: test_v4i16_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4
+; CHECK: mov w[[OFFSET:[0-9]+]], #4
 ; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]]
   %elt = extractelement <4 x i16> %in, i32 3
   store i16 %elt, i16* %addr
 
   %newaddr = getelementptr i16, i16* %addr, i32 2
   ret i16* %newaddr
 }
 
 define i32* @test_v2i32_post_imm_st1_lane(<2 x i32> %in, i32* %addr) {
 ; CHECK-LABEL: test_v2i32_post_imm_st1_lane:
 ; CHECK: st1.s { v0 }[1], [x0], #4
   %elt = extractelement <2 x i32> %in, i32 1
   store i32 %elt, i32* %addr
 
   %newaddr = getelementptr i32, i32* %addr, i32 1
   ret i32* %newaddr
 }
 
 define i32* @test_v2i32_post_reg_st1_lane(<2 x i32> %in, i32* %addr) {
 ; CHECK-LABEL: test_v2i32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
+; CHECK: mov w[[OFFSET:[0-9]+]], #8
 ; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]]
   %elt = extractelement <2 x i32> %in, i32 1
   store i32 %elt, i32* %addr
 
   %newaddr = getelementptr i32, i32* %addr, i32 2
   ret i32* %newaddr
 }
 
 define float* @test_v2f32_post_imm_st1_lane(<2 x float> %in, float* %addr) {
 ; CHECK-LABEL: test_v2f32_post_imm_st1_lane:
 ; CHECK: st1.s { v0 }[1], [x0], #4
   %elt = extractelement <2 x float> %in, i32 1
   store float %elt, float* %addr
 
   %newaddr = getelementptr float, float* %addr, i32 1
   ret float* %newaddr
 }
 
 define float* @test_v2f32_post_reg_st1_lane(<2 x float> %in, float* %addr) {
 ; CHECK-LABEL: test_v2f32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
+; CHECK: mov w[[OFFSET:[0-9]+]], #8
 ; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]]
   %elt = extractelement <2 x float> %in, i32 1
   store float %elt, float* %addr
 
   %newaddr = getelementptr float, float* %addr, i32 2
   ret float* %newaddr
 }
 

test/CodeGen/AArch64/arm64-inline-asm.ll

; CHECK-LABEL: test_zero_reg:
 
   tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind
 ; CHECK: USE(xzr)
 
   tail call void asm sideeffect "USE(${0:w})", "zr"(i32 0)
 ; CHECK: USE(wzr)
 
   tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1)
-; CHECK: orr [[VAL1:w[0-9]+]], wzr, #0x1
+; CHECK: mov [[VAL1:w[0-9]+]], #1
 ; CHECK: USE([[VAL1]])
 
   tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind
 ; CHECK: USE(xzr), USE(xzr)
 
   tail call void asm sideeffect "USE($0), USE(${1:w})", "z,z"(i32 0, i32 0) nounwind
 ; CHECK: USE(xzr), USE(wzr)
 

test/CodeGen/AArch64/arm64-memcpy-inline.ll

 ; CHECK: str [[DEST]], [x0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i1 false)
   ret void
 }
 
 define void @t4(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t4:
-; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x20
+; CHECK: mov [[REG5:w[0-9]+]], #32
 ; CHECK: strh [[REG5]], [x0, #16]
 ; CHECK: ldr [[REG6:q[0-9]+]], [x{{[0-9]+}}]
 ; CHECK: str [[REG6]], [x0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i1 false)
   ret void
 }
 
 define void @t5(i8* nocapture %C) nounwind {

test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll

 ; RUN: llc -mtriple=arm64-apple-ios -mattr=+strict-align < %s | FileCheck %s
 
 ; Small (16 bytes here) unaligned memcpy() should be a function call if
 ; strict-alignment is turned on.
 define void @t0(i8* %out, i8* %in) {
 ; CHECK-LABEL: t0:
-; CHECK:      orr w2, wzr, #0x10
+; CHECK:      mov w2, #16
 ; CHECK-NEXT: bl _memcpy
 entry:
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 16, i1 false)
   ret void
 }
 
 ; Small (16 bytes here) aligned memcpy() should be inlined even if
 ; strict-alignment is turned on.

test/CodeGen/AArch64/arm64-movi.ll

 ; CHECK-LABEL: test64_64_manybits:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x0, #4503599627304960
 ; CHECK-NEXT:    ret
   ret i64 4503599627304960
 }
 
 ; 64-bit immed with 64-bit pattern size, one bit.
-; FIXME: Prefer movz, so it prints as "mov".
 define i64 @test64_64_onebit() nounwind {
 ; CHECK-LABEL: test64_64_onebit:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr x0, xzr, #0x4000000000
+; CHECK-NEXT:    mov x0, #274877906944
 ; CHECK-NEXT:    ret
   ret i64 274877906944
 }
 
 ; 32-bit immed with 32-bit pattern size, rotated by 16.
-; FIXME: Prefer "movz" instead (so we print as "mov").
 define i32 @test32_32_rot16() nounwind {
 ; CHECK-LABEL: test32_32_rot16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0xff0000
+; CHECK-NEXT:    mov w0, #16711680
 ; CHECK-NEXT:    ret
   ret i32 16711680
 }
 
 ; 32-bit immed with 2-bit pattern size, rotated by 1.
 define i32 @test32_2_rot1() nounwind {
 ; CHECK-LABEL: test32_2_rot1:
 ; CHECK:       // %bb.0:

test/CodeGen/AArch64/arm64-neon-compare-instructions.ll

 ;CHECK: movi v[[ZERO:[0-9]+]].4s, #2
 ;CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, v[[ZERO]].4s
   %tmp3 = icmp uge <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2>
    %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
-;CHECK: orr w[[TWO:[0-9]+]], wzr, #0x2
+;CHECK: mov w[[TWO:[0-9]+]], #2
 ;CHECK-NEXT: dup v[[ZERO:[0-9]+]].2d, x[[TWO]]
 ;CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, v[[ZERO]].2d
   %tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2>
    %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 

 ;CHECK: movi v[[ZERO:[0-9]+]].4s, #1
 ;CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, v[[ZERO]].4s
   %tmp3 = icmp ugt <4 x i32> %A, <i32 1, i32 1, i32 1, i32 1>
    %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
-;CHECK: orr w[[ONE:[0-9]+]], wzr, #0x1
+;CHECK: mov w[[ONE:[0-9]+]], #1
 ;CHECK-NEXT: dup v[[ZERO:[0-9]+]].2d, x[[ONE]]
 ;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, v[[ZERO]].2d
   %tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1>
    %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
;CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v[[ZERO]].4s, v0.4s
   %tmp3 = icmp ult <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2>
    %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
 ; Using registers other than v0, v1 are possible, but would be odd.
 ; LO implemented as HI, so check reversed operands.
-;CHECK: orr w[[TWO:[0-9]+]], wzr, #0x2
+;CHECK: mov w[[TWO:[0-9]+]], #2
 ;CHECK-NEXT: dup v[[ZERO:[0-9]+]].2d, x[[TWO]]
 ;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v[[ZERO]].2d, v0.2d
   %tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2>
    %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <1 x i64> @cmeqz_v1i64(<1 x i64> %A) {

test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll

; FAST-NEXT:   blr x16
   tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
   ret void
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen2(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen2:
-; CHECK:       orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK:       mov w[[REG:[0-9]+]], #6
 ; CHECK-NEXT:  str x[[REG]], [sp, #24]
-; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x4
+; CHECK-NEXT:  mov w[[REG:[0-9]+]], #4
 ; CHECK-NEXT:  str w[[REG]], [sp, #16]
-; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x2
+; CHECK-NEXT:  mov w[[REG:[0-9]+]], #2
 ; CHECK-NEXT:  str x[[REG]], [sp]
 ; CHECK:       Ltmp
 ; CHECK-NEXT:  mov  x16, #281470681743360
 ; CHECK-NEXT:  movk  x16, #57005, lsl #16
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen2:
-; FAST:        orr [[REG1:x[0-9]+]], xzr, #0x2
+; FAST:        mov [[REG1:x[0-9]+]], #2
 ; FAST-NEXT:   str [[REG1]], [sp]
-; FAST-NEXT:   orr [[REG2:w[0-9]+]], wzr, #0x4
+; FAST-NEXT:   mov [[REG2:w[0-9]+]], #4
 ; FAST-NEXT:   str [[REG2]], [sp, #16]
-; FAST-NEXT:   orr [[REG3:x[0-9]+]], xzr, #0x6
+; FAST-NEXT:   mov [[REG3:x[0-9]+]], #6
 ; FAST-NEXT:   str [[REG3]], [sp, #24]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov  x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16
   %call = inttoptr i64 281474417671919 to i8*
   %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
   ret i64 %result
 }
 
 ; Test if the arguments are properly aligned and that we don't store undef arguments.
 define i64 @jscall_patchpoint_codegen3(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen3:
 ; CHECK:       mov  w[[REG:[0-9]+]], #10
 ; CHECK-NEXT:  str x[[REG]], [sp, #48]
-; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x8
+; CHECK-NEXT:  mov w[[REG:[0-9]+]], #8
 ; CHECK-NEXT:  str w[[REG]], [sp, #36]
-; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x6
+; CHECK-NEXT:  mov w[[REG:[0-9]+]], #6
 ; CHECK-NEXT:  str x[[REG]], [sp, #24]
-; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x4
+; CHECK-NEXT:  mov w[[REG:[0-9]+]], #4
 ; CHECK-NEXT:  str w[[REG]], [sp, #16]
-; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x2
+; CHECK-NEXT:  mov w[[REG:[0-9]+]], #2
 ; CHECK-NEXT:  str x[[REG]], [sp]
 ; CHECK:       Ltmp
 ; CHECK-NEXT:  mov   x16, #281470681743360
 ; CHECK-NEXT:  movk  x16, #57005, lsl #16
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen3:
-; FAST:        orr [[REG1:x[0-9]+]], xzr, #0x2
+; FAST:        mov [[REG1:x[0-9]+]], #2
 ; FAST-NEXT:   str [[REG1]], [sp]
-; FAST-NEXT:   orr [[REG2:w[0-9]+]], wzr, #0x4
+; FAST-NEXT:   mov [[REG2:w[0-9]+]], #4
 ; FAST-NEXT:   str [[REG2]], [sp, #16]
-; FAST-NEXT:   orr [[REG3:x[0-9]+]], xzr, #0x6
+; FAST-NEXT:   mov [[REG3:x[0-9]+]], #6
 ; FAST-NEXT:   str [[REG3]], [sp, #24]
-; FAST-NEXT:   orr [[REG4:w[0-9]+]], wzr, #0x8
+; FAST-NEXT:   mov [[REG4:w[0-9]+]], #8
 ; FAST-NEXT:   str [[REG4]], [sp, #36]
 ; FAST-NEXT:   mov [[REG5:x[0-9]+]], #10
 ; FAST-NEXT:   str [[REG5]], [sp, #48]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov   x16, #281470681743360
 ; FAST-NEXT:   movk  x16, #57005, lsl #16
 ; FAST-NEXT:   movk  x16, #48879
 ; FAST-NEXT:   blr x16

test/CodeGen/AArch64/atomic-ops-lse.ll

 
 define i8 @test_atomic_load_sub_i8_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_neg_imm:
   %old = atomicrmw sub i8* @var8, i8 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
-; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddalb w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_neg_imm:
   %old = atomicrmw sub i16* @var16, i16 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
-; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddalh w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_neg_imm:
   %old = atomicrmw sub i32* @var32, i32 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
-; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddal w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_neg_imm:
   %old = atomicrmw sub i64* @var64, i64 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
-; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddal x[[IMM]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define i8 @test_atomic_load_sub_i8_neg_arg(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_neg_arg:

 }
 
 define i8 @test_atomic_load_and_i8_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_inv_imm:
   %old = atomicrmw and i8* @var8, i8 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
-; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclralb w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_inv_imm:
   %old = atomicrmw and i16* @var16, i16 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
-; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclralh w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_inv_imm:
   %old = atomicrmw and i32* @var32, i32 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
-; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclral w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_inv_imm:
   %old = atomicrmw and i64* @var64, i64 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
-; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
+; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclral x[[CONST]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define i8 @test_atomic_load_and_i8_inv_arg(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_inv_arg:
   %inv = xor i8 %offset, -1

test/CodeGen/AArch64/branch-relax-asm.ll

 ; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %s | FileCheck %s
 define i32 @test_asm_length(i32 %in) {
 ; CHECK-LABEL: test_asm_length:
 
   ; It would be more natural to use just one "tbnz %false" here, but if the
   ; number of instructions in the asm is counted reasonably, that block is out
   ; of the limited range we gave tbz. So branch relaxation has to invert the
   ; condition.
 ; CHECK:     tbz w0, #0, [[TRUE:LBB[0-9]+_[0-9]+]]
 ; CHECK:     b [[FALSE:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: [[TRUE]]:
-; CHECK:     orr w0, wzr, #0x4
+; CHECK:     mov w0, #4
 ; CHECK:     nop
 ; CHECK:     nop
 ; CHECK:     nop
 ; CHECK:     nop
 ; CHECK:     nop
 ; CHECK:     nop
 ; CHECK:     ret
 

test/CodeGen/AArch64/branch-relax-bcc.ll

 ; CHECK-NEXT: b.le [[IF_THEN_BB]]
 ; CHECK-NEXT: b [[IF_END_BB:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: [[IF_THEN_BB]]:
 ; CHECK: bl _foo
 ; CHECK-NOT: b L
 
 ; CHECK: [[IF_END_BB]]:
-; CHECK: #0x7
+; CHECK: mov{{.*}}, #7
 ; CHECK: ret
 define i32 @block_split(i32 %a, i32 %b) #0 {
 entry:
   %cmp = icmp eq i32 %a, 5
   br i1 %cmp, label %if.then, label %lor.lhs.false
 
 lor.lhs.false:                                    ; preds = %entry
   %cmp1 = icmp slt i32 %b, 7

test/CodeGen/AArch64/bswap-known-bits.ll

 ; RUN: llc < %s -mtriple=aarch64-apple-darwin  | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 declare i32 @llvm.bswap.i32(i32)
 
 ; CHECK-LABEL: @test1
-; CHECK: orr w0, wzr, #0x1
+; CHECK: mov w0, #1
 define i1 @test1(i16 %arg) {
   %a = or i16 %arg, 511
   %b = call i16 @llvm.bswap.i16(i16 %a)
   %and = and i16 %b, 256
   %res = icmp eq i16 %and, 256
   ret i1 %res
 }
 
 ; CHECK-LABEL: @test2
-; CHECK: orr w0, wzr, #0x1
+; CHECK: mov w0, #1
 define i1 @test2(i16 %arg) {
   %a = or i16 %arg, 1
   %b = call i16 @llvm.bswap.i16(i16 %a)
   %and = and i16 %b, 256
   %res = icmp eq i16 %and, 256
   ret i1 %res
 }
 
 ; CHECK-LABEL: @test3
-; CHECK: orr w0, wzr, #0x1
+; CHECK: mov w0, #1
 define i1 @test3(i16 %arg) {
   %a = or i16 %arg, 256
   %b = call i16 @llvm.bswap.i16(i16 %a)
   %and = and i16 %b, 1
   %res = icmp eq i16 %and, 1
   ret i1 %res
 }
 
 ; CHECK-LABEL: @test4
-; CHECK: orr w0, wzr, #0x1
+; CHECK: mov w0, #1
 define i1 @test4(i32 %arg) {
   %a = or i32 %arg, 2147483647  ; i32_MAX
   %b = call i32 @llvm.bswap.i32(i32 %a)
   %and = and i32 %b, 127
   %res = icmp eq i32 %and, 127
   ret i1 %res
 }

test/CodeGen/AArch64/cmpxchg-idioms.ll

 ; RUN: llc -mtriple=aarch64-apple-ios7.0 -o - %s | FileCheck %s
 
 define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
 ; CHECK-LABEL: test_return:
 
 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
 ; CHECK: cmp [[LOADED]], w1
 ; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: stlxr [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
 ; CHECK: cbnz [[STATUS]], [[LOOP]]
 
 ; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK: orr w0, wzr, #0x1
+; CHECK: mov w0, #1
 ; CHECK: ret
 
 ; CHECK: [[FAILED]]:
 ; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
 ; CHECK: mov w0, wzr
 ; CHECK: ret
 
   %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst

 ; CHECK: cmp [[LOADED]], w1, uxtb
 ; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: stlxrb [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
 ; CHECK: cbnz [[STATUS]], [[LOOP]]
 
 ; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
   ; FIXME: DAG combine should be able to deal with this.
-; CHECK: orr [[TMP:w[0-9]+]], wzr, #0x1
+; CHECK: mov [[TMP:w[0-9]+]], #1
 ; CHECK: eor w0, [[TMP]], #0x1
 ; CHECK: ret
 
 ; CHECK: [[FAILED]]:
 ; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
 ; CHECK: eor w0, wzr, #0x1
 ; CHECK: ret
 

 ; CHECK-LABEL: test_conditional2:
 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x19]
 ; CHECK: cmp [[LOADED]], w21
 ; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: stlxr [[STATUS:w[0-9]+]], w20, [x19]
 ; CHECK: cbnz [[STATUS]], [[LOOP]]
-; CHECK: orr [[STATUS]], wzr, #0x1
+; CHECK: mov [[STATUS]], #1
 ; CHECK: b [[PH:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: [[FAILED]]:
 ; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
 
 ; verify the preheader is simplified by simplifycfg.
 ; CHECK: [[PH]]:
-; CHECK: orr w22, wzr, #0x2
-; CHECK-NOT: orr w22, wzr, #0x4
+; CHECK: mov w22, #2
+; CHECK-NOT: mov w22, #4
 ; CHECK-NOT: cmn w22, #4
 ; CHECK: b [[LOOP2:LBB[0-9]+_[0-9]+]]
 ; CHECK-NOT: b.ne [[LOOP2]]
 ; CHECK-NOT: b {{LBB[0-9]+_[0-9]+}}
 ; CHECK: bl _foo
 entry:
   %pair = cmpxchg i32* %c, i32 %a, i32 %b seq_cst seq_cst
   %success = extractvalue { i32, i1 } %pair, 1

test/CodeGen/AArch64/cond-sel-value-prop.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 ; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
 ; CHECK-LABEL: test1:
 ; CHECK: cmp w[[REG1:[0-9]+]], #2
-; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x7
+; CHECK: mov w[[REG2:[0-9]+]], #7
 ; CHECK: csel w0, w[[REG1]], w[[REG2]], eq
 define i32 @test1(i32 %x) {
   %cmp = icmp eq i32 %x, 2
   %res = select i1 %cmp, i32 2, i32 7
   ret i32 %res
 }
 
 ; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
 ; CHECK-LABEL: test2:
 ; CHECK: cmp x[[REG1:[0-9]+]], #2
-; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x7
+; CHECK: mov w[[REG2:[0-9]+]], #7
 ; CHECK: csel x0, x[[REG1]], x[[REG2]], eq
 define i64 @test2(i64 %x) {
   %cmp = icmp eq i64 %x, 2
   %res = select i1 %cmp, i64 2, i64 7
   ret i64 %res
 }
 
 ; Transform "a != C ? x : C" to "a != C ? x : a" to avoid materializing C.
 ; CHECK-LABEL: test3:
 ; CHECK: cmp x[[REG1:[0-9]+]], #7
-; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x2
+; CHECK: mov w[[REG2:[0-9]+]], #2
 ; CHECK: csel x0, x[[REG2]], x[[REG1]], ne
 define i64 @test3(i64 %x) {
   %cmp = icmp ne i64 %x, 7
   %res = select i1 %cmp, i64 2, i64 7
   ret i64 %res
 }
 
 ; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 0.  If we did we
 ; would needlessly extend the live range of x0 when we can just use xzr.
 ; CHECK-LABEL: test4:
 ; CHECK: cmp x0, #0
-; CHECK: orr w8, wzr, #0x7
+; CHECK: mov w8, #7
 ; CHECK: csel x0, xzr, x8, eq
 define i64 @test4(i64 %x) {
   %cmp = icmp eq i64 %x, 0
   %res = select i1 %cmp, i64 0, i64 7
   ret i64 %res
 }
 
 ; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == 1.  If we did we
 ; would needlessly extend the live range of x0 when we can just use xzr with
 ; CSINC to materialize the 1.
 ; CHECK-LABEL: test5:
 ; CHECK: cmp x0, #1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x7
+; CHECK: mov w[[REG:[0-9]+]], #7
 ; CHECK: csinc x0, x[[REG]], xzr, ne
 define i64 @test5(i64 %x) {
   %cmp = icmp eq i64 %x, 1
   %res = select i1 %cmp, i64 1, i64 7
   ret i64 %res
 }
 
 ; Don't transform "a == C ? C : x" to "a == C ? a : x" if a == -1.  If we did we
 ; would needlessly extend the live range of x0 when we can just use xzr with
 ; CSINV to materialize the -1.
 ; CHECK-LABEL: test6:
 ; CHECK: cmn x0, #1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x7
+; CHECK: mov w[[REG:[0-9]+]], #7
 ; CHECK: csinv x0, x[[REG]], xzr, ne
 define i64 @test6(i64 %x) {
   %cmp = icmp eq i64 %x, -1
   %res = select i1 %cmp, i64 -1, i64 7
   ret i64 %res
 }
 
 ; CHECK-LABEL: test7:

test/CodeGen/AArch64/cond-sel.ll

 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt
 
 
   %tst2 = fcmp ueq double %lhs64, %rhs64
 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK-NOFP-NOT: fcmp
   %val2 = select i1 %tst2, i64 9, i64 15
   store i64 %val2, i64* @var64
-; CHECK: orr w[[CONST15:[0-9]+]], wzr, #0xf
+; CHECK: mov w[[CONST15:[0-9]+]], #15
 ; CHECK: mov {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}}
 ; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq
 ; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs
 
   ret void
 ; CHECK: ret
 }
 

test/CodeGen/AArch64/dag-combine-invaraints.ll

main_:
   %tmp10 = load i32, i32* %i32F, align 4
   %DHSelect = select i1 %tmp8, i32 %tmp9, i32 %tmp10
   store i32 %DHSelect, i32* %i32X, align 4
   %tmp15 = load i32, i32* %i32X, align 4
   %tmp17 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str2, i32 0, i32 0), i32 %tmp15)
   ret i32 0
 
 ; CHECK: main:
-; CHECK-DAG: mov
-; CHECK-DAG: orr
+; CHECK-DAG: mov {{.*}}, #15
+; CHECK-DAG: mov {{.*}}, #5
 ; CHECK: csel
 }
 
 
 declare i32 @printf(i8*, ...) #1
 
 attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/AArch64/extract-bits.ll

 
 ; ---------------------------------------------------------------------------- ;
 ; Pattern a. 32-bit
 ; ---------------------------------------------------------------------------- ;
 
 define i32 @bextr32_a0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_a0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    lsr w8, w0, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %shifted = lshr i32 %val, %numskipbits
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %shifted
   ret i32 %masked
 }
 
 define i32 @bextr32_a0_arithmetic(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_a0_arithmetic:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    asr w8, w0, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %shifted = ashr i32 %val, %numskipbits
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %shifted
   ret i32 %masked
 }
 
 define i32 @bextr32_a1_indexzext(i32 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_a1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    lsr w8, w0, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %skip = zext i8 %numskipbits to i32
   %shifted = lshr i32 %val, %skip
   %conv = zext i8 %numlowbits to i32
   %onebit = shl i32 1, %conv
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %shifted
   ret i32 %masked
 }
 
 define i32 @bextr32_a2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_a2_load:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    lsr w8, w8, w1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
   %shifted = lshr i32 %val, %numskipbits
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %shifted
   ret i32 %masked
 }
 
 define i32 @bextr32_a3_load_indexzext(i32* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_a3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    lsr w8, w8, w1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
   %skip = zext i8 %numskipbits to i32
   %shifted = lshr i32 %val, %skip
   %conv = zext i8 %numlowbits to i32
   %onebit = shl i32 1, %conv
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %shifted
   ret i32 %masked
 }
 
 define i32 @bextr32_a4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_a4_commutative:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    lsr w8, w0, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w8, w9
 ; CHECK-NEXT:    ret
   %shifted = lshr i32 %val, %numskipbits
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %shifted, %mask ; swapped order
   ret i32 %masked
 }
 
 ; 64-bit
 
 define i64 @bextr64_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_a0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl x9, x9, x2
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %shifted = lshr i64 %val, %numskipbits
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %shifted
   ret i64 %masked
 }
 
 define i64 @bextr64_a0_arithmetic(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_a0_arithmetic:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl x9, x9, x2
 ; CHECK-NEXT:    asr x8, x0, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %shifted = ashr i64 %val, %numskipbits
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %shifted
   ret i64 %masked
 }
 
 define i64 @bextr64_a1_indexzext(i64 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_a1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
 ; CHECK-NEXT:    lsl x9, x9, x2
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %skip = zext i8 %numskipbits to i64
   %shifted = lshr i64 %val, %skip
   %conv = zext i8 %numlowbits to i64
   %onebit = shl i64 1, %conv
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %shifted
   ret i64 %masked
 }
 
 define i64 @bextr64_a2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_a2_load:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl x9, x9, x2
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    lsr x8, x8, x1
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
   %shifted = lshr i64 %val, %numskipbits
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %shifted
   ret i64 %masked
 }
 
 define i64 @bextr64_a3_load_indexzext(i64* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_a3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
 ; CHECK-NEXT:    lsl x9, x9, x2
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    lsr x8, x8, x1
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
   %skip = zext i8 %numskipbits to i64
   %shifted = lshr i64 %val, %skip
   %conv = zext i8 %numlowbits to i64
   %onebit = shl i64 1, %conv
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %shifted
   ret i64 %masked
 }
 
 define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_a4_commutative:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl x9, x9, x2
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    and x0, x8, x9
 ; CHECK-NEXT:    ret
   %shifted = lshr i64 %val, %numskipbits
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %shifted, %mask ; swapped order
   ret i64 %masked
 }
 
 ; 64-bit, but with 32-bit output
 
 ; Everything done in 64-bit, truncation happens last.
 define i32 @bextr64_32_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_32_a0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl x9, x9, x2
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %shifted = lshr i64 %val, %numskipbits
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %shifted
   %res = trunc i64 %masked to i32
   ret i32 %res
 }
 
 ; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
 define i32 @bextr64_32_a1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_32_a1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %shifted = lshr i64 %val, %numskipbits
   %truncshifted = trunc i64 %shifted to i32
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %truncshifted
   ret i32 %masked
 }
 
 ; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit.
 ; Masking is 64-bit. Then truncation.
 define i32 @bextr64_32_a2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_32_a2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w2
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %shifted = lshr i64 %val, %numskipbits
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
; CHECK-NEXT:    ret
   %mask = lshr i32 -1, %numhighbits
   %masked = and i32 %mask, %shifted
   ret i32 %masked
 }
 
 define i32 @bextr32_c1_indexzext(i32 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_c1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    mov w10, #-1
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsr w8, w0, w1
 ; CHECK-NEXT:    lsr w9, w10, w9
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %skip = zext i8 %numskipbits to i32
; CHECK-NEXT:    ret
   %masked = and i32 %mask, %shifted
   ret i32 %masked
 }
 
 define i32 @bextr32_c3_load_indexzext(i32* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_c3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    mov w10, #-1
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsr w8, w8, w1
 ; CHECK-NEXT:    lsr w9, w10, w9
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
; CHECK-NEXT:    ret
   %mask = lshr i64 -1, %numhighbits
   %masked = and i64 %mask, %shifted
   ret i64 %masked
 }
 
 define i64 @bextr64_c1_indexzext(i64 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_c1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    mov x10, #-1
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    lsr x9, x10, x9
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %skip = zext i8 %numskipbits to i64
; CHECK-NEXT:    ret
   %masked = and i64 %mask, %shifted
   ret i64 %masked
 }
 
 define i64 @bextr64_c3_load_indexzext(i64* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_c3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    mov x10, #-1
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsr x8, x8, x1
 ; CHECK-NEXT:    lsr x9, x10, x9
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
; CHECK-NEXT:    ret
   %highbitscleared = shl i32 %shifted, %numhighbits
   %masked = lshr i32 %highbitscleared, %numhighbits
   ret i32 %masked
 }
 
 define i32 @bextr32_d1_indexzext(i32 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_d1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsr w8, w0, w1
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    lsl w8, w8, w9
 ; CHECK-NEXT:    lsr w0, w8, w9
 ; CHECK-NEXT:    ret
   %skip = zext i8 %numskipbits to i32
   %shifted = lshr i32 %val, %skip
; CHECK-NEXT:    ret
   %masked = lshr i32 %highbitscleared, %numhighbits
   ret i32 %masked
 }
 
 define i32 @bextr32_d3_load_indexzext(i32* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr32_d3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    lsr w8, w8, w1
 ; CHECK-NEXT:    lsl w8, w8, w9
 ; CHECK-NEXT:    lsr w0, w8, w9
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
   %skip = zext i8 %numskipbits to i32
; CHECK-NEXT:    ret
   %highbitscleared = shl i64 %shifted, %numhighbits
   %masked = lshr i64 %highbitscleared, %numhighbits
   ret i64 %masked
 }
 
 define i64 @bextr64_d1_indexzext(i64 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_d1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsr x8, x0, x1
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    lsl x8, x8, x9
 ; CHECK-NEXT:    lsr x0, x8, x9
 ; CHECK-NEXT:    ret
   %skip = zext i8 %numskipbits to i64
   %shifted = lshr i64 %val, %skip
; CHECK-NEXT:    ret
   %masked = lshr i64 %highbitscleared, %numhighbits
   ret i64 %masked
 }
 
 define i64 @bextr64_d3_load_indexzext(i64* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bextr64_d3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    sub w9, w9, w2
 ; CHECK-NEXT:    lsr x8, x8, x1
 ; CHECK-NEXT:    lsl x8, x8, x9
 ; CHECK-NEXT:    lsr x0, x8, x9
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
   %skip = zext i8 %numskipbits to i64

test/CodeGen/AArch64/extract-lowbits.ll

 
 ; ---------------------------------------------------------------------------- ;
 ; Pattern a. 32-bit
 ; ---------------------------------------------------------------------------- ;
 
 define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    sub w8, w8, #1 // =1
 ; CHECK-NEXT:    and w0, w8, w0
 ; CHECK-NEXT:    ret
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    sub w8, w8, #1 // =1
 ; CHECK-NEXT:    and w0, w8, w0
 ; CHECK-NEXT:    ret
   %conv = zext i8 %numlowbits to i32
   %onebit = shl i32 1, %conv
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @bzhi32_a2_load(i32* %w, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a2_load:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w9, w9, w1
 ; CHECK-NEXT:    sub w9, w9, #1 // =1
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
   %conv = zext i8 %numlowbits to i32
   %onebit = shl i32 1, %conv
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_a4_commutative:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    sub w8, w8, #1 // =1
 ; CHECK-NEXT:    and w0, w0, w8
 ; CHECK-NEXT:    ret
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1
   %masked = and i32 %val, %mask ; swapped order
   ret i32 %masked
 }
 
 ; 64-bit
 
 define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a0:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl x8, x8, x1
 ; CHECK-NEXT:    sub x8, x8, #1 // =1
 ; CHECK-NEXT:    and x0, x8, x0
 ; CHECK-NEXT:    ret
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl x8, x8, x1
 ; CHECK-NEXT:    sub x8, x8, #1 // =1
 ; CHECK-NEXT:    and x0, x8, x0
 ; CHECK-NEXT:    ret
   %conv = zext i8 %numlowbits to i64
   %onebit = shl i64 1, %conv
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @bzhi64_a2_load(i64* %w, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a2_load:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl x9, x9, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x1
+; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl x9, x9, x1
 ; CHECK-NEXT:    sub x9, x9, #1 // =1
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
   %conv = zext i8 %numlowbits to i64
   %onebit = shl i64 1, %conv
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_a4_commutative:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    lsl x8, x8, x1
 ; CHECK-NEXT:    sub x8, x8, #1 // =1
 ; CHECK-NEXT:    and x0, x0, x8
 ; CHECK-NEXT:    ret
   %onebit = shl i64 1, %numlowbits
   %mask = add nsw i64 %onebit, -1
   %masked = and i64 %val, %mask ; swapped order
   ret i64 %masked
; CHECK-NEXT:    ret
   %mask = lshr i32 -1, %numhighbits
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_c1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x20
+; CHECK-NEXT:    mov w8, #32
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    mov w9, #-1
 ; CHECK-NEXT:    lsr w8, w9, w8
 ; CHECK-NEXT:    and w0, w8, w0
 ; CHECK-NEXT:    ret
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32
   %mask = lshr i32 -1, %sh_prom
; CHECK-NEXT:    ret
   %masked = and i32 %mask, %val
   ret i32 %masked
 }
 
 define i32 @bzhi32_c3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_c3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    mov w10, #-1
 ; CHECK-NEXT:    lsr w9, w10, w9
 ; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32
; CHECK-NEXT:    ret
   %mask = lshr i64 -1, %numhighbits
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @bzhi64_c1_indexzext(i64 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_c1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x40
+; CHECK-NEXT:    mov w8, #64
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    mov x9, #-1
 ; CHECK-NEXT:    lsr x8, x9, x8
 ; CHECK-NEXT:    and x0, x8, x0
 ; CHECK-NEXT:    ret
   %numhighbits = sub i8 64, %numlowbits
   %sh_prom = zext i8 %numhighbits to i64
   %mask = lshr i64 -1, %sh_prom
; CHECK-NEXT:    ret
   %masked = and i64 %mask, %val
   ret i64 %masked
 }
 
 define i64 @bzhi64_c3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_c3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    mov x10, #-1
 ; CHECK-NEXT:    lsr x9, x10, x9
 ; CHECK-NEXT:    and x0, x9, x8
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
   %numhighbits = sub i8 64, %numlowbits
   %sh_prom = zext i8 %numhighbits to i64
; CHECK-NEXT:    ret
   %highbitscleared = shl i32 %val, %numhighbits
   %masked = lshr i32 %highbitscleared, %numhighbits
   ret i32 %masked
 }
 
 define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_d1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x20
+; CHECK-NEXT:    mov w8, #32
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    lsl w9, w0, w8
 ; CHECK-NEXT:    lsr w0, w9, w8
 ; CHECK-NEXT:    ret
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32
   %highbitscleared = shl i32 %val, %sh_prom
   %masked = lshr i32 %highbitscleared, %sh_prom
; CHECK-NEXT:    ret
   %masked = lshr i32 %highbitscleared, %numhighbits
   ret i32 %masked
 }
 
 define i32 @bzhi32_d3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi32_d3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x20
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    lsl w8, w8, w9
 ; CHECK-NEXT:    lsr w0, w8, w9
 ; CHECK-NEXT:    ret
   %val = load i32, i32* %w
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32
   %highbitscleared = shl i32 %val, %sh_prom
; CHECK-NEXT:    ret
   %highbitscleared = shl i64 %val, %numhighbits
   %masked = lshr i64 %highbitscleared, %numhighbits
   ret i64 %masked
 }
 
 define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_d1_indexzext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x40
+; CHECK-NEXT:    mov w8, #64
 ; CHECK-NEXT:    sub w8, w8, w1
 ; CHECK-NEXT:    lsl x9, x0, x8
 ; CHECK-NEXT:    lsr x0, x9, x8
 ; CHECK-NEXT:    ret
   %numhighbits = sub i8 64, %numlowbits
   %sh_prom = zext i8 %numhighbits to i64
   %highbitscleared = shl i64 %val, %sh_prom
   %masked = lshr i64 %highbitscleared, %sh_prom
; CHECK-NEXT:    ret
   %masked = lshr i64 %highbitscleared, %numhighbits
   ret i64 %masked
 }
 
 define i64 @bzhi64_d3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
 ; CHECK-LABEL: bzhi64_d3_load_indexzext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr x8, [x0]
-; CHECK-NEXT:    orr w9, wzr, #0x40
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub w9, w9, w1
 ; CHECK-NEXT:    lsl x8, x8, x9
 ; CHECK-NEXT:    lsr x0, x8, x9
 ; CHECK-NEXT:    ret
   %val = load i64, i64* %w
   %numhighbits = sub i8 64, %numlowbits
   %sh_prom = zext i8 %numhighbits to i64
   %highbitscleared = shl i64 %val, %sh_prom

test/CodeGen/AArch64/fabs.ll

; CHECK-NEXT:    ret
   ret double %cond
 }
 
 ; Try again with different type, predicate, and compare constant.
 
 define float @still_not_fabs(float %x) #0 {
 ; CHECK-LABEL: still_not_fabs:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x80000000
+; CHECK-NEXT:    mov w8, #-2147483648
 ; CHECK-NEXT:    fmov s2, w8
 ; CHECK-NEXT:    fneg s1, s0
 ; CHECK-NEXT:    fcmp s0, s2
 ; CHECK-NEXT:    fcsel s0, s0, s1, ge
 ; CHECK-NEXT:    ret
   %cmp = fcmp nnan oge float %x, -0.0
   %sub = fsub nnan float -0.0, %x
   %cond = select i1 %cmp, float %x, float %sub
; CHECK-NEXT:    ret
   %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
   %conv1 = bitcast <4 x i32> %and to <4 x float>
   ret <4 x float> %conv1
 }
 
 define <2 x double> @nabsv2d64(<2 x double> %a) {
 ; CHECK-LABEL: nabsv2d64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr x8, xzr, #0x8000000000000000
+; CHECK-NEXT:    mov x8, #-9223372036854775808
 ; CHECK-NEXT:    dup v1.2d, x8
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
   %conv = bitcast <2 x double> %a to <2 x i64>
   %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
   %conv1 = bitcast <2 x i64> %and to <2 x double>
   ret <2 x double> %conv1
 }
 
 attributes #0 = { "no-nans-fp-math"="true" }
 

test/CodeGen/AArch64/fast-isel-addressing-modes.ll

 ; CHECK:       str xzr, [x0]
   store double 0.0, double* %a
   ret void
 }
 
 ; Load Immediate
 define i32 @load_immoff_1() {
 ; CHECK-LABEL: load_immoff_1
-; CHECK:       orr {{w|x}}[[REG:[0-9]+]], {{wzr|xzr}}, #0x80
+; CHECK:       mov {{w|x}}[[REG:[0-9]+]], #128
 ; CHECK:       ldr {{w[0-9]+}}, {{\[}}x[[REG]]{{\]}}
   %1 = inttoptr i64 128 to i32*
   %2 = load i32, i32* %1
   ret i32 %2
 }
 
 ; Load / Store Base Register + Immediate Offset
 ; Max supported negative offset
; CHECK:       ldr {{w[0-9]+}}, [x0, #16380]
   %2 = inttoptr i64 %1 to i32*
   %3 = load i32, i32* %2
   ret i32 %3
 }
 
 ; Min un-supported scaled offset
 define i32 @load_breg_immoff_6(i64 %a) {
 ; SDAG-LABEL: load_breg_immoff_6
-; SDAG:       orr w[[NUM:[0-9]+]], wzr, #0x4000
+; SDAG:       mov w[[NUM:[0-9]+]], #16384
 ; SDAG-NEXT:  ldr {{w[0-9]+}}, [x0, x[[NUM]]]
 ; FAST-LABEL: load_breg_immoff_6
 ; FAST:       add [[REG:x[0-9]+]], x0, #4, lsl #12
 ; FAST-NEXT:  ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
   %1 = add i64 %a, 16384
   %2 = inttoptr i64 %1 to i32*
   %3 = load i32, i32* %2
   ret i32 %3
; CHECK:       str wzr, [x0, #16380]
   %2 = inttoptr i64 %1 to i32*
   store i32 0, i32* %2
   ret void
 }
 
 ; Min un-supported scaled offset
 define void @store_breg_immoff_6(i64 %a) {
 ; SDAG-LABEL: store_breg_immoff_6
-; SDAG:       orr w[[NUM:[0-9]+]], wzr, #0x4000
+; SDAG:       mov w[[NUM:[0-9]+]], #16384
 ; SDAG-NEXT:  str wzr, [x0, x[[NUM]]]
 ; FAST-LABEL: store_breg_immoff_6
 ; FAST:       add [[REG:x[0-9]+]], x0, #4, lsl #12
 ; FAST-NEXT:  str wzr, {{\[}}[[REG]]{{\]}}
   %1 = add i64 %a, 16384
   %2 = inttoptr i64 %1 to i32*
   store i32 0, i32* %2
   ret void
; CHECK-NEXT:  ldr x0, {{\[}}[[REG]], #48{{\]}}
   %3 = inttoptr i64 %2 to i64*
   %4 = load i64, i64* %3
   ret i64 %4
 }
 
 define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
 ; SDAG-LABEL: load_breg_offreg_immoff_2
 ; SDAG:       add [[REG1:x[0-9]+]], x0, x1
-; SDAG-NEXT:  orr w[[NUM:[0-9]+]], wzr, #0xf000
+; SDAG-NEXT:  mov w[[NUM:[0-9]+]], #61440
 ; SDAG-NEXT:  ldr x0, {{\[}}[[REG1]], x[[NUM]]]
 ; FAST-LABEL: load_breg_offreg_immoff_2
 ; FAST:       add [[REG:x[0-9]+]], x0, #15, lsl #12
 ; FAST-NEXT:  ldr x0, {{\[}}[[REG]], x1{{\]}}
   %1 = add i64 %a, %b
   %2 = add i64 %1, 61440
   %3 = inttoptr i64 %2 to i64*
   %4 = load i64, i64* %3

test/CodeGen/AArch64/fast-isel-gep.ll

 ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
 
 %struct.foo = type { i32, i64, float, double }
 
 define double* @test_struct(%struct.foo* %f) {
 ; CHECK-LABEL: test_struct
 ; CHECK:       add x0, x0, #24
   %1 = getelementptr inbounds %struct.foo, %struct.foo* %f, i64 0, i32 3
   ret double* %1
 }
 
 define i32* @test_array1(i32* %a, i64 %i) {
 ; CHECK-LABEL: test_array1
-; CHECK:       orr [[REG:x[0-9]+]], xzr, #0x4
+; CHECK:       mov [[REG:x[0-9]+]], #4
 ; CHECK-NEXT:  madd  x0, x1, [[REG]], x0
   %1 = getelementptr inbounds i32, i32* %a, i64 %i
   ret i32* %1
 }
 
 define i32* @test_array2(i32* %a) {
 ; CHECK-LABEL: test_array2
 ; CHECK:       add  x0, x0, #16

 ; CHECK-NEXT:  add x0, x0, [[REG]]
   %1 = getelementptr inbounds i32, i32* %a, i64 1026
   ret i32* %1
 }
 
 define i32* @test_array5(i32* %a, i32 %i) {
 ; CHECK-LABEL: test_array5
 ; CHECK:       sxtw [[REG1:x[0-9]+]], w1
-; CHECK-NEXT:  orr  [[REG2:x[0-9]+]], xzr, #0x4
+; CHECK-NEXT:  mov  [[REG2:x[0-9]+]], #4
 ; CHECK-NEXT:  madd  {{x[0-9]+}}, [[REG1]], [[REG2]], x0
   %1 = getelementptr inbounds i32, i32* %a, i32 %i
   ret i32* %1
 }

test/CodeGen/AArch64/fold-global-offsets.ll

define i64 @f5() {
   %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262143)
   ret i64 %l
 }
 
 define i64 @f6() {
   ; CHECK: f6:
   ; CHECK: adrp x8, x2
   ; CHECK: add x8, x8, :lo12:x2
-  ; CHECK: orr w9, wzr, #0x200000
+  ; CHECK: mov w9, #2097152
   ; CHECK: ldr x0, [x8, x9]
   ; CHECK: ret
   %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262144)
   ret i64 %l
 }
 
 define i32 @f7() {
 entry:
   ; CHECK: f7
   ; CHECK: adrp x8, x3+108
   ; CHECK: ldr w0, [x8, :lo12:x3+108]
   %l = load i32, i32* getelementptr (i32, i32* inttoptr (i64 trunc (i128 lshr (i128 bitcast (<2 x i64> <i64 undef, i64 ptrtoint (i8** getelementptr inbounds ({ [9 x i8*], [8 x i8*] }, { [9 x i8*], [8 x i8*] }* @x3, i64 0, inrange i32 1, i64 2) to i64)> to i128), i128 64) to i64) to i32*), i64 5)
   ret i32 %l
 }

test/CodeGen/AArch64/funnel-shift.ll

 ; CHECK-NEXT:    ret
   %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
   ret i7 %f
 }
 
 define i8 @fshl_i8_const_fold_overshift_1() {
 ; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0x80
+; CHECK-NEXT:    mov w0, #128
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
   ret i8 %f
 }
 
 define i8 @fshl_i8_const_fold_overshift_2() {
 ; CHECK-LABEL: fshl_i8_const_fold_overshift_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0x78
+; CHECK-NEXT:    mov w0, #120
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11)
   ret i8 %f
 }
 
 define i8 @fshl_i8_const_fold_overshift_3() {
 ; CHECK-LABEL: fshl_i8_const_fold_overshift_3:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
   ret i64 %f
 }
 
 ; This should work without any node-specific logic.
 
 define i8 @fshl_i8_const_fold() {
 ; CHECK-LABEL: fshl_i8_const_fold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0x80
+; CHECK-NEXT:    mov w0, #128
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
   ret i8 %f
 }
 
 ; Repeat everything for funnel shift right.
 
 ; General case - all operands can be variables.

 }
 
 ; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
 
 declare i7 @llvm.fshr.i7(i7, i7, i7)
 define i7 @fshr_i7_const_fold() {
 ; CHECK-LABEL: fshr_i7_const_fold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0x1f
+; CHECK-NEXT:    mov w0, #31
 ; CHECK-NEXT:    ret
   %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
   ret i7 %f
 }
 
 define i8 @fshr_i8_const_fold_overshift_1() {
 ; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0xfe
+; CHECK-NEXT:    mov w0, #254
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
   ret i8 %f
 }
 
 define i8 @fshr_i8_const_fold_overshift_2() {
 ; CHECK-LABEL: fshr_i8_const_fold_overshift_2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w0, #225
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
   ret i8 %f
 }
 
 define i8 @fshr_i8_const_fold_overshift_3() {
 ; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0xff
+; CHECK-NEXT:    mov w0, #255
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
   ret i8 %f
 }
 
 ; With constant shift amount, this is 'extr'.
 
 define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
; CHECK-NEXT:    ret
   ret i64 %f
 }
 
 ; This should work without any node-specific logic.
 
 define i8 @fshr_i8_const_fold() {
 ; CHECK-LABEL: fshr_i8_const_fold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0xfe
+; CHECK-NEXT:    mov w0, #254
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
   ret i8 %f
 }
 
 define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {
 ; CHECK-LABEL: fshl_i32_shift_by_bitwidth:
 ; CHECK:       // %bb.0:

test/CodeGen/AArch64/i128-align.ll

 ; RUN: llc -mtriple=arm64-apple-ios7.0 -verify-machineinstrs -o - %s | FileCheck %s
 
 %struct = type { i32, i128, i8 }
 
 @var = global %struct zeroinitializer
 
 define i64 @check_size() {
 ; CHECK-LABEL: check_size:
   %starti = ptrtoint %struct* @var to i64
 
   %endp = getelementptr %struct, %struct* @var, i64 1
   %endi = ptrtoint %struct* %endp to i64
 
   %diff = sub i64 %endi, %starti
   ret i64 %diff
-; CHECK: {{movz x0, #48|orr w0, wzr, #0x30}}
+; CHECK: mov w0, #48
 }
 
 define i64 @check_field() {
 ; CHECK-LABEL: check_field:
   %starti = ptrtoint %struct* @var to i64
 
   %endp = getelementptr %struct, %struct* @var, i64 0, i32 1
   %endi = ptrtoint i128* %endp to i64
 
   %diff = sub i64 %endi, %starti
   ret i64 %diff
-; CHECK: {{movz x0, #16|orr w0, wzr, #0x10}}
+; CHECK: mov w0, #16
 }

test/CodeGen/AArch64/isinf.ll

; CHECK-NEXT:  cset    w0, eq
   %cmpinf = fcmp oeq half %abs, 0xH7C00
   %ret = zext i1 %cmpinf to i32
   ret i32 %ret
 }
 
 ; Check if INFINITY for float is materialized
 define i32 @replace_isinf_call_f32(float %x) {
 ; CHECK-LABEL: replace_isinf_call_f32:
-; CHECK:       orr    [[INFSCALARREG:w[0-9]+]], wzr, #0x7f800000
+; CHECK:       mov    [[INFSCALARREG:w[0-9]+]], #2139095040
 ; CHECK-NEXT:  fabs   [[ABS:s[0-9]+]], s0
 ; CHECK-NEXT:  fmov   [[INFREG:s[0-9]+]], [[INFSCALARREG]]
 ; CHECK-NEXT:  fcmp   [[ABS]], [[INFREG]]
 ; CHECK-NEXT:  cset   w0, eq
   %abs = tail call float @llvm.fabs.f32(float %x)
   %cmpinf = fcmp oeq float %abs, 0x7FF0000000000000
   %ret = zext i1 %cmpinf to i32
   ret i32 %ret
 }
 
 ; Check if INFINITY for double is materialized
 define i32 @replace_isinf_call_f64(double %x) {
 ; CHECK-LABEL: replace_isinf_call_f64:
-; CHECK:       orr    [[INFSCALARREG:x[0-9]+]], xzr, #0x7ff0000000000000
+; CHECK:       mov    [[INFSCALARREG:x[0-9]+]], #9218868437227405312
 ; CHECK-NEXT:  fabs   [[ABS:d[0-9]+]], d0
 ; CHECK-NEXT:  fmov   [[INFREG:d[0-9]+]], [[INFSCALARREG]]
 ; CHECK-NEXT:  fcmp   [[ABS]], [[INFREG]]
 ; CHECK-NEXT:  cset   w0, eq
   %abs = tail call double @llvm.fabs.f64(double %x)
   %cmpinf = fcmp oeq double %abs, 0x7FF0000000000000
   %ret = zext i1 %cmpinf to i32
   ret i32 %ret

test/CodeGen/AArch64/known-never-nan.ll

; CHECK-NEXT:    ret
   ret float %val
 }
 
 ; If f1 is 0, fmul is NaN because 0.0 * -INF = NaN
 ; Therefore, this is not fmaxnm.
 define float @not_fmaxnm_maybe_nan(i32 %i1, i32 %i2) #0 {
 ; CHECK-LABEL: not_fmaxnm_maybe_nan:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0xff800000
+; CHECK-NEXT:    mov w8, #-8388608
 ; CHECK-NEXT:    ucvtf s0, w0
 ; CHECK-NEXT:    ucvtf s1, w1
 ; CHECK-NEXT:    fmov s2, #17.00000000
 ; CHECK-NEXT:    fmov s3, w8
 ; CHECK-NEXT:    fmul s0, s0, s3
 ; CHECK-NEXT:    fadd s1, s1, s2
 ; CHECK-NEXT:    fcmp s0, s1
 ; CHECK-NEXT:    fcsel s0, s0, s1, pl

test/CodeGen/AArch64/ldst-paired-aliasing.ll

 ; RUN: llc -mcpu cortex-a53 < %s | FileCheck %s
 target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
 target triple = "aarch64--linux-gnu"
 
 declare void @f(i8*, i8*)
 declare void @f2(i8*, i8*)
 declare void @_Z5setupv()
 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3
 
 define i32 @main() local_unnamed_addr #1 {
 ; Make sure the stores happen in the correct order (the exact instructions could change).
 ; CHECK-LABEL: main:
 
-; CHECK: orr w9, wzr, #0x1
+; CHECK: mov w9, #1
 ; CHECK: str x9, [sp, #80]
 ; CHECK: stp q0, q0, [sp, #48]
 ; CHECK: ldr w8, [sp, #48]
 
 for.body.lr.ph.i.i.i.i.i.i63:
   %b1 = alloca [10 x i32], align 16
   %x0 = bitcast [10 x i32]* %b1 to i8*
   %b2 = alloca [10 x i32], align 16

test/CodeGen/AArch64/machine-outliner-tail.ll

 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-linux-gnu < %s | FileCheck %s
 
 ; CHECK: OUTLINED_FUNCTION_0:
-; CHECK:      orr     w0, wzr, #0x1
-; CHECK-NEXT: orr     w1, wzr, #0x2
-; CHECK-NEXT: orr     w2, wzr, #0x3
-; CHECK-NEXT: orr     w3, wzr, #0x4
+; CHECK:      mov     w0, #1
+; CHECK-NEXT: mov     w1, #2
+; CHECK-NEXT: mov     w2, #3
+; CHECK-NEXT: mov     w3, #4
 ; CHECK-NEXT: b       z
 
 define void @a() {
 entry:
   tail call void @z(i32 1, i32 2, i32 3, i32 4)
   ret void
 }
 
 declare void @z(i32, i32, i32, i32)
 
 define dso_local void @b(i32* nocapture readnone %p) {
 entry:
   tail call void @z(i32 1, i32 2, i32 3, i32 4)
   ret void
 }

test/CodeGen/AArch64/machine-outliner-thunk.ll

entry:
   %call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4)
   %add = add nsw i32 %call, 88
   ret i32 %add
 }
 
 ; CHECK: [[OUTLINED_INDIRECT]]:
 ; CHECK:        // %bb.0:
 ; CHECK-NEXT:   mov     x8, x0
-; CHECK-NEXT:   orr     w0, wzr, #0x1
-; CHECK-NEXT:   orr     w1, wzr, #0x2
-; CHECK-NEXT:   orr     w2, wzr, #0x3
-; CHECK-NEXT:   orr     w3, wzr, #0x4
+; CHECK-NEXT:   mov     w0, #1
+; CHECK-NEXT:   mov     w1, #2
+; CHECK-NEXT:   mov     w2, #3
+; CHECK-NEXT:   mov     w3, #4
 ; CHECK-NEXT:   br      x8
 
 ; CHECK: [[OUTLINED_DIRECT]]:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr     w0, wzr, #0x1
-; CHECK-NEXT:    orr     w1, wzr, #0x2
-; CHECK-NEXT:    orr     w2, wzr, #0x3
-; CHECK-NEXT:    orr     w3, wzr, #0x4
+; CHECK-NEXT:    mov     w0, #1
+; CHECK-NEXT:    mov     w1, #2
+; CHECK-NEXT:    mov     w2, #3
+; CHECK-NEXT:    mov     w3, #4
 ; CHECK-NEXT:    b       thunk_called_fn

test/CodeGen/AArch64/machine-outliner.ll

define void @dog() #0 {
   store i32 5, i32* %5, align 4
   store i32 6, i32* %6, align 4
   ret void
 }
 
 ; ODR: [[OUTLINED]]:
 ; CHECK: .p2align 2
 ; CHECK-NEXT: [[OUTLINED]]:
-; CHECK: orr     w8, wzr, #0x1
+; CHECK: mov     w8, #1
 ; CHECK-NEXT: str     w8, [sp, #28]
-; CHECK-NEXT: orr     w8, wzr, #0x2
+; CHECK-NEXT: mov     w8, #2
 ; CHECK-NEXT: str     w8, [sp, #24]
-; CHECK-NEXT: orr     w8, wzr, #0x3
+; CHECK-NEXT: mov     w8, #3
 ; CHECK-NEXT: str     w8, [sp, #20]
-; CHECK-NEXT: orr     w8, wzr, #0x4
+; CHECK-NEXT: mov     w8, #4
 ; CHECK-NEXT: str     w8, [sp, #16]
 ; CHECK-NEXT: mov     w8, #5
 ; CHECK-NEXT: str     w8, [sp, #12]
-; CHECK-NEXT: orr     w8, wzr, #0x6
+; CHECK-NEXT: mov     w8, #6
 ; CHECK-NEXT: str     w8, [sp, #8]
 ; CHECK-NEXT: add     sp, sp, #32
 ; CHECK-NEXT: ret
 
 attributes #0 = { noredzone "target-cpu"="cyclone" "target-features"="+sse" }

test/CodeGen/AArch64/machine_cse_impdef_killflags.ll

 ; RUN: llc < %s -mtriple=aarch64-apple-ios -fast-isel -verify-machineinstrs | FileCheck %s
 
 ; Check that the kill flag is cleared between CSE'd instructions on their
 ; imp-def'd registers.
 ; The verifier would complain otherwise.
 define i64 @csed-impdef-killflag(i64 %a) {
 ; CHECK-LABEL: csed-impdef-killflag
-; CHECK-DAG:  orr    [[REG1:w[0-9]+]], wzr, #0x1
-; CHECK-DAG:  orr    [[REG2:x[0-9]+]], xzr, #0x2
-; CHECK-DAG:  orr    [[REG3:x[0-9]+]], xzr, #0x3
+; CHECK-DAG:  mov    [[REG1:w[0-9]+]], #1
+; CHECK-DAG:  mov    [[REG2:x[0-9]+]], #2
+; CHECK-DAG:  mov    [[REG3:x[0-9]+]], #3
 ; CHECK-DAG:  cmp    x0, #0
 ; CHECK:  csel   w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
 ; CHECK-DAG:  csel   [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
 ; CHECK:      ubfx   [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
 ; CHECK-NEXT: add    x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]
 ; CHECK-NEXT: ret
 
   %1 = icmp ne i64 %a, 0
   %2 = select i1 %1, i32 0, i32 1
   %3 = icmp ne i64 %a, 0
   %4 = select i1 %3, i64 2, i64 3
   %5 = zext i32 %2 to i64
   %6 = add i64 %4, %5
   ret i64 %6
 }

test/CodeGen/AArch64/madd-combiner.ll

 ; RUN: llc -mtriple=aarch64-apple-darwin            -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
 
 ; Test that we use the correct register class.
 define i32 @mul_add_imm(i32 %a, i32 %b) {
 ; CHECK-LABEL: mul_add_imm
 ; CHECK:       orr [[REG:w[0-9]+]], wzr, #0x4
 ; CHECK-NEXT:  madd  {{w[0-9]+}}, w0, w1, [[REG]]
   %1 = mul i32 %a, %b
   %2 = add i32 %1, 4
   ret i32 %2
 }
 
 define i32 @mul_sub_imm1(i32 %a, i32 %b) {
 ; CHECK-LABEL: mul_sub_imm1
-; CHECK:       orr [[REG:w[0-9]+]], wzr, #0x4
+; CHECK:       mov [[REG:w[0-9]+]], #4
 ; CHECK-NEXT:  msub  {{w[0-9]+}}, w0, w1, [[REG]]
   %1 = mul i32 %a, %b
   %2 = sub i32 4, %1
   ret i32 %2
 }
 
 ; bugpoint reduced test case. This only tests that we pass the MI verifier.
 define void @mul_add_imm2() {

test/CodeGen/AArch64/movw-consts.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
 
 define i64 @test0() {
 ; CHECK-LABEL: test0:
 ; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
 ; CHECK: mov x0, xzr
   ret i64 0
 }
 
 define i64 @test1() {
 ; CHECK-LABEL: test1:
-; CHECK: orr w0, wzr, #0x1
+; CHECK: mov w0, #1
   ret i64 1
 }
 
 define i64 @test2() {
 ; CHECK-LABEL: test2:
-; CHECK: orr w0, wzr, #0xffff
+; CHECK: mov w0, #65535
   ret i64 65535
 }
 
 define i64 @test3() {
 ; CHECK-LABEL: test3:
-; CHECK: orr w0, wzr, #0x10000
+; CHECK: mov w0, #65536
   ret i64 65536
 }
 
 define i64 @test4() {
 ; CHECK-LABEL: test4:
-; CHECK: orr w0, wzr, #0xffff0000
+; CHECK: mov w0, #-65536
   ret i64 4294901760
 }
 
 define i64 @test5() {
 ; CHECK-LABEL: test5:
-; CHECK: orr x0, xzr, #0x100000000
+; CHECK: mov x0, #4294967296
   ret i64 4294967296
 }
 
 define i64 @test6() {
 ; CHECK-LABEL: test6:
-; CHECK: orr x0, xzr, #0xffff00000000
+; CHECK: mov x0, #281470681743360
   ret i64 281470681743360
 }
 
 define i64 @test7() {
 ; CHECK-LABEL: test7:
-; CHECK: orr x0, xzr, #0x1000000000000
+; CHECK: mov x0, #281474976710656
   ret i64 281474976710656
 }
 
 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
 ; couldn't. Useful even for i64
 define i64 @test8() {
 ; CHECK-LABEL: test8:
 ; CHECK: mov w0, #-60876

 ; CHECK-LABEL: test11:
 ; CHECK: str wzr
   store i32 0, i32* @var32
   ret void
 }
 
 define void @test12() {
 ; CHECK-LABEL: test12:
-; CHECK: orr {{w[0-9]+}}, wzr, #0x1
+; CHECK: mov {{w[0-9]+}}, #1
   store i32 1, i32* @var32
   ret void
 }
 
 define void @test13() {
 ; CHECK-LABEL: test13:
-; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
+; CHECK: mov {{w[0-9]+}}, #65535
   store i32 65535, i32* @var32
   ret void
 }
 
 define void @test14() {
 ; CHECK-LABEL: test14:
-; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
+; CHECK: mov {{w[0-9]+}}, #65536
   store i32 65536, i32* @var32
   ret void
 }
 
 define void @test15() {
 ; CHECK-LABEL: test15:
-; CHECK: orr {{w[0-9]+}}, wzr, #0xffff0000
+; CHECK: mov {{w[0-9]+}}, #-65536
   store i32 4294901760, i32* @var32
   ret void
 }
 
 define void @test16() {
 ; CHECK-LABEL: test16:
 ; CHECK: mov {{w[0-9]+}}, #-1
   store i32 -1, i32* @var32
   ret void
 }
 
 define i64 @test17() {
 ; CHECK-LABEL: test17:
 
   ; Mustn't MOVN w0 here.
-; CHECK: orr x0, xzr, #0xfffffffffffffffd
+; CHECK: mov x0, #-3
   ret i64 -3
 }

test/CodeGen/AArch64/neon-compare-instructions.ll

 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
   %tmp3 = icmp uge <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2>
    %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmhsz2xi64:
-; CHECK: orr w[[TWO:[0-9]+]], wzr, #0x2
+; CHECK: mov w[[TWO:[0-9]+]], #2
 ; CHECK-NEXT: {{v[0-9]+}}.2d, x[[TWO]]
 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
   %tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2>
    %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 

 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
   %tmp3 = icmp ugt <4 x i32> %A, <i32 1, i32 1, i32 1, i32 1>
    %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmhiz2xi64:
-; CHECK: orr w[[ONE:[0-9]+]], wzr, #{{0x1|1}}
+; CHECK: mov w[[ONE:[0-9]+]], #1
 ; CHECK-NEXT: dup {{v[0-9]+}}.2d, x[[ONE]]
 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
   %tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1>
    %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
    %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
 ; CHECK-LABEL: cmloz2xi64:
 ; Using registers other than v0, v1 are possible, but would be odd.
 ; LO implemented as HI, so check reversed operands.
-; CHECK: orr w[[TWO:[0-9]+]], wzr, #{{0x2|2}}
+; CHECK: mov w[[TWO:[0-9]+]], #2
 ; CHECK-NEXT: dup v1.2d, x[[TWO]]
 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
   %tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2>
    %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
   ret <2 x i64> %tmp4
 }
 
 

test/CodeGen/AArch64/optimize-imm.ll

entry:
   ret i32 %or
 }
 
 ; Make sure we don't shrink or optimize an XOR's immediate operand if the
 ; immediate is -1. Instruction selection turns (and ((xor $mask, -1), $v0)) into
 ; a BIC.
 
 ; CHECK-LABEL: xor1:
-; CHECK: orr [[R0:w[0-9]+]], wzr, #0x38
+; CHECK: mov [[R0:w[0-9]+]], #56
 ; CHECK: bic {{w[0-9]+}}, [[R0]], w0, lsl #3
 
 define i32 @xor1(i32 %a) {
 entry:
   %shl = shl i32 %a, 3
   %xor = and i32 %shl, 56
   %and = xor i32 %xor, 56
   ret i32 %and

test/CodeGen/AArch64/redundant-copy-elim-empty-mbb.ll

 ; RUN: llc < %s | FileCheck %s
 ; Make sure we don't crash in AArch64RedundantCopyElimination when a
 ; MachineBasicBlock is empty.  PR29035.
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-linux-gnu"
 
 declare i8* @bar()
 
 ; CHECK-LABEL: foo:
 ; CHECK: tbz
-; CHECK: orr
+; CHECK: mov{{.*}}, #1
 ; CHECK: ret
 ; CHECK: bl bar
 ; CHECK: cbnz
 ; CHECK: ret
 define i1 @foo(i1 %start) {
 entry:
   br i1 %start, label %cleanup, label %if.end
 

test/CodeGen/AArch64/sadd_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
 
 declare  i4  @llvm.sadd.sat.i4   (i4,  i4)
 declare  i32 @llvm.sadd.sat.i32  (i32, i32)
 declare  i64 @llvm.sadd.sat.i64  (i64, i64)
 declare  <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
 
 define i32 @func(i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: func:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adds w8, w0, w1
-; CHECK-NEXT:    orr w9, wzr, #0x7fffffff
+; CHECK-NEXT:    mov w9, #2147483647
 ; CHECK-NEXT:    cmp w8, #0 // =0
 ; CHECK-NEXT:    cinv w8, w9, ge
 ; CHECK-NEXT:    adds w9, w0, w1
 ; CHECK-NEXT:    csel w0, w8, w9, vs
 ; CHECK-NEXT:    ret
   %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: func2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adds x8, x0, x1
-; CHECK-NEXT:    orr x9, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x9, #9223372036854775807
 ; CHECK-NEXT:    cmp x8, #0 // =0
 ; CHECK-NEXT:    cinv x8, x9, ge
 ; CHECK-NEXT:    adds x9, x0, x1
 ; CHECK-NEXT:    csel x0, x8, x9, vs
 ; CHECK-NEXT:    ret
   %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
 
 define i4 @func3(i4 %x, i4 %y) nounwind {
 ; CHECK-LABEL: func3:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    lsl w8, w0, #28
 ; CHECK-NEXT:    adds w10, w8, w1, lsl #28
-; CHECK-NEXT:    orr w9, wzr, #0x7fffffff
+; CHECK-NEXT:    mov w9, #2147483647
 ; CHECK-NEXT:    cmp w10, #0 // =0
 ; CHECK-NEXT:    cinv w9, w9, ge
 ; CHECK-NEXT:    adds w8, w8, w1, lsl #28
 ; CHECK-NEXT:    csel w8, w9, w8, vs
 ; CHECK-NEXT:    asr w0, w8, #28
 ; CHECK-NEXT:    ret
   %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
   ret i4 %tmp;

test/CodeGen/AArch64/sadd_sat_vec.ll

 
 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; CHECK-LABEL: v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    add v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    cmge v1.2d, v1.2d, #0
 ; CHECK-NEXT:    cmge v0.2d, v0.2d, #0
 ; CHECK-NEXT:    cmge v5.2d, v2.2d, #0
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    cmlt v3.2d, v2.2d, #0
 ; CHECK-NEXT:    cmeq v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    cmeq v0.2d, v0.2d, v5.2d
 ; CHECK-NEXT:    dup v4.2d, x8
 ; CHECK-NEXT:    mvn v5.16b, v3.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    bsl v4.16b, v3.16b, v5.16b
 ; CHECK-NEXT:    and v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    bsl v0.16b, v4.16b, v2.16b
 ; CHECK-NEXT:    ret
   %z = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
   ret <2 x i64> %z
 }
 
 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
 ; CHECK-LABEL: v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    add v4.2d, v0.2d, v2.2d
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    cmlt v6.2d, v4.2d, #0
 ; CHECK-NEXT:    dup v7.2d, x8
 ; CHECK-NEXT:    add v5.2d, v1.2d, v3.2d
 ; CHECK-NEXT:    mvn v16.16b, v6.16b
 ; CHECK-NEXT:    mov v17.16b, v7.16b
 ; CHECK-NEXT:    bsl v17.16b, v6.16b, v16.16b
 ; CHECK-NEXT:    cmlt v6.2d, v5.2d, #0
 ; CHECK-NEXT:    mvn v16.16b, v6.16b
; CHECK-NEXT:    ret
   %z = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
   ret <4 x i64> %z
 }
 
 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
 ; CHECK-LABEL: v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    add v16.2d, v0.2d, v4.2d
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    add v17.2d, v1.2d, v5.2d
 ; CHECK-NEXT:    cmlt v20.2d, v16.2d, #0
 ; CHECK-NEXT:    dup v21.2d, x8
 ; CHECK-NEXT:    add v18.2d, v2.2d, v6.2d
 ; CHECK-NEXT:    cmlt v22.2d, v17.2d, #0
 ; CHECK-NEXT:    mvn v24.16b, v20.16b
 ; CHECK-NEXT:    mov v25.16b, v21.16b
 ; CHECK-NEXT:    cmlt v23.2d, v18.2d, #0

 ; CHECK-NEXT:    cset w10, ge
 ; CHECK-NEXT:    csinc w10, w10, wzr, ne
 ; CHECK-NEXT:    cmp w10, w9
 ; CHECK-NEXT:    cset w9, eq
 ; CHECK-NEXT:    adds x11, x2, x6
 ; CHECK-NEXT:    adcs x12, x3, x7
 ; CHECK-NEXT:    cmp x12, #0 // =0
 ; CHECK-NEXT:    cset w13, ge
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    csinc w13, w13, wzr, ne
 ; CHECK-NEXT:    cinv x14, x8, ge
 ; CHECK-NEXT:    cmp w10, w13
 ; CHECK-NEXT:    cset w13, ne
 ; CHECK-NEXT:    asr x10, x12, #63
 ; CHECK-NEXT:    tst w9, w13
 ; CHECK-NEXT:    csel x3, x14, x12, ne
 ; CHECK-NEXT:    csel x2, x10, x11, ne

test/CodeGen/AArch64/sdivpow2.ll

 ; CHECK-NEXT:    ret
   %div = sdiv i64 %x, 64
   ret i64 %div
 }
 
 define i64 @test7(i64 %x) {
 ; CHECK-LABEL: test7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr x8, xzr, #0xffffffffffff
+; CHECK-NEXT:    mov x8, #281474976710655
 ; CHECK-NEXT:    add x8, x0, x8
 ; CHECK-NEXT:    cmp x0, #0 // =0
 ; CHECK-NEXT:    csel x8, x8, x0, lt
 ; CHECK-NEXT:    asr x0, x8, #48
 ; CHECK-NEXT:    ret
   %div = sdiv i64 %x, 281474976710656
   ret i64 %div
 }
 

test/CodeGen/AArch64/seh-finally.ll

 
 %struct.S = type { i32 }
 
 ; Test simple SEH (__try/__finally).
 define void @simple_seh() #0 personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) {
 entry:
 ; CHECK-LABEL: simple_seh
 ; CHECK: add     x29, sp, #16
-; CHECK: orr     x0, xzr, #0xfffffffffffffffe
+; CHECK: mov     x0, #-2
 ; CHECK: stur    x0, [x29, #-16]
 ; CHECK: .set .Lsimple_seh$frame_escape_0, -8
 ; CHECK: ldur    w0, [x29, #-8]
 ; CHECK: bl      foo
 
   %o = alloca %struct.S, align 4
   call void (...) @llvm.localescape(%struct.S* %o)
   %x = getelementptr inbounds %struct.S, %struct.S* %o, i32 0, i32 0

 ; Test SEH when stack realignment is needed in case highly aligned stack objects are present.
 define void @stack_realign() #0 personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) {
 entry:
 ; CHECK-LABEL: stack_realign
 ; CHECK: add     x29, sp, #16
 ; CHECK: sub     x9, sp, #64
 ; CHECK: and     sp, x9, #0xffffffffffffffe0
 ; CHECK: mov     x19, sp
-; CHECK: orr     x0, xzr, #0xfffffffffffffffe
+; CHECK: mov     x0, #-2
 ; CHECK: stur    x0, [x19, #16]
 ; CHECK: .set .Lstack_realign$frame_escape_0, 32
 ; CHECK: ldr     w0, [x19, #32]
 ; CHECK: bl      foo
 
   %o = alloca %struct.S, align 32
   call void (...) @llvm.localescape(%struct.S* %o)
   %x = getelementptr inbounds %struct.S, %struct.S* %o, i32 0, i32 0
; CHECK: bl      foo
   ret void
 }
 
 ; Test SEH when variable size objects are present on the stack. Note: Escaped vla's are current not supported by SEH.
 define void @vla_present(i32 %n) #0 personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) {
 entry:
 ; CHECK-LABEL: vla_present
 ; CHECK: add     x29, sp, #32
-; CHECK: orr     x1, xzr, #0xfffffffffffffffe
+; CHECK: mov     x1, #-2
 ; CHECK: stur    x1, [x29, #-32]
 ; CHECK: .set .Lvla_present$frame_escape_0, -4
 ; CHECK: stur    w0, [x29, #-4]
 ; CHECK: ldur    w8, [x29, #-4]
 ; CHECK: mov     x9, sp
 ; CHECK: stur    x9, [x29, #-16]
 ; CHECK: stur    x8, [x29, #-24]
 ; CHECK: ldur    w0, [x29, #-4]

 ; Test when both vla's and highly aligned objects are present on stack.
 define void @vla_and_realign(i32 %n) #0 personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) {
 entry:
 ; CHECK-LABEL: vla_and_realign
 ; CHECK: add     x29, sp, #16
 ; CHECK: sub     x9, sp, #64
 ; CHECK: and     sp, x9, #0xffffffffffffffe0
 ; CHECK: mov     x19, sp
-; CHECK: orr     x1, xzr, #0xfffffffffffffffe
+; CHECK: mov     x1, #-2
 ; CHECK: stur    x1, [x19]
 ; CHECK: .set .Lvla_and_realign$frame_escape_0, 32
 ; CHECK: stur    w0, [x29, #-4]
 ; CHECK: ldur    w8, [x29, #-4]
 ; CHECK: mov     x9, sp
 ; CHECK: str     x9, [x19, #24]
 ; CHECK: str     x8, [x19, #16]
 ; CHECK: ldr     w0, [x19, #32]

test/CodeGen/AArch64/selectcc-to-shiftand.ll

;
   ret i32 %retval
 }
 
 ; Compare if positive and select of constants where one constant is zero and the other is a single bit.
 
 define i32 @pos_sel_special_constant(i32 %a) {
 ; CHECK-LABEL: pos_sel_special_constant:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x200
+; CHECK-NEXT:    mov w8, #512
 ; CHECK-NEXT:    bic w0, w8, w0, lsr #22
 ; CHECK-NEXT:    ret
 ;
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
 }
 

test/CodeGen/AArch64/signed-truncation-check.ll

; CHECK-NEXT:    ret
   %tmp0 = add i24 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp ult i24 %tmp0, 256 ; 1U << 8
   ret i1 %tmp1
 }
 
 define i1 @add_ulecmp_bad_i16_i8(i16 %x) nounwind {
 ; CHECK-LABEL: add_ulecmp_bad_i16_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0x1
+; CHECK-NEXT:    mov w0, #1
 ; CHECK-NEXT:    ret
   %tmp0 = add i16 %x, 128 ; 1U << (8-1)
   %tmp1 = icmp ule i16 %tmp0, -1 ; when we +1 it, it will wrap to 0
   ret i1 %tmp1
 }

test/CodeGen/AArch64/ssub_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
 
 declare  i4  @llvm.ssub.sat.i4   (i4,  i4)
 declare  i32 @llvm.ssub.sat.i32  (i32, i32)
 declare  i64 @llvm.ssub.sat.i64  (i64, i64)
 declare  <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
 
 define i32 @func(i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: func:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    subs w8, w0, w1
-; CHECK-NEXT:    orr w9, wzr, #0x7fffffff
+; CHECK-NEXT:    mov w9, #2147483647
 ; CHECK-NEXT:    cmp w8, #0 // =0
 ; CHECK-NEXT:    cinv w8, w9, ge
 ; CHECK-NEXT:    subs w9, w0, w1
 ; CHECK-NEXT:    csel w0, w8, w9, vs
 ; CHECK-NEXT:    ret
   %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: func2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    subs x8, x0, x1
-; CHECK-NEXT:    orr x9, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x9, #9223372036854775807
 ; CHECK-NEXT:    cmp x8, #0 // =0
 ; CHECK-NEXT:    cinv x8, x9, ge
 ; CHECK-NEXT:    subs x9, x0, x1
 ; CHECK-NEXT:    csel x0, x8, x9, vs
 ; CHECK-NEXT:    ret
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
 
 define i4 @func3(i4 %x, i4 %y) nounwind {
 ; CHECK-LABEL: func3:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    lsl w8, w0, #28
 ; CHECK-NEXT:    subs w10, w8, w1, lsl #28
-; CHECK-NEXT:    orr w9, wzr, #0x7fffffff
+; CHECK-NEXT:    mov w9, #2147483647
 ; CHECK-NEXT:    cmp w10, #0 // =0
 ; CHECK-NEXT:    cinv w9, w9, ge
 ; CHECK-NEXT:    subs w8, w8, w1, lsl #28
 ; CHECK-NEXT:    csel w8, w9, w8, vs
 ; CHECK-NEXT:    asr w0, w8, #28
 ; CHECK-NEXT:    ret
   %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
   ret i4 %tmp;

test/CodeGen/AArch64/ssub_sat_vec.ll

 
 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; CHECK-LABEL: v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub v2.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    cmge v1.2d, v1.2d, #0
 ; CHECK-NEXT:    cmge v0.2d, v0.2d, #0
 ; CHECK-NEXT:    cmge v5.2d, v2.2d, #0
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    cmlt v3.2d, v2.2d, #0
 ; CHECK-NEXT:    cmeq v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    cmeq v0.2d, v0.2d, v5.2d
 ; CHECK-NEXT:    dup v4.2d, x8
 ; CHECK-NEXT:    mvn v5.16b, v3.16b
 ; CHECK-NEXT:    mvn v1.16b, v1.16b
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    bsl v4.16b, v3.16b, v5.16b
 ; CHECK-NEXT:    and v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    bsl v0.16b, v4.16b, v2.16b
 ; CHECK-NEXT:    ret
   %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
   ret <2 x i64> %z
 }
 
 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
 ; CHECK-LABEL: v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub v4.2d, v0.2d, v2.2d
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    cmlt v6.2d, v4.2d, #0
 ; CHECK-NEXT:    dup v7.2d, x8
 ; CHECK-NEXT:    sub v5.2d, v1.2d, v3.2d
 ; CHECK-NEXT:    mvn v16.16b, v6.16b
 ; CHECK-NEXT:    mov v17.16b, v7.16b
 ; CHECK-NEXT:    bsl v17.16b, v6.16b, v16.16b
 ; CHECK-NEXT:    cmlt v6.2d, v5.2d, #0
 ; CHECK-NEXT:    mvn v16.16b, v6.16b
; CHECK-NEXT:    ret
   %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
   ret <4 x i64> %z
 }
 
 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
 ; CHECK-LABEL: v8i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub v16.2d, v0.2d, v4.2d
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    sub v17.2d, v1.2d, v5.2d
 ; CHECK-NEXT:    cmlt v20.2d, v16.2d, #0
 ; CHECK-NEXT:    dup v21.2d, x8
 ; CHECK-NEXT:    sub v18.2d, v2.2d, v6.2d
 ; CHECK-NEXT:    cmlt v22.2d, v17.2d, #0
 ; CHECK-NEXT:    mvn v24.16b, v20.16b
 ; CHECK-NEXT:    mov v25.16b, v21.16b
 ; CHECK-NEXT:    cmlt v23.2d, v18.2d, #0

 ; CHECK-NEXT:    cset w10, ge
 ; CHECK-NEXT:    csinc w10, w10, wzr, ne
 ; CHECK-NEXT:    cmp w10, w9
 ; CHECK-NEXT:    cset w9, ne
 ; CHECK-NEXT:    subs x11, x2, x6
 ; CHECK-NEXT:    sbcs x12, x3, x7
 ; CHECK-NEXT:    cmp x12, #0 // =0
 ; CHECK-NEXT:    cset w13, ge
-; CHECK-NEXT:    orr x8, xzr, #0x7fffffffffffffff
+; CHECK-NEXT:    mov x8, #9223372036854775807
 ; CHECK-NEXT:    csinc w13, w13, wzr, ne
 ; CHECK-NEXT:    cinv x14, x8, ge
 ; CHECK-NEXT:    cmp w10, w13
 ; CHECK-NEXT:    cset w13, ne
 ; CHECK-NEXT:    asr x10, x12, #63
 ; CHECK-NEXT:    tst w9, w13
 ; CHECK-NEXT:    csel x3, x14, x12, ne
 ; CHECK-NEXT:    csel x2, x10, x11, ne

test/CodeGen/AArch64/swifterror.ll

 ; RUN: llc -fast-isel-sink-local-values -verify-machineinstrs -frame-pointer=all -enable-shrink-wrap=false < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck -allow-deprecated-dag-overlap --check-prefix=CHECK-APPLE %s
 ; RUN: llc -fast-isel-sink-local-values -verify-machineinstrs -frame-pointer=all -O0 -fast-isel < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck -allow-deprecated-dag-overlap --check-prefix=CHECK-O0 %s
 
 declare i8* @malloc(i64)
 declare void @free(i8*)
 %swift_error = type {i64, i8}
 
 ; This tests the basic usage of a swifterror parameter. "foo" is the function
 ; that takes a swifterror parameter and "caller" is the caller of "foo".
 define float @foo(%swift_error** swifterror %error_ptr_ref) {
 ; CHECK-APPLE-LABEL: foo:
-; CHECK-APPLE: orr w0, wzr, #0x10
+; CHECK-APPLE: mov w0, #16
 ; CHECK-APPLE: malloc
-; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
+; CHECK-APPLE: mov [[ID:w[0-9]+]], #1
 ; CHECK-APPLE: strb [[ID]], [x0, #8]
 ; CHECK-APPLE: mov x21, x0
 ; CHECK-APPLE-NOT: x21
 
 ; CHECK-O0-LABEL: foo:
-; CHECK-O0: orr w{{.*}}, wzr, #0x10
+; CHECK-O0: mov w{{.*}}, #16
 ; CHECK-O0: malloc
 ; CHECK-O0: mov x1, x0
 ; CHECK-O0-NOT: x1
-; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
+; CHECK-O0: mov [[ID:w[0-9]+]], #1
 ; CHECK-O0: strb [[ID]], [x0, #8]
 ; CHECK-O0: mov x21, x1
 entry:
   %call = call i8* @malloc(i64 16)
   %call.0 = bitcast i8* %call to %swift_error*
   store %swift_error* %call.0, %swift_error** %error_ptr_ref
   %tmp = getelementptr inbounds i8, i8* %call, i64 8
   store i8 1, i8* %tmp
handler:
   ret float 1.0
 }
 
 ; "foo_if" is a function that takes a swifterror parameter, it sets swifterror
 ; under a certain condition.
 define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
 ; CHECK-APPLE-LABEL: foo_if:
 ; CHECK-APPLE: cbz w0
-; CHECK-APPLE: orr w0, wzr, #0x10
+; CHECK-APPLE: mov w0, #16
 ; CHECK-APPLE: malloc
-; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
+; CHECK-APPLE: mov [[ID:w[0-9]+]], #1
 ; CHECK-APPLE: strb [[ID]], [x0, #8]
 ; CHECK-APPLE: mov x21, x0
 ; CHECK-APPLE-NOT: x21
 ; CHECK-APPLE: ret
 
 ; CHECK-O0-LABEL: foo_if:
 ; spill x21
 ; CHECK-O0: str x21, [sp, [[SLOT:#[0-9]+]]]
 ; CHECK-O0: cbz w0
-; CHECK-O0: orr w{{.*}}, wzr, #0x10
+; CHECK-O0: mov w{{.*}}, #16
 ; CHECK-O0: malloc
 ; CHECK-O0: mov [[ID:x[0-9]+]], x0
-; CHECK-O0: orr [[ID2:w[0-9]+]], wzr, #0x1
+; CHECK-O0: mov [[ID2:w[0-9]+]], #1
 ; CHECK-O0: strb [[ID2]], [x0, #8]
 ; CHECK-O0: mov x21, [[ID]]
 ; CHECK-O0: ret
 ; reload from stack
 ; CHECK-O0: ldr [[ID3:x[0-9]+]], [sp, [[SLOT]]]
 ; CHECK-O0: mov x21, [[ID3]]
 ; CHECK-O0: ret
 entry:

 }
 
 ; "foo_loop" is a function that takes a swifterror parameter, it sets swifterror
 ; under a certain condition inside a loop.
 define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) {
 ; CHECK-APPLE-LABEL: foo_loop:
 ; CHECK-APPLE: mov x0, x21
 ; CHECK-APPLE: cbz
-; CHECK-APPLE: orr w0, wzr, #0x10
+; CHECK-APPLE: mov w0, #16
 ; CHECK-APPLE: malloc
 ; CHECK-APPLE: strb w{{.*}}, [x0, #8]
 ; CHECK-APPLE: fcmp
 ; CHECK-APPLE: b.le
 ; CHECK-APPLE: mov x21, x0
 ; CHECK-APPLE: ret
 
 ; CHECK-O0-LABEL: foo_loop:
 ; spill x21
 ; CHECK-O0: str x21, [sp, [[SLOT:#[0-9]+]]]
 ; CHECK-O0: b [[BB1:[A-Za-z0-9_]*]]
 ; CHECK-O0: [[BB1]]:
 ; CHECK-O0: ldr     x0, [sp, [[SLOT]]]
 ; CHECK-O0: str     x0, [sp, [[SLOT2:#[0-9]+]]]
 ; CHECK-O0: cbz {{.*}}, [[BB2:[A-Za-z0-9_]*]]
-; CHECK-O0: orr w{{.*}}, wzr, #0x10
+; CHECK-O0: mov w{{.*}}, #16
 ; CHECK-O0: malloc
 ; CHECK-O0: mov [[ID:x[0-9]+]], x0
 ; CHECK-O0: strb w{{.*}}, [{{.*}}[[ID]], #8]
 ; spill x0
 ; CHECK-O0: str x0, [sp, [[SLOT2]]]
 ; CHECK-O0:[[BB2]]:
 ; CHECK-O0: ldr     x0, [sp, [[SLOT2]]]
 ; CHECK-O0: fcmp

 
 %struct.S = type { i32, i32, i32, i32, i32, i32 }
 
 ; "foo_sret" is a function that takes a swifterror parameter, it also has a sret
 ; parameter.
 define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) {
 ; CHECK-APPLE-LABEL: foo_sret:
 ; CHECK-APPLE: mov [[SRET:x[0-9]+]], x8
-; CHECK-APPLE: orr w0, wzr, #0x10
+; CHECK-APPLE: mov w0, #16
 ; CHECK-APPLE: malloc
-; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
+; CHECK-APPLE: mov [[ID:w[0-9]+]], #1
 ; CHECK-APPLE: strb [[ID]], [x0, #8]
 ; CHECK-APPLE: str w{{.*}}, [{{.*}}[[SRET]], #4]
 ; CHECK-APPLE: mov x21, x0
 ; CHECK-APPLE-NOT: x21
 
 ; CHECK-O0-LABEL: foo_sret:
-; CHECK-O0: orr w{{.*}}, wzr, #0x10
+; CHECK-O0: mov w{{.*}}, #16
 ; spill x8
 ; CHECK-O0-DAG: str x8
 ; spill x21
 ; CHECK-O0-DAG: str x21
 ; CHECK-O0: malloc
-; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
+; CHECK-O0: mov [[ID:w[0-9]+]], #1
 ; CHECK-O0: strb [[ID]], [x0, #8]
 ; reload from stack
 ; CHECK-O0: ldr [[SRET:x[0-9]+]]
 ; CHECK-O0: str w{{.*}}, [{{.*}}[[SRET]], #4]
 ; CHECK-O0: mov x21
 ; CHECK-O0-NOT: x21
 entry:
   %call = call i8* @malloc(i64 16)
handler:
   ret float 1.0
 }
 
 ; "foo_vararg" is a function that takes a swifterror parameter, it also has
 ; variable number of arguments.
 declare void @llvm.va_start(i8*) nounwind
 define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) {
 ; CHECK-APPLE-LABEL: foo_vararg:
-; CHECK-APPLE: orr w0, wzr, #0x10
+; CHECK-APPLE: mov w0, #16
 ; CHECK-APPLE: malloc
-; CHECK-APPLE-DAG: orr [[ID:w[0-9]+]], wzr, #0x1
+; CHECK-APPLE-DAG: mov [[ID:w[0-9]+]], #1
 ; CHECK-APPLE-DAG: add [[ARGS:x[0-9]+]], [[TMP:x[0-9]+]], #16
 ; CHECK-APPLE-DAG: strb [[ID]], [x0, #8]
 
 ; First vararg
 ; CHECK-APPLE-DAG: ldr {{w[0-9]+}}, [{{.*}}[[TMP]], #16]
 ; Second vararg
 ; CHECK-APPLE-DAG: ldr {{w[0-9]+}}, [{{.*}}[[TMP]], #24]
 ; CHECK-APPLE-DAG: add {{x[0-9]+}}, {{x[0-9]+}}, #16

 ; CHECK-APPLE:  mov      x24, x6
 ; CHECK-APPLE:  mov      x25, x5
 ; CHECK-APPLE:  mov      x26, x4
 ; CHECK-APPLE:  mov      x27, x3
 ; CHECK-APPLE:  mov      x28, x2
 ; CHECK-APPLE:  mov      x19, x1
 ; CHECK-APPLE:  mov      x22, x0
 ; Setup call.
-; CHECK-APPLE:  orr     w0, wzr, #0x1
-; CHECK-APPLE:  orr     w1, wzr, #0x2
-; CHECK-APPLE:  orr     w2, wzr, #0x3
-; CHECK-APPLE:  orr     w3, wzr, #0x4
+; CHECK-APPLE:  mov     w0, #1
+; CHECK-APPLE:  mov     w1, #2
+; CHECK-APPLE:  mov     w2, #3
+; CHECK-APPLE:  mov     w3, #4
 ; CHECK-APPLE:  mov     w4, #5
-; CHECK-APPLE:  orr     w5, wzr, #0x6
-; CHECK-APPLE:  orr     w6, wzr, #0x7
-; CHECK-APPLE:  orr     w7, wzr, #0x8
+; CHECK-APPLE:  mov     w5, #6
+; CHECK-APPLE:  mov     w6, #7
+; CHECK-APPLE:  mov     w7, #8
 ; CHECK-APPLE:  mov      x20, xzr
 ; CHECK-APPLE:  mov      x21, xzr
 ; CHECK-APPLE:  bl      _params_in_reg2
 ; Restore original arguments for next call.
 ; CHECK-APPLE:  mov      x0, x22
 ; CHECK-APPLE:  mov      x1, x19
 ; CHECK-APPLE:  mov      x2, x28
 ; CHECK-APPLE:  mov      x3, x27

 ; CHECK-APPLE:  mov      x24, x6
 ; CHECK-APPLE:  mov      x25, x5
 ; CHECK-APPLE:  mov      x26, x4
 ; CHECK-APPLE:  mov      x27, x3
 ; CHECK-APPLE:  mov      x28, x2
 ; CHECK-APPLE:  mov      x19, x1
 ; CHECK-APPLE:  mov      x22, x0
 ; Setup call arguments.
-; CHECK-APPLE:  orr     w0, wzr, #0x1
-; CHECK-APPLE:  orr     w1, wzr, #0x2
-; CHECK-APPLE:  orr     w2, wzr, #0x3
-; CHECK-APPLE:  orr     w3, wzr, #0x4
+; CHECK-APPLE:  mov     w0, #1
+; CHECK-APPLE:  mov     w1, #2
+; CHECK-APPLE:  mov     w2, #3
+; CHECK-APPLE:  mov     w3, #4
 ; CHECK-APPLE:  mov     w4, #5
-; CHECK-APPLE:  orr     w5, wzr, #0x6
-; CHECK-APPLE:  orr     w6, wzr, #0x7
-; CHECK-APPLE:  orr     w7, wzr, #0x8
+; CHECK-APPLE:  mov     w5, #6
+; CHECK-APPLE:  mov     w6, #7
+; CHECK-APPLE:  mov     w7, #8
 ; CHECK-APPLE:  mov      x20, xzr
 ; CHECK-APPLE:  mov      x21, xzr
 ; CHECK-APPLE:  bl      _params_in_reg2
 ; Store swifterror %error_ptr_ref.
 ; CHECK-APPLE:  str     x21, [sp, #8]
 ; Setup call arguments from original arguments.
 ; CHECK-APPLE:  mov      x0, x22
 ; CHECK-APPLE:  mov      x1, x19

 ; CHECK-APPLE:  mov      x25, x3
 ; CHECK-APPLE:  mov      x26, x4
 ; CHECK-APPLE:  mov      x27, x5
 ; CHECK-APPLE:  mov      x28, x6
 ; CHECK-APPLE:  mov      x23, x7
 ; Save swifterror %err.
 ; CHECK-APPLE:  str     x21, [sp, #24]
 ; Setup call.
-; CHECK-APPLE:  orr     w0, wzr, #0x1
-; CHECK-APPLE:  orr     w1, wzr, #0x2
-; CHECK-APPLE:  orr     w2, wzr, #0x3
-; CHECK-APPLE:  orr     w3, wzr, #0x4
+; CHECK-APPLE:  mov     w0, #1
+; CHECK-APPLE:  mov     w1, #2
+; CHECK-APPLE:  mov     w2, #3
+; CHECK-APPLE:  mov     w3, #4
 ; CHECK-APPLE:  mov     w4, #5
-; CHECK-APPLE:  orr     w5, wzr, #0x6
-; CHECK-APPLE:  orr     w6, wzr, #0x7
-; CHECK-APPLE:  orr     w7, wzr, #0x8
-; CHECK-APPLE:  mov      x20, xzr
+; CHECK-APPLE:  mov     w5, #6
+; CHECK-APPLE:  mov     w6, #7
+; CHECK-APPLE:  mov     w7, #8
+; CHECK-APPLE:  mov     x20, xzr
 ; ... setup call with swiferror %error_ptr_ref.
 ; CHECK-APPLE:  ldr     x21, [sp, #8]
 ; CHECK-APPLE:  bl      _params_in_reg2
 ; Restore return values for return from this function.
 ; CHECK-APPLE:  mov      x0, x19
 ; CHECK-APPLE:  mov      x1, x22
 ; CHECK-APPLE:  mov      x2, x24
 ; CHECK-APPLE:  mov      x3, x25

test/CodeGen/AArch64/tst-br.ll

 
 test3:
   %tbit3 = and i64 %val64, 4096
   %tst3 = icmp ne i64 %tbit3, 0
   br i1 %tst3, label %end2, label %end1
 ; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
 
 end2:
-; CHECK: {{movz x0, #1|orr w0, wzr, #0x1}}
+; CHECK: mov w0, #1
 ; CHECK-NEXT: ret
   ret i32 1
 
 end1:
 ; CHECK: [[LBL_end1]]:
-; CHECK-NEXT: {{mov x0, xzr|mov w0, wzr}}
+; CHECK-NEXT: mov w0, wzr
 ; CHECK-NEXT: ret
   ret i32 0
 }

test/CodeGen/AArch64/urem-seteq.ll

 ; CHECK-LABEL: test_urem_even:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w10, #9363
 ; CHECK-NEXT:    ubfx w9, w0, #1, #15
 ; CHECK-NEXT:    movk w10, #37449, lsl #16
 ; CHECK-NEXT:    umull x9, w9, w10
 ; CHECK-NEXT:    and w8, w0, #0xffff
 ; CHECK-NEXT:    lsr x9, x9, #34
-; CHECK-NEXT:    orr w10, wzr, #0xe
+; CHECK-NEXT:    mov w10, #14
 ; CHECK-NEXT:    msub w8, w9, w10, w8
 ; CHECK-NEXT:    cmp w8, #0 // =0
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret
   %urem = urem i16 %X, 14
   %cmp = icmp ne i16 %urem, 0
   %ret = zext i1 %cmp to i16
   ret i16 %ret
; CHECK-NEXT:    ret
   %ret = zext i1 %cmp to i32
   ret i32 %ret
 }
 
 ; We should not proceed with this fold if the divisor is 1 or -1
 define i32 @test_urem_one(i32 %X) nounwind readnone {
 ; CHECK-LABEL: test_urem_one:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w0, wzr, #0x1
+; CHECK-NEXT:    mov w0, #1
 ; CHECK-NEXT:    ret
   %urem = urem i32 %X, 1
   %cmp = icmp eq i32 %urem, 0
   %ret = zext i1 %cmp to i32
   ret i32 %ret
 }
 
 ; We can lower remainder of division by powers of two much better elsewhere;

test/CodeGen/AArch64/vec_cttz.ll

 ; CHECK-NEXT:    ret
     %b = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 true)
     ret <2 x i32> %b
 }
 
 define <1 x i64> @cttz_v1i64(<1 x i64> %a) nounwind {
 ; CHECK-LABEL: cttz_v1i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    fmov d1, x8
 ; CHECK-NEXT:    sub d1, d0, d1
 ; CHECK-NEXT:    bic v0.8b, v1.8b, v0.8b
 ; CHECK-NEXT:    cnt v0.8b, v0.8b
 ; CHECK-NEXT:    uaddlp v0.4h, v0.8b
 ; CHECK-NEXT:    uaddlp v0.2s, v0.4h
 ; CHECK-NEXT:    uaddlp v0.1d, v0.2s
 ; CHECK-NEXT:    ret

 ; CHECK-NEXT:    ret
     %b = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true)
     ret <4 x i32> %b
 }
 
 define <2 x i64> @cttz_v2i64(<2 x i64> %a) nounwind {
 ; CHECK-LABEL: cttz_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    dup v1.2d, x8
 ; CHECK-NEXT:    sub v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    bic v0.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    cnt v0.16b, v0.16b
 ; CHECK-NEXT:    uaddlp v0.8h, v0.16b
 ; CHECK-NEXT:    uaddlp v0.4s, v0.8h
 ; CHECK-NEXT:    uaddlp v0.2d, v0.4s
 ; CHECK-NEXT:    ret
     %b = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
     ret <2 x i64> %b
 }

test/CodeGen/AArch64/vecreduce-fmax-legalization.ll

 ; CHECK-NEXT:    ret
   %b = call nnan fp128 @llvm.experimental.vector.reduce.fmax.f128.v1f128(<1 x fp128> %a)
   ret fp128 %b
 }
 
 define float @test_v3f32(<3 x float> %a) nounwind {
 ; CHECK-LABEL: test_v3f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    orr w8, wzr, #0x7f800000
+; CHECK-NEXT:    mov w8, #2139095040
 ; CHECK-NEXT:    fmov s1, w8
 ; CHECK-NEXT:    mov v0.s[3], v1.s[0]
 ; CHECK-NEXT:    fmaxnmv s0, v0.4s
 ; CHECK-NEXT:    ret
   %b = call nnan float @llvm.experimental.vector.reduce.fmax.f32.v3f32(<3 x float> %a)
   ret float %b
 }
 

test/CodeGen/AArch64/wineh-try-catch-cbz.ll

 ; RUN: llc < %s | FileCheck %s
 
 ; Make sure the prologue is sane.  (Doesn't need to exactly match this,
 ; but the original issue only reproduced if the cbz was immediately
 ; after the frame setup.)
 
 ; CHECK:      sub     sp, sp, #32
 ; CHECK-NEXT: stp     x29, x30, [sp, #16]
 ; CHECK-NEXT: add     x29, sp, #16
-; CHECK-NEXT: orr     x1, xzr, #0xfffffffffffffffe
+; CHECK-NEXT: mov     x1, #-2
 ; CHECK-NEXT: stur    x1, [x29, #-16]
 ; CHECK-NEXT: cbz     w0, .LBB0_2
 
 target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-windows-msvc19.11.0"
 
 ; Function Attrs: uwtable
 define dso_local void @"?f@@YAXH@Z"(i32 %x) local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {

test/CodeGen/AArch64/wineh-try-catch.ll

 ; CHECK-LABEL: "?func@@YAHXZ":
 ; CHECK:       str     x28, [sp, #-48]!
 ; CHECK:       str     x21, [sp, #8]
 ; CHECK:       stp     x19, x20, [sp, #16]
 ; CHECK:       stp     x29, x30, [sp, #32]
 ; CHECK:       add     x29, sp, #32
 ; CHECK:       sub     sp, sp, #624
 ; CHECK:       mov     x19, sp
-; CHECK:       orr     x0, xzr, #0xfffffffffffffffe
+; CHECK:       mov     x0, #-2
 ; CHECK:       stur    x0, [x19]
 
 ; Now check that x is stored at fp - 20.  We check that this is the same
 ; location accessed from the funclet to retrieve x.
-; CHECK:       orr     w8, wzr, #0x1
+; CHECK:       mov     w8, #1
 ; CHECK:       stur    w8, [x29, [[X_OFFSET:#-[1-9][0-9]+]]
 
 ; Check the offset off the frame pointer at which B is located.
 ; Check the same offset is used to pass the address of B to init2 in the
 ; funclet.
 ; CHECK:       sub     x0, x29, [[B_OFFSET:#[1-9][0-9]+]]
 ; CHECK:       bl      "?init@@YAXPEAH@Z"