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Differential D59690

[SelectionDAG] Add more tests
ClosedPublic

Authored by piotr on Mar 22 2019, 4:10 AM.

Details

Reviewers
RKSimon
Commits
rGf896785cb72a: [SelectionDAG] Add 2 tests for selection across basic blocks
rL357149: [SelectionDAG] Add 2 tests for selection across basic blocks
Summary

Add tests for selection across basic block boundary.

This commit was extracted from https://reviews.llvm.org/D59535.

Diff Detail

Event Timeline

piotr created this revision.Mar 22 2019, 4:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 22 2019, 4:10 AM
Herald added subscribers: llvm-commits, nhaehnle, jvesely. · View Herald Transcript
Harbormaster completed remote builds in B29489: Diff 191855.Mar 22 2019, 4:11 AM
piotr added a reviewer: RKSimon.Mar 22 2019, 4:13 AM
piotr mentioned this in D59535: [SelectionDAG] Compute known bits of CopyFromReg.Mar 22 2019, 4:15 AM
RKSimon accepted this revision.Mar 22 2019, 4:50 AM

LGTM but please improve the patch title and message to be be something more meaningful before committing

This revision is now accepted and ready to land.Mar 22 2019, 4:50 AM
Closed by commit rL357149: [SelectionDAG] Add 2 tests for selection across basic blocks (authored by piotr). · Explain WhyMar 28 2019, 12:05 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
test/
CodeGen/
AMDGPU/
39 lines

Diff 191855

test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Linesmain_body:
%x = bitcast i32 %load0 to float %x = bitcast i32 %load0 to float
%y = bitcast i32 %load1 to float %y = bitcast i32 %load1 to float
%z = bitcast i32 %load2 to float %z = bitcast i32 %load2 to float
%w = bitcast i32 %load3 to float %w = bitcast i32 %load3 to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true)
ret void ret void
} }
;CHECK-LABEL: {{^}}s_buffer_load_index_across_bb:
;CHECK-NOT: s_waitcnt;
;CHECK: v_or_b32
;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_ps void @s_buffer_load_index_across_bb(<4 x i32> inreg %desc, i32 %index) {
main_body:
%tmp = shl i32 %index, 4
br label %bb1
bb1: ; preds = %main_body
%tmp1 = or i32 %tmp, 8
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp1, i32 0)
%bitcast = bitcast i32 %load to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true)
ret void
}
;CHECK-LABEL: {{^}}s_buffer_load_index_across_bb_merged:
;CHECK-NOT: s_waitcnt;
;CHECK: v_or_b32
;CHECK: v_or_b32
;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
define amdgpu_ps void @s_buffer_load_index_across_bb_merged(<4 x i32> inreg %desc, i32 %index) {
main_body:
%tmp = shl i32 %index, 4
br label %bb1
bb1: ; preds = %main_body
%tmp1 = or i32 %tmp, 8
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp1, i32 0)
%tmp2 = or i32 %tmp1, 4
%load2 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp2, i32 0)
%bitcast = bitcast i32 %load to float
%bitcast2 = bitcast i32 %load2 to float
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float %bitcast2, float undef, float undef, i1 true, i1 true)
ret void
}
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)
declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32) declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32)
declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32) declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32)
declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32) declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32)