[MIPS GlobalISel] Select copy for arguments from FPRBRegBank

[Petar.Avramovic]

Summary

Move selectCopy into MipsInstructionSelector class.
Select copy for arguments from FPRBRegBank for MIPS32.

[atanasyan]

LGTM with a nit

lib/Target/Mips/MipsInstructionSelector.cpp

86

Is this line necessary?

lib/Target/Mips/MipsInstructionSelector.cpp

public:
 
   bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
   static const char *getName() { return DEBUG_TYPE; }
 
 private:
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
   bool materialize32BitImm(unsigned DestReg, APInt Imm,
                            MachineIRBuilder &B) const;
+  bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
 
   const MipsTargetMachine &TM;
   const MipsSubtarget &STI;
   const MipsInstrInfo &TII;
   const MipsRegisterInfo &TRI;
   const MipsRegisterBankInfo &RBI;
 
 #define GET_GLOBALISEL_PREDICATES_DECL

 #include "MipsGenGlobalISel.inc"
 #undef GET_GLOBALISEL_PREDICATES_INIT
 #define GET_GLOBALISEL_TEMPORARIES_INIT
 #include "MipsGenGlobalISel.inc"
 #undef GET_GLOBALISEL_TEMPORARIES_INIT
 {
 }
 
-static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
-                       MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
-                       const RegisterBankInfo &RBI) {
+bool MipsInstructionSelector::selectCopy(MachineInstr &I,
+                                         MachineRegisterInfo &MRI) const {
   unsigned DstReg = I.getOperand(0).getReg();
   if (TargetRegisterInfo::isPhysicalRegister(DstReg))
     return true;
 
-  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
+  const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
+  const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
 
+  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
+  if (RegBank->getID() == Mips::FPRBRegBankID) {
+    if (DstSize == 32)
+      RC = &Mips::FGR32RegClass;
+    else if (DstSize == 64)
+      RC = STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
+    else
+      llvm_unreachable("Unsupported destination size");
+  }
   if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
                       << " operand\n");
     return false;
   }
   return true;
 }
 
bool MipsInstructionSelector::select(MachineInstr &I,
                                      CodeGenCoverage &CoverageInfo) const {
 
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
-      return selectCopy(I, TII, MRI, TRI, RBI);
+      return selectCopy(I, MRI);
 
     return true;
   }
 
   if (I.getOpcode() == Mips::G_MUL) {
     MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
                             .add(I.getOperand(0))
                             .add(I.getOperand(1))

test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @float_in_fpr() {entry: ret void}
+  define void @double_in_fpr() {entry: ret void}
+  define void @float_in_gpr() {entry: ret void}
+  define void @double_in_gpr() {entry: ret void}
+  define void @call_float_in_fpr() {entry: ret void}
+  define void @call_double_in_fpr() {entry: ret void}
+  define void @call_float_in_gpr() {entry: ret void}
+  define void @call_double_in_gpr() {entry: ret void}
+
+...
+---
+name:            float_in_fpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $f12, $f14
+
+    ; FP32-LABEL: name: float_in_fpr
+    ; FP32: liveins: $f12, $f14
+    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f14
+    ; FP32: $f0 = COPY [[COPY]]
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: float_in_fpr
+    ; FP64: liveins: $f12, $f14
+    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f14
+    ; FP64: $f0 = COPY [[COPY]]
+    ; FP64: RetRA implicit $f0
+    %1:fprb(s32) = COPY $f14
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            double_in_fpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $d6, $d7
+
+    ; FP32-LABEL: name: double_in_fpr
+    ; FP32: liveins: $d6, $d7
+    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d7
+    ; FP32: $d0 = COPY [[COPY]]
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: double_in_fpr
+    ; FP64: liveins: $d6, $d7
+    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d7
+    ; FP64: $d0 = COPY [[COPY]]
+    ; FP64: RetRA implicit $d0
+    %1:fprb(s64) = COPY $d7
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            float_in_gpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; FP32-LABEL: name: float_in_gpr
+    ; FP32: liveins: $a0, $a1
+    ; FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
+    ; FP32: $f0 = COPY [[MTC1_]]
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: float_in_gpr
+    ; FP64: liveins: $a0, $a1
+    ; FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
+    ; FP64: $f0 = COPY [[MTC1_]]
+    ; FP64: RetRA implicit $f0
+    %1:fgr32(s32) = MTC1 $a1
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            double_in_gpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a2, $a3
+
+    ; FP32-LABEL: name: double_in_gpr
+    ; FP32: liveins: $a0, $a2, $a3
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 $a2, $a3
+    ; FP32: $d0 = COPY [[BuildPairF64_]]
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: double_in_gpr
+    ; FP64: liveins: $a0, $a2, $a3
+    ; FP64: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 $a2, $a3
+    ; FP64: $d0 = COPY [[BuildPairF64_]]
+    ; FP64: RetRA implicit $d0
+    %1:afgr64(s64) = BuildPairF64 $a2, $a3
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            call_float_in_fpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $f12, $f14
+
+    ; FP32-LABEL: name: call_float_in_fpr
+    ; FP32: liveins: $f12, $f14
+    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f12 = COPY [[COPY]]
+    ; FP32: $f14 = COPY [[COPY1]]
+    ; FP32: JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+    ; FP32: [[COPY2:%[0-9]+]]:fgr32 = COPY $f0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f0 = COPY [[COPY2]]
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: call_float_in_fpr
+    ; FP64: liveins: $f12, $f14
+    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f12 = COPY [[COPY]]
+    ; FP64: $f14 = COPY [[COPY1]]
+    ; FP64: JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+    ; FP64: [[COPY2:%[0-9]+]]:fgr32 = COPY $f0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f0 = COPY [[COPY2]]
+    ; FP64: RetRA implicit $f0
+    %0:fprb(s32) = COPY $f12
+    %1:fprb(s32) = COPY $f14
+    ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    $f12 = COPY %0(s32)
+    $f14 = COPY %1(s32)
+    JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+    %2:fprb(s32) = COPY $f0
+    ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    $f0 = COPY %2(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            call_double_in_fpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $d6, $d7
+
+    ; FP32-LABEL: name: call_double_in_fpr
+    ; FP32: liveins: $d6, $d7
+    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d6 = COPY [[COPY]]
+    ; FP32: $d7 = COPY [[COPY1]]
+    ; FP32: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+    ; FP32: [[COPY2:%[0-9]+]]:afgr64 = COPY $d0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d0 = COPY [[COPY2]]
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: call_double_in_fpr
+    ; FP64: liveins: $d6, $d7
+    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d6 = COPY [[COPY]]
+    ; FP64: $d7 = COPY [[COPY1]]
+    ; FP64: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+    ; FP64: [[COPY2:%[0-9]+]]:fgr64 = COPY $d0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d0 = COPY [[COPY2]]
+    ; FP64: RetRA implicit $d0
+    %0:fprb(s64) = COPY $d6
+    %1:fprb(s64) = COPY $d7
+    ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    $d6 = COPY %0(s64)
+    $d7 = COPY %1(s64)
+    JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+    %2:fprb(s64) = COPY $d0
+    ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    $d0 = COPY %2(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            call_float_in_gpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; FP32-LABEL: name: call_float_in_gpr
+    ; FP32: liveins: $a0, $a1
+    ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $a0 = COPY [[COPY]]
+    ; FP32: $a1 = MFC1 [[MTC1_]]
+    ; FP32: JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f0 = COPY [[COPY1]]
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: call_float_in_gpr
+    ; FP64: liveins: $a0, $a1
+    ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $a0 = COPY [[COPY]]
+    ; FP64: $a1 = MFC1 [[MTC1_]]
+    ; FP64: JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f0 = COPY [[COPY1]]
+    ; FP64: RetRA implicit $f0
+    %0:gprb(s32) = COPY $a0
+    %1:fgr32(s32) = MTC1 $a1
+    ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    $a0 = COPY %0(s32)
+    $a1 = MFC1 %1(s32)
+    JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+    %2:fprb(s32) = COPY $f0
+    ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    $f0 = COPY %2(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            call_double_in_gpr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a2, $a3
+
+    ; FP32-LABEL: name: call_double_in_gpr
+    ; FP32: liveins: $a0, $a2, $a3
+    ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 $a2, $a3
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $a0 = COPY [[COPY]]
+    ; FP32: $a3 = ExtractElementF64 [[BuildPairF64_]], 1
+    ; FP32: $a2 = ExtractElementF64 [[BuildPairF64_]], 0
+    ; FP32: JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d0 = COPY [[COPY1]]
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: call_double_in_gpr
+    ; FP64: liveins: $a0, $a2, $a3
+    ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP64: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 $a2, $a3
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $a0 = COPY [[COPY]]
+    ; FP64: $a3 = ExtractElementF64 [[BuildPairF64_]], 1
+    ; FP64: $a2 = ExtractElementF64 [[BuildPairF64_]], 0
+    ; FP64: JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d0 = COPY [[COPY1]]
+    ; FP64: RetRA implicit $d0
+    %0:gprb(s32) = COPY $a0
+    %1:afgr64(s64) = BuildPairF64 $a2, $a3
+    ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    $a0 = COPY %0(s32)
+    $a3 = ExtractElementF64 %1(s64), 1
+    $a2 = ExtractElementF64 %1(s64), 0
+    JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+    %2:fprb(s64) = COPY $d0
+    ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    $d0 = COPY %2(s64)
+    RetRA implicit $d0
+
+...
+

test/CodeGen/Mips/GlobalISel/llvm-ir/float_args.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+
+define float @float_in_fpr(float %a, float %b) {
+; MIPS32-LABEL: float_in_fpr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    mov.s $f0, $f14
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret float %b
+}
+
+define double @double_in_fpr(double %a, double %b) {
+; MIPS32-LABEL: double_in_fpr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    mov.d $f0, $f14
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret double %b
+}
+
+define float @float_in_gpr(i32 %a, float %b) {
+; MIPS32-LABEL: float_in_gpr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    mtc1 $5, $f0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret float %b
+}
+
+define double @double_in_gpr(i32 %a, double %b) {
+; FP32-LABEL: double_in_gpr:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    mtc1 $6, $f0
+; FP32-NEXT:    mtc1 $7, $f1
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: double_in_gpr:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    mtc1 $6, $f0
+; FP64-NEXT:    mthc1 $7, $f0
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  ret double %b
+}
+
+define float @call_float_in_fpr(float %a, float %b) {
+; MIPS32-LABEL: call_float_in_fpr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal float_in_fpr
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %call = call float @float_in_fpr(float %a, float %b)
+  ret float %call
+}
+
+define double @call_double_in_fpr(double %a, double %b) {
+; MIPS32-LABEL: call_double_in_fpr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal double_in_fpr
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %call = call double @double_in_fpr(double %a, double %b)
+  ret double %call
+}
+
+define float @call_float_in_gpr(i32 %a, float %b) {
+; MIPS32-LABEL: call_float_in_gpr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    mtc1 $5, $f0
+; MIPS32-NEXT:    mfc1 $5, $f0
+; MIPS32-NEXT:    jal float_in_gpr
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %call = call float @float_in_gpr(i32 %a, float %b)
+  ret float %call
+}
+
+
+define double @call_double_in_gpr(i32 %a, double %b) {
+; FP32-LABEL: call_double_in_gpr:
+; FP32:       # %bb.0: # %entry
+; FP32-NEXT:    addiu $sp, $sp, -24
+; FP32-NEXT:    .cfi_def_cfa_offset 24
+; FP32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; FP32-NEXT:    .cfi_offset 31, -4
+; FP32-NEXT:    mtc1 $6, $f0
+; FP32-NEXT:    mtc1 $7, $f1
+; FP32-NEXT:    mfc1 $7, $f1
+; FP32-NEXT:    mfc1 $6, $f0
+; FP32-NEXT:    jal double_in_gpr
+; FP32-NEXT:    nop
+; FP32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; FP32-NEXT:    addiu $sp, $sp, 24
+; FP32-NEXT:    jr $ra
+; FP32-NEXT:    nop
+;
+; FP64-LABEL: call_double_in_gpr:
+; FP64:       # %bb.0: # %entry
+; FP64-NEXT:    addiu $sp, $sp, -24
+; FP64-NEXT:    .cfi_def_cfa_offset 24
+; FP64-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; FP64-NEXT:    .cfi_offset 31, -4
+; FP64-NEXT:    mtc1 $6, $f0
+; FP64-NEXT:    mthc1 $7, $f0
+; FP64-NEXT:    mfhc1 $7, $f0
+; FP64-NEXT:    mfc1 $6, $f0
+; FP64-NEXT:    jal double_in_gpr
+; FP64-NEXT:    nop
+; FP64-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; FP64-NEXT:    addiu $sp, $sp, 24
+; FP64-NEXT:    jr $ra
+; FP64-NEXT:    nop
+entry:
+  %call = call double @double_in_gpr(i32 %a, double %b)
+  ret double %call
+}