This is an archive of the discontinued LLVM Phabricator instance.

Differential D59642

[MIPS GlobalISel] Lower float and double arguments in registers
ClosedPublic

Authored by Petar.Avramovic on Mar 21 2019, 7:45 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG5a457e08f6f9: [MIPS GlobalISel] Lower float and double arguments in registers
rL356882: [MIPS GlobalISel] Lower float and double arguments in registers
Summary

Lower float and double arguments in registers for MIPS32.
When float/double argument is passed through gpr registers
select appropriate move instruction.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Mar 21 2019, 7:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 21 2019, 7:45 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 3 others. · View Herald Transcript
Petar.Avramovic added a child revision: D59643: [MIPS GlobalISel] Add floating point register bank.Mar 21 2019, 7:48 AM
atanasyan accepted this revision.Mar 24 2019, 2:34 PM

LGTM

This revision is now accepted and ready to land.Mar 24 2019, 2:34 PM
Closed by commit rL356882: [MIPS GlobalISel] Lower float and double arguments in registers (authored by Petar.Avramovic). · Explain WhyMar 25 2019, 4:22 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
10 lines
124 lines
test/
CodeGen/
Mips/
GlobalISel/
irtranslator/
211 lines

Diff 192073

llvm/trunk/lib/Target/Mips/MipsCallLowering.h

Show All 29 Lines public:
virtual ~MipsHandler() = default; virtual ~MipsHandler() = default;
bool handle(ArrayRef<CCValAssign> ArgLocs, bool handle(ArrayRef<CCValAssign> ArgLocs,
ArrayRef<CallLowering::ArgInfo> Args); ArrayRef<CallLowering::ArgInfo> Args);
protected: protected:
bool assignVRegs(ArrayRef<unsigned> VRegs, ArrayRef<CCValAssign> ArgLocs, bool assignVRegs(ArrayRef<unsigned> VRegs, ArrayRef<CCValAssign> ArgLocs,
unsigned Index); unsigned ArgLocsStartIndex, const EVT &VT);
void setLeastSignificantFirst(SmallVectorImpl<unsigned> &VRegs); void setLeastSignificantFirst(SmallVectorImpl<unsigned> &VRegs);
MachineIRBuilder &MIRBuilder; MachineIRBuilder &MIRBuilder;
MachineRegisterInfo &MRI; MachineRegisterInfo &MRI;
private: private:
bool assign(unsigned VReg, const CCValAssign &VA); bool assign(unsigned VReg, const CCValAssign &VA, const EVT &VT);
virtual unsigned getStackAddress(const CCValAssign &VA, virtual unsigned getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) = 0; MachineMemOperand *&MMO) = 0;
virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) = 0; virtual void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
const EVT &VT) = 0;
virtual void assignValueToAddress(unsigned ValVReg, virtual void assignValueToAddress(unsigned ValVReg,
const CCValAssign &VA) = 0; const CCValAssign &VA) = 0;
virtual bool handleSplit(SmallVectorImpl<unsigned> &VRegs, virtual bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
ArrayRef<CCValAssign> ArgLocs, ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex, unsigned ArgsReg) = 0; unsigned ArgLocsStartIndex, unsigned ArgsReg,
const EVT &VT) = 0;
}; };
MipsCallLowering(const MipsTargetLowering &TLI); MipsCallLowering(const MipsTargetLowering &TLI);
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
ArrayRef<unsigned> VRegs) const override; ArrayRef<unsigned> VRegs) const override;
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
Show All 25 Lines

llvm/trunk/lib/Target/Mips/MipsCallLowering.cpp

Show All 17 Lines
#include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
using namespace llvm; using namespace llvm;
MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI) MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
: CallLowering(&TLI) {} : CallLowering(&TLI) {}
bool MipsCallLowering::MipsHandler::assign(unsigned VReg, bool MipsCallLowering::MipsHandler::assign(unsigned VReg, const CCValAssign &VA,
const CCValAssign &VA) { const EVT &VT) {
if (VA.isRegLoc()) { if (VA.isRegLoc()) {
assignValueToReg(VReg, VA); assignValueToReg(VReg, VA, VT);
} else if (VA.isMemLoc()) { } else if (VA.isMemLoc()) {
assignValueToAddress(VReg, VA); assignValueToAddress(VReg, VA);
} else { } else {
return false; return false;
} }
return true; return true;
} }
bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<unsigned> VRegs, bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<unsigned> VRegs,
ArrayRef<CCValAssign> ArgLocs, ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex) { unsigned ArgLocsStartIndex,
const EVT &VT) {
for (unsigned i = 0; i < VRegs.size(); ++i) for (unsigned i = 0; i < VRegs.size(); ++i)
if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i])) if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
return false; return false;
return true; return true;
} }
void MipsCallLowering::MipsHandler::setLeastSignificantFirst( void MipsCallLowering::MipsHandler::setLeastSignificantFirst(
SmallVectorImpl<unsigned> &VRegs) { SmallVectorImpl<unsigned> &VRegs) {
if (!MIRBuilder.getMF().getDataLayout().isLittleEndian()) if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
std::reverse(VRegs.begin(), VRegs.end()); std::reverse(VRegs.begin(), VRegs.end());
Show All 15 Lines SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
F.getCallingConv(), VT); F.getCallingConv(), VT);
if (SplitLength > 1) { if (SplitLength > 1) {
VRegs.clear(); VRegs.clear();
MVT RegisterVT = TLI.getRegisterTypeForCallingConv( MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
F.getContext(), F.getCallingConv(), VT); F.getContext(), F.getCallingConv(), VT);
for (unsigned i = 0; i < SplitLength; ++i) for (unsigned i = 0; i < SplitLength; ++i)
VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg)) if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg, VT))
return false; return false;
} else { } else {
if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex])) if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex], VT))
return false; return false;
} }
} }
return true; return true;
} }
namespace { namespace {
class IncomingValueHandler : public MipsCallLowering::MipsHandler { class IncomingValueHandler : public MipsCallLowering::MipsHandler {
public: public:
IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
: MipsHandler(MIRBuilder, MRI) {} : MipsHandler(MIRBuilder, MRI) {}
private: private:
void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override; void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
const EVT &VT) override;
unsigned getStackAddress(const CCValAssign &VA, unsigned getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) override; MachineMemOperand *&MMO) override;
void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override; void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
bool handleSplit(SmallVectorImpl<unsigned> &VRegs, bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex, ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
unsigned ArgsReg) override; unsigned ArgsReg, const EVT &VT) override;
virtual void markPhysRegUsed(unsigned PhysReg) { virtual void markPhysRegUsed(unsigned PhysReg) {
MIRBuilder.getMBB().addLiveIn(PhysReg); MIRBuilder.getMBB().addLiveIn(PhysReg);
} }
void buildLoad(unsigned Val, const CCValAssign &VA) { void buildLoad(unsigned Val, const CCValAssign &VA) {
MachineMemOperand *MMO; MachineMemOperand *MMO;
unsigned Addr = getStackAddress(VA, MMO); unsigned Addr = getStackAddress(VA, MMO);
Show All 13 Linesprivate:
} }
MachineInstrBuilder &MIB; MachineInstrBuilder &MIB;
}; };
} // end anonymous namespace } // end anonymous namespace
void IncomingValueHandler::assignValueToReg(unsigned ValVReg, void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
const CCValAssign &VA) { const CCValAssign &VA,
const EVT &VT) {
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
unsigned PhysReg = VA.getLocReg(); unsigned PhysReg = VA.getLocReg();
if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
MIRBuilder
.buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64
: Mips::BuildPairF64)
.addDef(ValVReg)
.addUse(PhysReg + (STI.isLittle() ? 0 : 1))
.addUse(PhysReg + (STI.isLittle() ? 1 : 0))
.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
*STI.getRegBankInfo());
markPhysRegUsed(PhysReg);
markPhysRegUsed(PhysReg + 1);
} else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
MIRBuilder.buildInstr(Mips::MTC1)
.addDef(ValVReg)
.addUse(PhysReg)
.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
*STI.getRegBankInfo());
markPhysRegUsed(PhysReg);
} else {
switch (VA.getLocInfo()) { switch (VA.getLocInfo()) {
case CCValAssign::LocInfo::SExt: case CCValAssign::LocInfo::SExt:
case CCValAssign::LocInfo::ZExt: case CCValAssign::LocInfo::ZExt:
case CCValAssign::LocInfo::AExt: { case CCValAssign::LocInfo::AExt: {
auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
MIRBuilder.buildTrunc(ValVReg, Copy); MIRBuilder.buildTrunc(ValVReg, Copy);
break; break;
} }
default: default:
MIRBuilder.buildCopy(ValVReg, PhysReg); MIRBuilder.buildCopy(ValVReg, PhysReg);
break; break;
} }
markPhysRegUsed(PhysReg); markPhysRegUsed(PhysReg);
} }
}
unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA, unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) { MachineMemOperand *&MMO) {
MachineFunction &MF = MIRBuilder.getMF(); MachineFunction &MF = MIRBuilder.getMF();
unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8; unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
unsigned Offset = VA.getLocMemOffset(); unsigned Offset = VA.getLocMemOffset();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
Show All 21 Lines if (VA.getLocInfo() == CCValAssign::SExt ||
MIRBuilder.buildTrunc(ValVReg, LoadReg); MIRBuilder.buildTrunc(ValVReg, LoadReg);
} else } else
buildLoad(ValVReg, VA); buildLoad(ValVReg, VA);
} }
bool IncomingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs, bool IncomingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
ArrayRef<CCValAssign> ArgLocs, ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex, unsigned ArgLocsStartIndex,
unsigned ArgsReg) { unsigned ArgsReg, const EVT &VT) {
if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex)) if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
return false; return false;
setLeastSignificantFirst(VRegs); setLeastSignificantFirst(VRegs);
MIRBuilder.buildMerge(ArgsReg, VRegs); MIRBuilder.buildMerge(ArgsReg, VRegs);
return true; return true;
} }
namespace { namespace {
class OutgoingValueHandler : public MipsCallLowering::MipsHandler { class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
public: public:
OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
MachineInstrBuilder &MIB) MachineInstrBuilder &MIB)
: MipsHandler(MIRBuilder, MRI), MIB(MIB) {} : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
private: private:
void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override; void assignValueToReg(unsigned ValVReg, const CCValAssign &VA,
const EVT &VT) override;
unsigned getStackAddress(const CCValAssign &VA, unsigned getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) override; MachineMemOperand *&MMO) override;
void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override; void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
bool handleSplit(SmallVectorImpl<unsigned> &VRegs, bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex, ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
unsigned ArgsReg) override; unsigned ArgsReg, const EVT &VT) override;
unsigned extendRegister(unsigned ValReg, const CCValAssign &VA); unsigned extendRegister(unsigned ValReg, const CCValAssign &VA);
MachineInstrBuilder &MIB; MachineInstrBuilder &MIB;
}; };
} // end anonymous namespace } // end anonymous namespace
void OutgoingValueHandler::assignValueToReg(unsigned ValVReg, void OutgoingValueHandler::assignValueToReg(unsigned ValVReg,
const CCValAssign &VA) { const CCValAssign &VA,
const EVT &VT) {
unsigned PhysReg = VA.getLocReg(); unsigned PhysReg = VA.getLocReg();
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
MIRBuilder
.buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
: Mips::ExtractElementF64)
.addDef(PhysReg + (STI.isLittle() ? 1 : 0))
.addUse(ValVReg)
.addImm(1)
.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
*STI.getRegBankInfo());
MIRBuilder
.buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
: Mips::ExtractElementF64)
.addDef(PhysReg + (STI.isLittle() ? 0 : 1))
.addUse(ValVReg)
.addImm(0)
.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
*STI.getRegBankInfo());
} else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
MIRBuilder.buildInstr(Mips::MFC1)
.addDef(PhysReg)
.addUse(ValVReg)
.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
*STI.getRegBankInfo());
} else {
unsigned ExtReg = extendRegister(ValVReg, VA); unsigned ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg); MIRBuilder.buildCopy(PhysReg, ExtReg);
MIB.addUse(PhysReg, RegState::Implicit); MIB.addUse(PhysReg, RegState::Implicit);
} }
}
unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA, unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
MachineMemOperand *&MMO) { MachineMemOperand *&MMO) {
MachineFunction &MF = MIRBuilder.getMF(); MachineFunction &MF = MIRBuilder.getMF();
const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
LLT p0 = LLT::pointer(0, 32); LLT p0 = LLT::pointer(0, 32);
LLT s32 = LLT::scalar(32); LLT s32 = LLT::scalar(32);
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines default:
break; break;
} }
llvm_unreachable("unable to extend register"); llvm_unreachable("unable to extend register");
} }
bool OutgoingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs, bool OutgoingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
ArrayRef<CCValAssign> ArgLocs, ArrayRef<CCValAssign> ArgLocs,
unsigned ArgLocsStartIndex, unsigned ArgLocsStartIndex,
unsigned ArgsReg) { unsigned ArgsReg, const EVT &VT) {
MIRBuilder.buildUnmerge(VRegs, ArgsReg); MIRBuilder.buildUnmerge(VRegs, ArgsReg);
setLeastSignificantFirst(VRegs); setLeastSignificantFirst(VRegs);
if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex)) if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
return false; return false;
return true; return true;
} }
static bool isSupportedType(Type *T) { static bool isSupportedType(Type *T) {
if (T->isIntegerTy()) if (T->isIntegerTy())
return true; return true;
if (T->isPointerTy()) if (T->isPointerTy())
return true; return true;
if (T->isFloatingPointTy())
return true;
return false; return false;
} }
static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
const ISD::ArgFlagsTy &Flags) { const ISD::ArgFlagsTy &Flags) {
// > does not mean loss of information as type RegisterVT can't hold type VT, // > does not mean loss of information as type RegisterVT can't hold type VT,
// it means that type VT is split into multiple registers of type RegisterVT // it means that type VT is split into multiple registers of type RegisterVT
if (VT.getSizeInBits() >= RegisterVT.getSizeInBits()) if (VT.getSizeInBits() >= RegisterVT.getSizeInBits())
▲ Show 20 Lines • Show All 274 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
define float @float_in_fpr(float %a, float %b) {
; FP32-LABEL: name: float_in_fpr
; FP32: bb.1.entry:
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP32: $f0 = COPY [[COPY1]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: float_in_fpr
; FP64: bb.1.entry:
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP64: $f0 = COPY [[COPY1]](s32)
; FP64: RetRA implicit $f0
entry:
ret float %b
}
define double @double_in_fpr(double %a, double %b) {
; FP32-LABEL: name: double_in_fpr
; FP32: bb.1.entry:
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
; FP32: $d0 = COPY [[COPY1]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: double_in_fpr
; FP64: bb.1.entry:
; FP64: liveins: $d12_64, $d14_64
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d14_64
; FP64: $d0_64 = COPY [[COPY1]](s64)
; FP64: RetRA implicit $d0_64
entry:
ret double %b
}
define float @float_in_gpr(i32 %a, float %b) {
; FP32-LABEL: name: float_in_gpr
; FP32: bb.1.entry:
; FP32: liveins: $a0, $a1
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
; FP32: $f0 = COPY [[MTC1_]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: float_in_gpr
; FP64: bb.1.entry:
; FP64: liveins: $a0, $a1
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
; FP64: $f0 = COPY [[MTC1_]](s32)
; FP64: RetRA implicit $f0
entry:
ret float %b
}
define double @double_in_gpr(i32 %a, double %b) {
; FP32-LABEL: name: double_in_gpr
; FP32: bb.1.entry:
; FP32: liveins: $a0, $a2, $a3
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
; FP32: $d0 = COPY [[BuildPairF64_]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: double_in_gpr
; FP64: bb.1.entry:
; FP64: liveins: $a0, $a2, $a3
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 $a2, $a3
; FP64: $d0_64 = COPY [[BuildPairF64_64_]](s64)
; FP64: RetRA implicit $d0_64
entry:
ret double %b
}
define float @call_float_in_fpr(float %a, float %b) {
; FP32-LABEL: name: call_float_in_fpr
; FP32: bb.1.entry:
; FP32: liveins: $f12, $f14
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $f12 = COPY [[COPY]](s32)
; FP32: $f14 = COPY [[COPY1]](s32)
; FP32: JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $f0 = COPY [[COPY2]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: call_float_in_fpr
; FP64: bb.1.entry:
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $f12 = COPY [[COPY]](s32)
; FP64: $f14 = COPY [[COPY1]](s32)
; FP64: JAL @float_in_fpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $f0 = COPY [[COPY2]](s32)
; FP64: RetRA implicit $f0
entry:
%call = call float @float_in_fpr(float %a, float %b)
ret float %call
}
define double @call_double_in_fpr(double %a, double %b) {
; FP32-LABEL: name: call_double_in_fpr
; FP32: bb.1.entry:
; FP32: liveins: $d6, $d7
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $d6 = COPY [[COPY]](s64)
; FP32: $d7 = COPY [[COPY1]](s64)
; FP32: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $d0 = COPY [[COPY2]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: call_double_in_fpr
; FP64: bb.1.entry:
; FP64: liveins: $d12_64, $d14_64
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d12_64
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d14_64
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $d12_64 = COPY [[COPY]](s64)
; FP64: $d14_64 = COPY [[COPY1]](s64)
; FP64: JAL @double_in_fpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit $d14_64, implicit-def $d0_64
; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $d0_64 = COPY [[COPY2]](s64)
; FP64: RetRA implicit $d0_64
entry:
%call = call double @double_in_fpr(double %a, double %b)
ret double %call
}
define float @call_float_in_gpr(i32 %a, float %b) {
; FP32-LABEL: name: call_float_in_gpr
; FP32: bb.1.entry:
; FP32: liveins: $a0, $a1
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $a0 = COPY [[COPY]](s32)
; FP32: $a1 = MFC1 [[MTC1_]](s32)
; FP32: JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $f0 = COPY [[COPY1]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: call_float_in_gpr
; FP64: bb.1.entry:
; FP64: liveins: $a0, $a1
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $a0 = COPY [[COPY]](s32)
; FP64: $a1 = MFC1 [[MTC1_]](s32)
; FP64: JAL @float_in_gpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $f0 = COPY [[COPY1]](s32)
; FP64: RetRA implicit $f0
entry:
%call = call float @float_in_gpr(i32 %a, float %b)
ret float %call
}
define double @call_double_in_gpr(i32 %a, double %b) {
; FP32-LABEL: name: call_double_in_gpr
; FP32: bb.1.entry:
; FP32: liveins: $a0, $a2, $a3
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $a0 = COPY [[COPY]](s32)
; FP32: $a3 = ExtractElementF64 [[BuildPairF64_]](s64), 1
; FP32: $a2 = ExtractElementF64 [[BuildPairF64_]](s64), 0
; FP32: JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $d0 = COPY [[COPY1]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: call_double_in_gpr
; FP64: bb.1.entry:
; FP64: liveins: $a0, $a2, $a3
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 $a2, $a3
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $a0 = COPY [[COPY]](s32)
; FP64: $a3 = ExtractElementF64_64 [[BuildPairF64_64_]](s64), 1
; FP64: $a2 = ExtractElementF64_64 [[BuildPairF64_64_]](s64), 0
; FP64: JAL @double_in_gpr, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0_64
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $d0_64 = COPY [[COPY1]](s64)
; FP64: RetRA implicit $d0_64
entry:
%call = call double @double_in_gpr(i32 %a, double %b)
ret double %call
}