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[CodeGenPrepare] limit formation of overflow intrinsics (PR41129)
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Authored by spatel on Mar 20 2019, 10:07 AM.

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Summary

This is probably a bigger limitation than necessary, but since we don't have any evidence yet that this transform led to perf improvements rather than regressions, I'm proposing a quick, blunt fix.

In the motivating x86 example from:
https://bugs.llvm.org/show_bug.cgi?id=41129
...and shown in the regression test, we want to avoid an extra instruction in the dominating block because that could be costly.

The x86 LSR test diff is reversing the changes from D57789. I don't have evidence that 1 version is any better than the other.

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Event Timeline

spatel created this revision.Mar 20 2019, 10:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 20 2019, 10:07 AM
Carrot accepted this revision.Mar 20 2019, 6:34 PM

Thanks a lot!

This should not be a problem for a 3-address ISA, like PPC or ARM.

This revision is now accepted and ready to land.Mar 20 2019, 6:34 PM
This revision was automatically updated to reflect the committed changes.