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[X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend.
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Authored by craig.topper on Mar 17 2019, 9:11 PM.

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Summary

This patch enables the use of lowerShuffleAsBitMask for 512-bit blends before
falling back to move immedate, GPR to k-register, and masked op.

I had to make some changes to support v8i64 when i64 is not a legal type. And to
support floating point types.

This trades a load for the move immediate and GPR move which is higher latency.
But its probably better for register pressure not having to hop through other
register classes. The load+and should play better with LICM and
rematerialization I think.

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rL LLVM

Event Timeline

craig.topper created this revision.Mar 17 2019, 9:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 17 2019, 9:11 PM
RKSimon added a comment.EditedMar 18 2019, 7:39 AM

Should we not do this if opt-size is set?

Add optsize qualification. Copied one of the test cases in avx512-mask-op.ll and add the optsize attribute to test.

RKSimon accepted this revision.Mar 20 2019, 2:04 AM

LGTM - cheers

This revision is now accepted and ready to land.Mar 20 2019, 2:04 AM
This revision was automatically updated to reflect the committed changes.
fhahn added a subscriber: fhahn.Mar 22 2019, 8:25 AM

I've bisected https://bugs.llvm.org/show_bug.cgi?id=41203 to this commit, which seems to cause crashes when building the test-suite with AXV512.