[DAG] Move integer setcc %x, %x folding into FoldSetCC

[RKSimon]

Summary

First step towards PR40800

I intend to move the float case in a separate future patch

I had to tweak the (overly reduced) thumb2 test

The x86 widening test change is annoying (no longer rematerializable) but we should address this separately.

[t.p.northover]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3007–3008

I think you might still get here if someone does a sneaky MorphNodeTo behind your back. Might be safer to bail with non-debug code.

[RKSimon]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3007–3008

FoldSetCC is called at the start of this function now so I think we should be safe - but I'm happy to update the if to:

if (N0 == N1 && !N0.getValueType().isInteger()) {

[t.p.northover]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3007–3008

Is that new? I can't see it in my source.

[RKSimon]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3007–3008

I committed it yesterday in rL355828

[t.p.northover]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

3007–3008

Ah, sorry. I thought you meant MorphNodeTo by "this" (my mistake). The assert is fine by me then.

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
   case ISD::SETO:
   case ISD::SETUO:
   case ISD::SETUEQ:
   case ISD::SETUNE:
     assert(!OpVT.isInteger() && "Illegal setcc for integer!");
     break;
   }
 
+  // We can always fold X == X for integer setcc's.
+  if (N1 == N2 && OpVT.isInteger())
+    return getBoolConstant(ISD::isTrueWhenEqual(Cond), dl, VT, OpVT);
+
   if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2)) {
     const APInt &C2 = N2C->getAPIntValue();
     if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
       const APInt &C1 = N1C->getAPIntValue();
 
       switch (Cond) {
       default: llvm_unreachable("Unknown integer setcc!");
       case ISD::SETEQ:  return getBoolConstant(C1 == C2, dl, VT, OpVT);

lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
         }
       }
     }
   }
 
   if (N0 == N1) {
     // The sext(setcc()) => setcc() optimization relies on the appropriate
     // constant being emitted.
+    assert(!N0.getValueType().isInteger() &&
+           "Integer types should be handled by FoldSetCC");
 
     bool EqTrue = ISD::isTrueWhenEqual(Cond);
-
-    // We can always fold X == X for integer setcc's.
-    if (N0.getValueType().isInteger())
-      return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
-
     unsigned UOF = ISD::getUnorderedFlavor(Cond);
     if (UOF == 2) // FP operators that are undefined on NaNs.
       return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
     if (UOF == unsigned(EqTrue))
       return DAG.getBoolConstant(EqTrue, dl, VT, OpVT);
     // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
     // if it is not already.
     ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;

test/CodeGen/AArch64/fast-isel-cmp-vec.ll

 bb2:
   %z = zext <2 x i1> %c to <2 x i32>
   ret <2 x i32> %z
 }
 
 define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: icmp_constfold_v2i32:
 ; CHECK:      ; %bb.0:
-; CHECK-NEXT:  movi.2d v[[CMP:[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.2s [[MASK:v[0-9]+]], #1
-; CHECK-NEXT:  and.8b v0, v[[CMP]], [[MASK]]
+; CHECK-NEXT:  and.8b v0, [[MASK]], [[MASK]]
 ; CHECK-NEXT:  ret
   %1 = icmp eq <2 x i32> %a, %a
   br label %bb2
 bb2:
   %2 = zext <2 x i1> %1 to <2 x i32>
   ret <2 x i32> %2
 }
 

 bb2:
   %z = zext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %z
 }
 
 define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: icmp_constfold_v4i32:
 ; CHECK:      ; %bb.0:
-; CHECK-NEXT:  movi.2d v[[CMP:[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #1
-; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
+; CHECK-NEXT: ; %bb.1:
+; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], [[MASK]], [[MASK]]
 ; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
 ; CHECK-NEXT:  ret
   %1 = icmp eq <4 x i32> %a, %a
   br label %bb2
 bb2:
   %2 = zext <4 x i1> %1 to <4 x i32>
   ret <4 x i32> %2
 }

 bb2:
   %z = zext <16 x i1> %c to <16 x i8>
   ret <16 x i8> %z
 }
 
 define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: icmp_constfold_v16i8:
 ; CHECK:      ; %bb.0:
-; CHECK-NEXT:  movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.16b [[MASK:v[0-9]+]], #1
-; CHECK-NEXT:  and.16b v0, [[CMP]], [[MASK]]
+; CHECK-NEXT:  and.16b v0, [[MASK]], [[MASK]]
 ; CHECK-NEXT:  ret
   %1 = icmp eq <16 x i8> %a, %a
   br label %bb2
 bb2:
   %2 = zext <16 x i1> %1 to <16 x i8>
   ret <16 x i8> %2
 }

test/CodeGen/Thumb2/cross-rc-coalescing-2.ll

; CHECK: blt
   store float %28, float* %fi.1, align 4
   %29 = fadd float %12, %24                       ; <float> [#uses=1]
   store float %29, float* null, align 4
   %30 = fmul float 0.000000e+00, %21              ; <float> [#uses=1]
   %31 = fmul float %s1.02, %17                    ; <float> [#uses=1]
   %32 = fsub float %30, %31                       ; <float> [#uses=1]
   %33 = fsub float %10, %32                       ; <float> [#uses=1]
   store float %33, float* undef, align 4
-  %34 = icmp slt i32 undef, undef                 ; <i1> [#uses=1]
+  %34 = icmp slt i32 %tmp54, %tmp80               ; <i1> [#uses=1]
   br i1 %34, label %bb8, label %bb9
 
 bb9:                                              ; preds = %bb8
   %35 = fadd float 0.000000e+00, %33
   br label %bb7
 }

test/CodeGen/X86/widen_compare-1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64
 
 ; compare v2i16
 
 define <2 x i16> @compare_v2i64_to_v2i16_unary(<2 x i16>* %src) nounwind {
 ; X86-LABEL: compare_v2i64_to_v2i16_unary:
 ; X86:       # %bb.0:
-; X86-NEXT:    pcmpeqd %xmm0, %xmm0
+; X86-NEXT:    movaps {{.*#+}} xmm0 = [65535,0,65535,0]
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: compare_v2i64_to_v2i16_unary:
 ; X64:       # %bb.0:
-; X64-NEXT:    pcmpeqd %xmm0, %xmm0
+; X64-NEXT:    movaps {{.*#+}} xmm0 = [65535,65535]
 ; X64-NEXT:    retq
   %val = load <2 x i16>, <2 x i16>* %src, align 4
   %cmp = icmp uge <2 x i16> %val, %val
   %sel = select <2 x i1> %cmp, <2 x i16> <i16 -1, i16 -1>, <2 x i16> zeroinitializer
   ret <2 x i16> %sel
 }
 
 define <2 x i16> @compare_v2i64_to_v2i16_binary(<2 x i16>* %src0, <2 x i16>* %src1) nounwind {