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Differential D58932

[RISCV] Allow access to FP CSRs without F extension
ClosedPublic

Authored by apazos on Mar 4 2019, 3:38 PM.

Details

Reviewers
asb
Commits
rG5254d1baae63: [RISCV] Allow access to FP CSRs without F extension
rL355753: [RISCV] Allow access to FP CSRs without F extension
Summary

Floating-point CSRs should be accessible even when F extension is not enabled.
But pseudo instructions that access floating point CSRs still require the F extension.
GNU tools already implement this behavior.
RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs.

Diff Detail

Event Timeline

apazos created this revision.Mar 4 2019, 3:38 PM
Herald added subscribers: jocewei, PkmX, rkruppe and 14 others. · View Herald TranscriptMar 4 2019, 3:38 PM
asb requested changes to this revision.Mar 7 2019, 6:19 AM
asb added a reviewer: asb.

The behaviour I'm seeing with a recent-ish GCC toolchain is that the floating points CSR names are accepted regardless of -march, but the pseudoinstructions (e.g. frcsr) require the F extension to be enabled.

This revision now requires changes to proceed.Mar 7 2019, 6:19 AM
apazos added a comment.Mar 7 2019, 8:56 AM

OK, I can restrict the patch to access CSR names and value range without F extension, while we wait GCC and the RISC-V specs to be updated.

apazos updated this revision to Diff 189774.Mar 7 2019, 1:25 PM
apazos edited the summary of this revision. (Show Details)

Leaving pseudo instructions that access FP CSRs untouched for now.

asb accepted this revision.Mar 7 2019, 1:37 PM

LGTM, thanks!

This revision is now accepted and ready to land.Mar 7 2019, 1:37 PM
Closed by commit rL355753: [RISCV] Allow access to FP CSRs without F extension (authored by apazos). · Explain WhyMar 8 2019, 3:01 PM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMar 8 2019, 3:01 PM
Herald added a subscriber: jrtc27. · View Herald Transcript
jrtc27 mentioned this in D109587: [RISCV]Generate target attribute in attribute section of object file when assemble .s file.Sep 10 2021, 3:18 AM
craig.topper mentioned this in D116350: [RISCV] Modification of RVV CSR test file.Dec 28 2021, 8:41 PM

Revision Contents

PathSize
lib/
Target/
RISCV/
2 lines
test/
MC/
RISCV/
26 lines
2 lines
12 lines
11 lines

Diff 189774

lib/Target/RISCV/RISCVSystemOperands.td

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def : SysReg<"ucause", 0x042>; def : SysReg<"ucause", 0x042>;
def : SysReg<"utval", 0x043>; def : SysReg<"utval", 0x043>;
def : SysReg<"uip", 0x044>; def : SysReg<"uip", 0x044>;
//===-------------------------- //===--------------------------
// User Floating-Point CSRs // User Floating-Point CSRs
//===-------------------------- //===--------------------------
let FeaturesRequired = [{ {RISCV::FeatureStdExtF} }] in {
def : SysReg<"fflags", 0x001>; def : SysReg<"fflags", 0x001>;
def : SysReg<"frm", 0x002>; def : SysReg<"frm", 0x002>;
def : SysReg<"fcsr", 0x003>; def : SysReg<"fcsr", 0x003>;
}
//===-------------------------- //===--------------------------
// User Counter/Timers // User Counter/Timers
//===-------------------------- //===--------------------------
def : SysReg<"cycle", 0xC00>; def : SysReg<"cycle", 0xC00>;
def : SysReg<"time", 0xC01>; def : SysReg<"time", 0xC01>;
def : SysReg<"instret", 0xC02>; def : SysReg<"instret", 0xC02>;
▲ Show 20 Lines • Show All 265 Lines • Show Last 20 Lines

test/MC/RISCV/csr-aliases.s

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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
# RUN: | llvm-objdump -d -mattr=-f - \ # RUN: | llvm-objdump -d -mattr=-f - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
# CHECK-INST: csrrs t0, fcsr, zero # CHECK-INST: csrrs t0, fcsr, zero
# CHECK-ALIAS: frcsr t0 # CHECK-ALIAS: frcsr t0
# CHECK-EXT-F: frcsr t0 # CHECK-EXT-F: frcsr t0
# CHECK-EXT-F-OFF: csrr t0, 3 # CHECK-EXT-F-OFF: csrr t0, fcsr
csrrs t0, 3, zero csrrs t0, 3, zero
# CHECK-INST: csrrw t1, fcsr, t2 # CHECK-INST: csrrw t1, fcsr, t2
# CHECK-ALIAS: fscsr t1, t2 # CHECK-ALIAS: fscsr t1, t2
# CHECK-EXT-F-ON: fscsr t1, t2 # CHECK-EXT-F-ON: fscsr t1, t2
# CHECK-EXT-F-OFF: csrrw t1, 3, t2 # CHECK-EXT-F-OFF: csrrw t1, fcsr, t2
csrrw t1, 3, t2 csrrw t1, 3, t2
# CHECK-INST: csrrw zero, fcsr, t2 # CHECK-INST: csrrw zero, fcsr, t2
# CHECK-ALIAS: fscsr t2 # CHECK-ALIAS: fscsr t2
# CHECK-EXT-F-ON: fscsr t2 # CHECK-EXT-F-ON: fscsr t2
# CHECK-EXT-F-OFF: csrw 3, t2 # CHECK-EXT-F-OFF: csrw fcsr, t2
csrrw zero, 3, t2 csrrw zero, 3, t2
# CHECK-INST: csrrw zero, fcsr, t2 # CHECK-INST: csrrw zero, fcsr, t2
# CHECK-ALIAS: fscsr t2 # CHECK-ALIAS: fscsr t2
# CHECK-EXT-F-ON: fscsr t2 # CHECK-EXT-F-ON: fscsr t2
# CHECK-EXT-F-OFF: csrw 3, t2 # CHECK-EXT-F-OFF: csrw fcsr, t2
csrrw zero, 3, t2 csrrw zero, 3, t2
# CHECK-INST: csrrw t0, frm, zero # CHECK-INST: csrrw t0, frm, zero
# CHECK-ALIAS: fsrm t0, zero # CHECK-ALIAS: fsrm t0, zero
# CHECK-EXT-F-ON: fsrm t0, zero # CHECK-EXT-F-ON: fsrm t0, zero
# CHECK-EXT-F-OFF: csrrw t0, 2, zero # CHECK-EXT-F-OFF: csrrw t0, frm
csrrw t0, 2, zero csrrw t0, 2, zero
# CHECK-INST: csrrw t0, frm, t1 # CHECK-INST: csrrw t0, frm, t1
# CHECK-ALIAS: fsrm t0, t1 # CHECK-ALIAS: fsrm t0, t1
# CHECK-EXT-F-ON: fsrm t0, t1 # CHECK-EXT-F-ON: fsrm t0, t1
# CHECK-EXT-F-OFF: csrrw t0, 2, t1 # CHECK-EXT-F-OFF: csrrw t0, frm, t1
csrrw t0, 2, t1 csrrw t0, 2, t1
# CHECK-INST: csrrwi t0, frm, 31 # CHECK-INST: csrrwi t0, frm, 31
# CHECK-ALIAS: fsrmi t0, 31 # CHECK-ALIAS: fsrmi t0, 31
# CHECK-EXT-F-ON: fsrmi t0, 31 # CHECK-EXT-F-ON: fsrmi t0, 31
# CHECK-EXT-F-OFF: csrrwi t0, 2, 31 # CHECK-EXT-F-OFF: csrrwi t0, frm, 31
csrrwi t0, 2, 31 csrrwi t0, 2, 31
# CHECK-INST: csrrwi zero, frm, 31 # CHECK-INST: csrrwi zero, frm, 31
# CHECK-ALIAS: fsrmi 31 # CHECK-ALIAS: fsrmi 31
# CHECK-EXT-F-ON: fsrmi 31 # CHECK-EXT-F-ON: fsrmi 31
# CHECK-EXT-F-OFF: csrwi 2, 31 # CHECK-EXT-F-OFF: csrwi frm, 31
csrrwi zero, 2, 31 csrrwi zero, 2, 31
# CHECK-INST: csrrs t0, fflags, zero # CHECK-INST: csrrs t0, fflags, zero
# CHECK-ALIAS: frflags t0 # CHECK-ALIAS: frflags t0
# CHECK-EXT-F-ON: frflags t0 # CHECK-EXT-F-ON: frflags t0
# CHECK-EXT-F-OFF: csrr t0, 1 # CHECK-EXT-F-OFF: csrr t0, fflags
csrrs t0, 1, zero csrrs t0, 1, zero
# CHECK-INST: csrrw t0, fflags, t2 # CHECK-INST: csrrw t0, fflags, t2
# CHECK-ALIAS: fsflags t0, t2 # CHECK-ALIAS: fsflags t0, t2
# CHECK-EXT-F-ON: fsflags t0, t2 # CHECK-EXT-F-ON: fsflags t0, t2
# CHECK-EXT-F-OFF: csrrw t0, 1, t2 # CHECK-EXT-F-OFF: csrrw t0, fflags, t2
csrrw t0, 1, t2 csrrw t0, 1, t2
# CHECK-INST: csrrw zero, fflags, t2 # CHECK-INST: csrrw zero, fflags, t2
# CHECK-ALIAS: fsflags t2 # CHECK-ALIAS: fsflags t2
# CHECK-EXT-F-ON: fsflags t2 # CHECK-EXT-F-ON: fsflags t2
# CHECK-EXT-F-OFF: csrw 1, t2 # CHECK-EXT-F-OFF: csrw fflags, t2
csrrw zero, 1, t2 csrrw zero, 1, t2
# CHECK-INST: csrrwi t0, fflags, 31 # CHECK-INST: csrrwi t0, fflags, 31
# CHECK-ALIAS: fsflagsi t0, 31 # CHECK-ALIAS: fsflagsi t0, 31
# CHECK-EXT-F: fsflagsi t0, 31 # CHECK-EXT-F: fsflagsi t0, 31
# CHECK-EXT-F-OFF: csrrwi t0, 1, 31 # CHECK-EXT-F-OFF: csrrwi t0, fflags, 31
csrrwi t0, 1, 31 csrrwi t0, 1, 31
# CHECK-INST: csrrwi zero, fflags, 31 # CHECK-INST: csrrwi zero, fflags, 31
# CHECK-ALIAS: fsflagsi 31 # CHECK-ALIAS: fsflagsi 31
# CHECK-EXT-F: fsflagsi 31 # CHECK-EXT-F: fsflagsi 31
# CHECK-EXT-F-OFF: csrwi 1, 31 # CHECK-EXT-F-OFF: csrwi fflags, 31
csrrwi zero, 1, 31 csrrwi zero, 1, 31

test/MC/RISCV/rv32i-valid.s

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.equ CONST, 16 .equ CONST, 16
# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
# CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff] # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]
csrrw t0, 0xfff, t1 csrrw t0, 0xfff, t1
# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
# CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0] # CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
csrrs s0, 0xc00, x0 csrrs s0, 0xc00, x0
# CHECK-ASM-AND-OBJ: csrrs s3, 1, s5 # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
# CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00] # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
csrrs s3, 0x001, s5 csrrs s3, 0x001, s5
# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra # CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00] # CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]
csrrc sp, 0x000, ra csrrc sp, 0x000, ra
# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 # CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00] # CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00]
csrrwi a5, 0x000, 0 csrrwi a5, 0x000, 0
# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
# CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff] # CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff]
csrrsi t2, 0xfff, 31 csrrsi t2, 0xfff, 31
# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 # CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
# CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14] # CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14]
csrrci t1, 0x140, 5 csrrci t1, 0x140, 5

test/MC/RISCV/rvf-user-csr-names.s

Show All 19 Lines
# User Floating Pont CSRs # User Floating Pont CSRs
################################## ##################################
# fflags # fflags
# name # name
# CHECK-INST: csrrs t1, fflags, zero # CHECK-INST: csrrs t1, fflags, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x00] # CHECK-ENC: encoding: [0x73,0x23,0x10,0x00]
# CHECK-INST-ALIAS: frflags t1 # CHECK-INST-ALIAS: frflags t1
# CHECK-INST-ALIAS-NO-F: csrr t1, 1 # CHECK-INST-ALIAS-NO-F: csrr t1, fflags
# uimm12 # uimm12
# CHECK-INST: csrrs t2, fflags, zero # CHECK-INST: csrrs t2, fflags, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x00] # CHECK-ENC: encoding: [0xf3,0x23,0x10,0x00]
# CHECK-INST-ALIAS: frflags t2 # CHECK-INST-ALIAS: frflags t2
# CHECK-INST-ALIAS-NO-F: csrr t2, 1 # CHECK-INST-ALIAS-NO-F: csrr t2, fflags
# name # name
csrrs t1, fflags, zero csrrs t1, fflags, zero
# uimm12 # uimm12
csrrs t2, 0x001, zero csrrs t2, 0x001, zero
# frm # frm
# name # name
# CHECK-INST: csrrs t1, frm, zero # CHECK-INST: csrrs t1, frm, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x00] # CHECK-ENC: encoding: [0x73,0x23,0x20,0x00]
# CHECK-INST-ALIAS: frrm t1 # CHECK-INST-ALIAS: frrm t1
# CHECK-INST-ALIAS-NO-F: csrr t1, 2 # CHECK-INST-ALIAS-NO-F: csrr t1, frm
# uimm12 # uimm12
# CHECK-INST: csrrs t2, frm, zero # CHECK-INST: csrrs t2, frm, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x00] # CHECK-ENC: encoding: [0xf3,0x23,0x20,0x00]
# CHECK-INST-ALIAS: frrm t2 # CHECK-INST-ALIAS: frrm t2
# CHECK-INST-ALIAS-NO-F: csrr t2, 2 # CHECK-INST-ALIAS-NO-F: csrr t2, frm
# name # name
csrrs t1, frm, zero csrrs t1, frm, zero
# uimm12 # uimm12
csrrs t2, 0x002, zero csrrs t2, 0x002, zero
# fcsr # fcsr
# name # name
# CHECK-INST: csrrs t1, fcsr, zero # CHECK-INST: csrrs t1, fcsr, zero
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x00] # CHECK-ENC: encoding: [0x73,0x23,0x30,0x00]
# CHECK-INST-ALIAS: frcsr t1 # CHECK-INST-ALIAS: frcsr t1
# CHECK-INST-ALIAS-NO-F: csrr t1, 3 # CHECK-INST-ALIAS-NO-F: csrr t1, fcsr
# uimm12 # uimm12
# CHECK-INST: csrrs t2, fcsr, zero # CHECK-INST: csrrs t2, fcsr, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x00] # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x00]
# CHECK-INST-ALIAS: frcsr t2 # CHECK-INST-ALIAS: frcsr t2
# CHECK-INST-ALIAS-NO-F: csrr t2, 3 # CHECK-INST-ALIAS-NO-F: csrr t2, fcsr
# name # name
csrrs t1, fcsr, zero csrrs t1, fcsr, zero
# uimm12 # uimm12
csrrs t2, 0x003, zero csrrs t2, 0x003, zero

test/MC/RISCV/user-csr-names-invalid.s

# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-NEED-F %s
# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \ # RUN: not llvm-mc -triple riscv64 < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NEED-RV32,CHECK-NEED-F %s # RUN: | FileCheck -check-prefixes=CHECK-NEED-RV32 %s
# These user mode CSR register names are RV32 only. # These user mode CSR register names are RV32 only.
csrrs t1, cycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, cycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, timeh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, timeh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, instreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, instreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
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csrrs t1, hpmcounter24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
# These user mode CSR register names require F extension.
csrrs t1, fflags, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, frm, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, fcsr, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled