Adding an option to use for targets that do not have support for atomic load-modify-store instructions

[maya.madhavan]

Summary

The ARM documentation for ARMv7-M indicates that atomic read-modify-write operations can be implemented using LDREX/STREX loops but some Cortex-M4 hardware implementations including ti_sitara_m4 and fsl_imx6sx_m4 do not provide the "global monitor" required to support exclusive load/stores. On such hardware, use of LDREX/STREX leads to a bus error (Signal 10) or segmentation fault (Signal 11).

See:
http://e2e.ti.com/support/arm/automotive_processors/f/1021/t/708195?tisearch=e2e-quicksearch&keymatch=ldrex
https://e2e.ti.com/support/legacy_forums/embedded/tirtos/f/355/p/541932/1979054#1979054

The "mno-gm" option (gm for Global Monitor) suppresses the generation of these RMW instructions and uses libcalls instead.

[maya.madhavan]

$ /home/mmadhava/llvm-trunk/llvm-project/fullbuild/bin/llc -verify-machineinstrs -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 /home/mmadhava/llvm-trunk/llvm-project/llvm/test/CodeGen/ARM/atomic-nogm.ll -o - | /home/mmadhava/llvm-trunk/llvm-project/fullbuild/bin/FileCheck /home/mmadhava/llvm-trunk/llvm-project/llvm/test/CodeGen/ARM/atomic-nogm.ll && echo $?
0
$ /home/mmadhava/llvm-trunk/llvm-project/fullbuild/bin/llc -verify-machineinstrs -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 -mattr=+no-gm /home/mmadhava/llvm-trunk/llvm-project/llvm/test/CodeGen/ARM/atomic-nogm.ll -o - | /home/mmadhava/llvm-trunk/llvm-project/fullbuild/bin/FileCheck /home/mmadhava/llvm-trunk/llvm-project/llvm/test/CodeGen/ARM/atomic-nogm.ll --check-prefix=CHECK-T1 && echo $?
0
$ /home/mmadhava/llvm-trunk/llvm-project/fullbuild/bin/llc -verify-machineinstrs -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 -mattr=+no-gm -mattr=-no-gm /home/mmadhava/llvm-trunk/llvm-project/llvm/test/CodeGen/ARM/atomic-nogm.ll -o - | /home/mmadhava/llvm-trunk/llvm-project/fullbuild/bin/FileCheck /home/mmadhava/llvm-trunk/llvm-project/llvm/test/CodeGen/ARM/atomic-nogm.ll && echo $?
0

clang/include/clang/Driver/Options.td

 def mno_movt : Flag<["-"], "mno-movt">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of movt/movw pairs (ARM only)">;
 def mcrc : Flag<["-"], "mcrc">, Group<m_Group>,
   HelpText<"Allow use of CRC instructions (ARM/Mips only)">;
 def mnocrc : Flag<["-"], "mnocrc">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of CRC instructions (ARM only)">;
 def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">, Group<m_arm_Features_Group>,
   HelpText<"Disallow converting instructions with negative immediates to their negation or inversion.">;
+def mgm: Flag<["-"], "mgm">, Group<m_arm_Features_Group>,
+  HelpText<"Target has a Global Monitor, supports ldrex/strex atomic instructions.">;
+def mno_gm: Flag<["-"], "mno-gm">, Group<m_arm_Features_Group>,
+  HelpText<"Target has no Global Monitor, does not support /strex atomic instructions.">;
 
 def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group<m_aarch64_Features_Group>,
   HelpText<"Generate code which only uses the general purpose registers (AArch64 only)">;
 def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
   Group<m_aarch64_Features_Group>,
   HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;
 def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
   Group<m_aarch64_Features_Group>,

clang/lib/Driver/ToolChains/Arch/ARM.cpp

if (Args.hasArg(options::OPT_ffixed_r9))
     Features.push_back("+reserve-r9");
 
   // The kext linker doesn't know how to deal with movw/movt.
   if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
     Features.push_back("+no-movt");
 
   if (Args.hasArg(options::OPT_mno_neg_immediates))
     Features.push_back("+no-neg-immediates");
+
+  if (Arg *A = Args.getLastArg(options::OPT_mno_gm, options::OPT_mgm)) {
+    if (A->getOption().matches(options::OPT_mno_gm))
+      Features.push_back("+no-gm");
+  }
 }
 
 const std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
   std::string MArch;
   if (!Arch.empty())
     MArch = Arch;
   else
     MArch = Triple.getArchName();

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

public:
   ///
   /// By default this queries the PostRAScheduling bit in the scheduling model
   /// which is the preferred way to influence this.
   virtual bool enablePostRAScheduler() const;
 
   /// True if the subtarget should run the atomic expansion pass.
   virtual bool enableAtomicExpand() const;
 
+  /// True if the subtarget has a global monitor 
+  virtual bool hasGlobalMonitor() const;
+
   /// True if the subtarget should run the indirectbr expansion pass.
   virtual bool enableIndirectBrExpand() const;
 
   /// Override generic scheduling policy within a region.
   ///
   /// This is a convenient way for targets that don't provide any custom
   /// scheduling heuristics (no custom MachineSchedStrategy) to make
   /// changes to the generic scheduling policy.

llvm/lib/CodeGen/AtomicExpandPass.cpp

if (LI) {
       }
     } else if (SI) {
       if (!atomicSizeSupported(TLI, SI)) {
         expandAtomicStoreToLibcall(SI);
         MadeChange = true;
         continue;
       }
     } else if (RMWI) {
-      if (!atomicSizeSupported(TLI, RMWI)) {
+      if (!atomicSizeSupported(TLI, RMWI) || !TM.getSubtargetImpl(F)->hasGlobalMonitor()) {
         expandAtomicRMWToLibcall(RMWI);
         MadeChange = true;
         continue;
       }
     } else if (CASI) {
       if (!atomicSizeSupported(TLI, CASI)) {
         expandAtomicCASToLibcall(CASI);
         MadeChange = true;

llvm/lib/CodeGen/TargetSubtargetInfo.cpp

 }
 
 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
 
 bool TargetSubtargetInfo::enableAtomicExpand() const {
   return true;
 }
 
+bool TargetSubtargetInfo::hasGlobalMonitor() const {
+  return true;
+}
+
 bool TargetSubtargetInfo::enableIndirectBrExpand() const {
   return false;
 }
 
 bool TargetSubtargetInfo::enableMachineScheduler() const {
   return false;
 }
 

llvm/lib/Target/ARM/ARM.td

 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
                                    "Has full data barrier (dfb) instruction">;
 
 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
                                              "HasAcquireRelease", "true",
                                              "Has v8 acquire/release (lda/ldaex "
                                              " etc) instructions">;
 
+def FeatureHasNoGlobalMonitor : SubtargetFeature<"no-gm",
+                                             "HasNoGlobalMonitor", "true",
+                                             "Has no Global Monitor, no support"
+                                             "for ldrex/strex instructions">;
 
 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
                                              "FP compare + branch is slow">;
 
 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
                                              "Enable support for Performance "
                                              "Monitor extensions">;
 

llvm/lib/Target/ARM/ARMInstrInfo.td

def HasDB            : Predicate<"Subtarget->hasDataBarrier()">,
                                  AssemblerPredicate<"FeatureDB",
                                                     "data-barriers">;
 def HasDFB           : Predicate<"Subtarget->hasFullDataBarrier()">,
                                  AssemblerPredicate<"FeatureDFB",
                                                     "full-data-barrier">;
 def HasV7Clrex  : Predicate<"Subtarget->hasV7Clrex()">,
                             AssemblerPredicate<"FeatureV7Clrex",
                                                "v7 clrex">;
+def HasNoGlobalMonitor : Predicate<"Subtarget->hasNoGlobalMonitor()">;
+def HasGlobalMonitor : Predicate<"!Subtarget->hasNoGlobalMonitor()">;
 def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">,
                                   AssemblerPredicate<"FeatureAcquireRelease",
                                                      "acquire/release">;
 def HasMP            : Predicate<"Subtarget->hasMPExtension()">,
                                  AssemblerPredicate<"FeatureMP",
                                                     "mp-extensions">;
 def HasVirtualization: Predicate<"false">,
                                  AssemblerPredicate<"FeatureVirtualization",

llvm/lib/Target/ARM/ARMInstrThumb2.td

class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
   let Inst{15-12} = Rt;
 }
 
 let mayLoad = 1 in {
 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldrexb", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasV8MBaseline]>;
+               Requires<[IsThumb, HasV8MBaseline, HasGlobalMonitor]>;
 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldrexh", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasV8MBaseline]>;
+               Requires<[IsThumb, HasV8MBaseline, HasGlobalMonitor]>;
 def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
                        AddrModeT2_ldrex, 4, NoItinerary,
                        "ldrex", "\t$Rt, $addr", "",
                      [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,
-               Requires<[IsThumb, HasV8MBaseline]> {
+               Requires<[IsThumb, HasV8MBaseline, HasGlobalMonitor]> {
   bits<4> Rt;
   bits<12> addr;
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0000101;
   let Inst{19-16} = addr{11-8};
   let Inst{15-12} = Rt;
   let Inst{11-8} = 0b1111;
   let Inst{7-0} = addr{7-0};
 }
 let hasExtraDefRegAllocReq = 1 in
 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
                          (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldrexd", "\t$Rt, $Rt2, $addr", "",
                          [], {?, ?, ?, ?}>,
-               Requires<[IsThumb2, IsNotMClass]> {
+               Requires<[IsThumb2, IsNotMClass, HasGlobalMonitor]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 }
 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldaexb", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
+               Requires<[IsThumb, HasAcquireRelease, HasV7Clrex, HasGlobalMonitor]>;
 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldaexh", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
+               Requires<[IsThumb, HasAcquireRelease, HasV7Clrex, HasGlobalMonitor]>;
 def t2LDAEX  : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
                        AddrModeNone, 4, NoItinerary,
                        "ldaex", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
+               Requires<[IsThumb, HasAcquireRelease, HasV7Clrex, HasGlobalMonitor]> {
   bits<4> Rt;
   bits<4> addr;
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0001101;
   let Inst{19-16} = addr;
   let Inst{15-12} = Rt;
   let Inst{11-8} = 0b1111;
   let Inst{7-0} = 0b11101111;

 
 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "strexb", "\t$Rd, $Rt, $addr", "",
                          [(set rGPR:$Rd,
                                (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasV8MBaseline]>;
+               Requires<[IsThumb, HasV8MBaseline, HasGlobalMonitor]>;
 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "strexh", "\t$Rd, $Rt, $addr", "",
                          [(set rGPR:$Rd,
                                (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasV8MBaseline]>;
+               Requires<[IsThumb, HasV8MBaseline, HasGlobalMonitor]>;
 
 def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
                              t2addrmode_imm0_1020s4:$addr),
                   AddrModeT2_ldrex, 4, NoItinerary,
                   "strex", "\t$Rd, $Rt, $addr", "",
                   [(set rGPR:$Rd,
                         (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,
-               Requires<[IsThumb, HasV8MBaseline]> {
+               Requires<[IsThumb, HasV8MBaseline, HasGlobalMonitor]> {
   bits<4> Rd;
   bits<4> Rt;
   bits<12> addr;
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0000100;
   let Inst{19-16} = addr{11-8};
   let Inst{15-12} = Rt;
   let Inst{11-8}  = Rd;
   let Inst{7-0} = addr{7-0};
 }
 let hasExtraSrcRegAllocReq = 1 in
 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
                          {?, ?, ?, ?}>,
-               Requires<[IsThumb2, IsNotMClass]> {
+               Requires<[IsThumb2, IsNotMClass, HasGlobalMonitor]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 }
 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "stlexb", "\t$Rd, $Rt, $addr", "",
                          [(set rGPR:$Rd,
                                (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
                          Requires<[IsThumb, HasAcquireRelease,
-                                   HasV7Clrex]>;
+                                   HasV7Clrex, HasGlobalMonitor]>;
 
 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "stlexh", "\t$Rd, $Rt, $addr", "",
                          [(set rGPR:$Rd,
                                (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
                          Requires<[IsThumb, HasAcquireRelease,
-                                   HasV7Clrex]>;
+                                   HasV7Clrex, HasGlobalMonitor]>;
 
 def t2STLEX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
                              addr_offset_none:$addr),
                   AddrModeNone, 4, NoItinerary,
                   "stlex", "\t$Rd, $Rt, $addr", "",
                   [(set rGPR:$Rd,
                         (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
                   Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> {
   bits<4> Rd;
   bits<4> Rt;
   bits<4> addr;
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0001100;
   let Inst{19-16} = addr;
   let Inst{15-12} = Rt;
   let Inst{11-4}  = 0b11111110;
   let Inst{3-0}   = Rd;
 }
 let hasExtraSrcRegAllocReq = 1 in
 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
                          {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,
-                         HasV7Clrex, IsNotMClass]> {
+                         HasV7Clrex, IsNotMClass, HasGlobalMonitor]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 }
 }
 
 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
             Requires<[IsThumb, HasV7Clrex]>  {
   let Inst{31-16} = 0xf3bf;

llvm/lib/Target/ARM/ARMSubtarget.h

protected:
 
   /// HasV7Clrex - True if the subtarget supports CLREX instructions
   bool HasV7Clrex = false;
 
   /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
   /// instructions
   bool HasAcquireRelease = false;
 
+  /// HasNoGlobalMonitor - True if the subtarget does not have a Global Monitor 
+  /// i.e. cannot support ldrex/strex instructions
+  bool HasNoGlobalMonitor = false;
+
   /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
   /// over 16-bit ones.
   bool Pref32BitThumb = false;
 
   /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
   /// that partially update CPSR and add false dependency on the previous
   /// CPSR setting instruction.
   bool AvoidCPSRPartialUpdate = false;
public:
   }
 
   bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
   bool hasDataBarrier() const { return HasDataBarrier; }
   bool hasFullDataBarrier() const { return HasFullDataBarrier; }
   bool hasV7Clrex() const { return HasV7Clrex; }
   bool hasAcquireRelease() const { return HasAcquireRelease; }
+  bool hasNoGlobalMonitor() const { return HasNoGlobalMonitor; }
 
   bool hasAnyDataBarrier() const {
     return HasDataBarrier || (hasV6Ops() && !isThumb());
   }
 
   bool useMulOps() const { return UseMulOps; }
   bool useFPVMLx() const { return !SlowFPVMLx; }
   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
public:
 
   /// Enable use of alias analysis during code generation (during MI
   /// scheduling, DAGCombine, etc.).
   bool useAA() const override { return UseAA; }
 
   // enableAtomicExpand- True if we need to expand our atomics.
   bool enableAtomicExpand() const override;
 
+  // hasGlobalMonitor - True if the processor has a Global Monitor
+  /// i.e. can support ldrex/strex instructions
+  bool hasGlobalMonitor() const override { return !hasNoGlobalMonitor(); }
+
   /// getInstrItins - Return the instruction itineraries based on subtarget
   /// selection.
   const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
 
   /// getStackAlignment - Returns the minimum alignment known to hold of the
   /// stack frame on entry to the function and which must be maintained by every

llvm/test/CodeGen/ARM/atomic-nogm.ll

+; RUN: llc -verify-machineinstrs -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 -mattr=+no-gm %s -o - | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc -verify-machineinstrs -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 -mattr=+no-gm -mattr=-no-gm %s -o - | FileCheck %s
+
+; CHECK-NOT: __atomic_fetch_add_8
+; CHECK: ldrex
+; CHECK: strex
+; CHECK-NOT: __atomic_fetch_add_4
+; CHECK: ldrexh
+; CHECK: strexh
+; CHECK-NOT: __atomic_fetch_add_2
+; CHECK: ldrexb
+; CHECK: strexb
+; CHECK-NOT: __atomic_fetch_add_1
+; CHECK: ldrexb
+; CHECK: strexb
+; CHECK-NOT: __atomic_exchange_1
+
+; CHECK-T1: __atomic_fetch_add_8
+; CHECK-T1-NOT: ldrex
+; CHECK-T1-NOT: strex
+; CHECK-T1: __atomic_fetch_add_4
+; CHECK-T1-NOT: ldrexh
+; CHECK-T1-NOT: strexh
+; CHECK-T1: __atomic_fetch_add_2
+; CHECK-T1-NOT: ldrexb
+; CHECK-T1-NOT: strexb
+; CHECK-T1: __atomic_fetch_add_1
+; CHECK-T1-NOT: ldrexb
+; CHECK-T1-NOT: strexb
+; CHECK-T1: __atomic_exchange_1
+
+define dso_local void @atomic_function_example_64() #0 {
+entry:
+  %v = alloca i64, align 4
+  store i64 0, i64* %v, align 4
+  %0 = atomicrmw add i64* %v, i64 1 seq_cst
+  %1 = add i64 %0, 1
+  ret void
+}
+
+define dso_local void @atomic_function_example_32() #0 {
+entry:
+  %v = alloca i32, align 4
+  store i32 0, i32* %v, align 4
+  %0 = atomicrmw add i32* %v, i32 1 seq_cst
+  %1 = add i32 %0, 1
+  ret void
+}
+
+define dso_local void @atomic_function_example_16() #0 {
+entry:
+  %v = alloca i16, align 4
+  store i16 0, i16* %v, align 4
+  %0 = atomicrmw add i16* %v, i16 1 seq_cst
+  %1 = add i16 %0, 1
+  ret void
+}
+
+define dso_local void @atomic_function_example_8() #0 {
+entry:
+  %v = alloca i8, align 4
+  store i8 0, i8* %v, align 4
+  %0 = atomicrmw add i8* %v, i8 1 seq_cst
+  %1 = add i8 %0, 1
+  ret void
+}
+
+%struct.atomic_flag = type { i8 }
+
+define dso_local zeroext i1 @atomic_flag_test_and_set(%struct.atomic_flag* %object) #0 {
+entry:
+  %object.addr = alloca %struct.atomic_flag*, align 4
+  %.atomictmp = alloca i8, align 1
+  %atomic-temp = alloca i8, align 1
+  store %struct.atomic_flag* %object, %struct.atomic_flag** %object.addr, align 4
+  %0 = load %struct.atomic_flag*, %struct.atomic_flag** %object.addr, align 4
+  %_Value = getelementptr inbounds %struct.atomic_flag, %struct.atomic_flag* %0, i32 0, i32 0
+  store i8 1, i8* %.atomictmp, align 1
+  %1 = load i8, i8* %.atomictmp, align 1
+  %2 = atomicrmw volatile xchg i8* %_Value, i8 %1 seq_cst
+  store i8 %2, i8* %atomic-temp, align 1
+  %3 = load i8, i8* %atomic-temp, align 1
+  %tobool = trunc i8 %3 to i1
+  ret i1 %tobool
+}
+