[x86] convert anyext of pinsrb scalar op to subreg insert

[spatel]

Summary

This is trying to fix one of the potential regressions seen in D58521, but it's a problem independent of that patch as shown in the diffs here.

We are aggressively converting 'anyext' to 'zext' in isel to avoid partial reg stalls, but that shouldn't be a problem for pinsrb because the instruction only uses the low byte of the 32-bit scalar reg. AFAICT, this isn't a problem for pinsrw because we promote all 16-bit ops.

I'm not sure why we don't get load folding with some of the fast-isel tests, but I assume that's as expected or an independent problem.

[craig.topper]

I'm not convinced that the dependency logic in the frontend and the renaming portion of Intel CPUs know that this instruction only uses the lower 8 bits. Same with BT/BTC/BTR/BTS/SHLX/SHRX/SARX and probably others. On Sandy Bridge and later CPUs, probably the worst this means is that it would force an AH/BH/CH/DH merge if it had been written independently previously. Bits 63:16 and 7:0 are always together. In 64-bit mode that should never really happen since we won't consider the AH/BH/CH/DH for general use by the register allocator.

[spatel]

In D58703#1411623, @craig.topper wrote:

I'm not convinced that the dependency logic in the frontend and the renaming portion of Intel CPUs know that this instruction only uses the lower 8 bits. Same with BT/BTC/BTR/BTS/SHLX/SHRX/SARX and probably others. On Sandy Bridge and later CPUs, probably the worst this means is that it would force an AH/BH/CH/DH merge if it had been written independently previously. Bits 63:16 and 7:0 are always together. In 64-bit mode that should never really happen since we won't consider the AH/BH/CH/DH for general use by the register allocator.

So the movzbl here and in the other patch are preferred? I’m happy to leave this as-is if everyone’s ok with the x86 diffs in D58521. Personally, I don’t think those tests with extra instructions are worth worrying about unless there’s some evidence of a perf regression from that.

[spatel]

In D58703#1411635, @spatel wrote:

In D58703#1411623, @craig.topper wrote:

I'm not convinced that the dependency logic in the frontend and the renaming portion of Intel CPUs know that this instruction only uses the lower 8 bits. Same with BT/BTC/BTR/BTS/SHLX/SHRX/SARX and probably others. On Sandy Bridge and later CPUs, probably the worst this means is that it would force an AH/BH/CH/DH merge if it had been written independently previously. Bits 63:16 and 7:0 are always together. In 64-bit mode that should never really happen since we won't consider the AH/BH/CH/DH for general use by the register allocator.

So the movzbl here and in the other patch are preferred? I’m happy to leave this as-is if everyone’s ok with the x86 diffs in D58521. Personally, I don’t think those tests with extra instructions are worth worrying about unless there’s some evidence of a perf regression from that.

Reading this again...is the suggestion to promote 8-bit ops to 32-bit like we do for 16-bit? I actually tried that somewhere along the way, and it seemed like a reasonable alternative based on the regression test diffs. That would at least make our lives easier in the compiler by allowing for removal of what would become unlikely/unnecessary patterns.

[RKSimon]

TBH I'm more worried about the failure of those PINSRBs to fold the loads

[craig.topper]

The fast-isel loads don't fold because we run the argument lowering and the rest of the code through selectiondag separately during fast-isel. So selectiondag doesn't see them together to fold the load during isel. Then we can't fold them during peephole because there is an INSERT_SUBREG between the MOVB and the PINSRB and the memory folding code can't handle that. Prior to this patch we had a MOVB, followed by a MOVZX, then the PINSRB at the time of peephole. Peephole pass did merge the MOVB and the MOVZX, but MOVZX isn't a foldable load so we don't go any further to merge with the PINSRB.

[spatel]

Ping.

Thoughts on where this should go?

I tried a few experiments with promoting some 8-bit ops to 32-bit, but I don't see a way to do that in stages. I think what we should do is promote almost all of those to 32-bit (like we do for 16-bit) because there's very little upside in using 8-bit ops, but lots of downside (this would make our codegen more like gcc from what I can tell). But that change is going to expose lots of small regressions because we've come to expect the 8-bit patterns.

[RKSimon]

Should we just aim to remove X86ISD::PINSRW/PINSRB and use INSERT_VECTOR_ELT directly? https://bugs.llvm.org/show_bug.cgi?id=39956

llvm/lib/Target/X86/X86InstrSSE.td

def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
                    Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>;
 }
 
 let Predicates = [HasAVX, NoBWI] in
   defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
 let Constraints = "$src1 = $dst" in
   defm PINSRB  : SS41I_insert8<0x20, "pinsrb">;
 
+// PINSRB copies only the low byte of the 32-bit scalar operand, so remove an
+// unnecessary extension of that operand.
+let Predicates = [UseSSE41] in {
+  def : Pat<(X86pinsrb VR128:$src1, (i32 (anyext GR8:$src2)), imm:$src3),
+            (PINSRBrr VR128:$src1, (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
+                                         GR8:$src2, sub_8bit)), imm:$src3)>;
+}
+let Predicates = [HasAVX, NoBWI] in {
+  def : Pat<(X86pinsrb VR128:$src1, (i32 (anyext GR8:$src2)), imm:$src3),
+            (VPINSRBrr VR128:$src1, (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
+                                          GR8:$src2, sub_8bit)), imm:$src3)>;
+}
+
 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
   def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
       (ins VR128:$src1, GR32:$src2, u8imm:$src3),
       !if(Is2Addr,
         !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
         !strconcat(asm,
                    "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
       [(set VR128:$dst,

llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

; CHECK-NEXT:    ret{{[l|q]}}
   %res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)
   ret <8 x float> %res
 }
 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
 
 define <4 x i64> @test_mm256_insert_epi8(<4 x i64> %a0, i8 %a1) nounwind {
 ; X86-LABEL: test_mm256_insert_epi8:
 ; X86:       # %bb.0:
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm1
 ; X86-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_insert_epi8:
 ; X64:       # %bb.0:
-; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm1
+; X64-NEXT:    vpinsrb $4, %edi, %xmm0, %xmm1
 ; X64-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
 ; X64-NEXT:    retq
   %arg0 = bitcast <4 x i64> %a0 to <32 x i8>
   %res = insertelement <32 x i8> %arg0, i8 %a1, i32 4
   %bc = bitcast <32 x i8> %res to <4 x i64>
   ret <4 x i64> %bc
 }
 
; CHECK-NEXT:    ret{{[l|q]}}
   ret <8 x float> %res
 }
 declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone
 
 define <4 x i64> @test_mm256_set_epi8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31) nounwind {
 ; X86-LABEL: test_mm256_set_epi8:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    vmovd %ecx, %xmm0
+; X86-NEXT:    vmovd %eax, %xmm0
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    vmovd %ecx, %xmm1
+; X86-NEXT:    vmovd %eax, %xmm1
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $1, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $2, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $3, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $4, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $5, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $6, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $7, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $8, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $9, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $10, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $11, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $12, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $13, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $14, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $15, %eax, %xmm1, %xmm1
 ; X86-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_set_epi8:
 ; X64:       # %bb.0:
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %r10d
 ; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    vmovd %eax, %xmm0
-; X64-NEXT:    vpinsrb $1, %r10d, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
+; X64-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl %r9b, %eax
-; X64-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl %r8b, %eax
-; X64-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl %cl, %eax
-; X64-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl %dl, %eax
-; X64-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl %sil, %eax
-; X64-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl %dil, %eax
-; X64-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
+; X64-NEXT:    vpinsrb $10, %r9d, %xmm0, %xmm0
+; X64-NEXT:    vpinsrb $11, %r8d, %xmm0, %xmm0
+; X64-NEXT:    vpinsrb $12, %ecx, %xmm0, %xmm0
+; X64-NEXT:    vpinsrb $13, %edx, %xmm0, %xmm0
+; X64-NEXT:    vpinsrb $14, %esi, %xmm0, %xmm0
+; X64-NEXT:    vpinsrb $15, %edi, %xmm0, %xmm0
 ; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %ecx
-; X64-NEXT:    vmovd %ecx, %xmm1
+; X64-NEXT:    vmovd %eax, %xmm1
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $1, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $2, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $3, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $4, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $5, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $6, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $7, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $8, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $9, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $10, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $11, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $12, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $13, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $14, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $15, %eax, %xmm1, %xmm1
 ; X64-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; X64-NEXT:    retq
   %res0  = insertelement <32 x i8> undef,  i8 %a31, i32 0
   %res1  = insertelement <32 x i8> %res0,  i8 %a30, i32 1
   %res2  = insertelement <32 x i8> %res1,  i8 %a29, i32 2
   %res3  = insertelement <32 x i8> %res2,  i8 %a28, i32 3
   %res4  = insertelement <32 x i8> %res3,  i8 %a27, i32 4
; X64-NEXT:    retq
   %res7 = insertelement <8 x float> %res6, float %a0, i32 7
   ret <8 x float> %res7
 }
 
 define <4 x i64> @test_mm256_setr_epi8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31) nounwind {
 ; X86-LABEL: test_mm256_setr_epi8:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    vmovd %ecx, %xmm0
+; X86-NEXT:    vmovd %eax, %xmm0
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    vmovd %ecx, %xmm1
+; X86-NEXT:    vmovd %eax, %xmm1
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $1, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $2, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $3, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $4, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $5, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $6, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $7, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $8, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $9, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $10, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $11, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $12, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $13, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $14, %eax, %xmm1, %xmm1
-; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-NEXT:    vpinsrb $15, %eax, %xmm1, %xmm1
 ; X86-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_setr_epi8:
 ; X64:       # %bb.0:
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %r10d
 ; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
 ; X64-NEXT:    vmovd %eax, %xmm0
-; X64-NEXT:    vpinsrb $1, %r10d, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
+; X64-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0
-; X64-NEXT:    movzbl %sil, %eax
-; X64-NEXT:    movzbl %dil, %esi
-; X64-NEXT:    vmovd %esi, %xmm1
-; X64-NEXT:    vpinsrb $1, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl %dl, %eax
-; X64-NEXT:    vpinsrb $2, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl %cl, %eax
-; X64-NEXT:    vpinsrb $3, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl %r8b, %eax
-; X64-NEXT:    vpinsrb $4, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl %r9b, %eax
-; X64-NEXT:    vpinsrb $5, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movzbl %dil, %eax
+; X64-NEXT:    vmovd %eax, %xmm1
+; X64-NEXT:    vpinsrb $1, %esi, %xmm1, %xmm1
+; X64-NEXT:    vpinsrb $2, %edx, %xmm1, %xmm1
+; X64-NEXT:    vpinsrb $3, %ecx, %xmm1, %xmm1
+; X64-NEXT:    vpinsrb $4, %r8d, %xmm1, %xmm1
+; X64-NEXT:    vpinsrb $5, %r9d, %xmm1, %xmm1
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $6, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $7, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $8, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $9, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $10, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $11, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $12, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $13, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $14, %eax, %xmm1, %xmm1
-; X64-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax
+; X64-NEXT:    movb {{[0-9]+}}(%rsp), %al
 ; X64-NEXT:    vpinsrb $15, %eax, %xmm1, %xmm1
 ; X64-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; X64-NEXT:    retq
   %res0  = insertelement <32 x i8> undef,  i8 %a0 , i32 0
   %res1  = insertelement <32 x i8> %res0,  i8 %a1 , i32 1
   %res2  = insertelement <32 x i8> %res1,  i8 %a2 , i32 2
   %res3  = insertelement <32 x i8> %res2,  i8 %a3 , i32 3
   %res4  = insertelement <32 x i8> %res3,  i8 %a4 , i32 4

llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll

 ; X86-SSE-NEXT:    punpckldq %xmm3, %xmm0 # encoding: [0x66,0x0f,0x62,0xc3]
 ; X86-SSE-NEXT:    # xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
 ; X86-SSE-NEXT:    punpcklqdq %xmm1, %xmm0 # encoding: [0x66,0x0f,0x6c,0xc1]
 ; X86-SSE-NEXT:    # xmm0 = xmm0[0],xmm1[0]
 ; X86-SSE-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX1-LABEL: test_mm_set_epi8:
 ; X86-AVX1:       # %bb.0:
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x3c]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx # encoding: [0x0f,0xb6,0x4c,0x24,0x40]
-; X86-AVX1-NEXT:    vmovd %ecx, %xmm0 # encoding: [0xc5,0xf9,0x6e,0xc1]
+; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x40]
+; X86-AVX1-NEXT:    vmovd %eax, %xmm0 # encoding: [0xc5,0xf9,0x6e,0xc0]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x3c]
 ; X86-AVX1-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x01]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x38]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x38]
 ; X86-AVX1-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x02]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x34]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x34]
 ; X86-AVX1-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x03]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x30]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x30]
 ; X86-AVX1-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x04]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x2c]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x2c]
 ; X86-AVX1-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x05]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x28]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x28]
 ; X86-AVX1-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x06]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x24]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x24]
 ; X86-AVX1-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x07]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x20]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x20]
 ; X86-AVX1-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x08]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x1c]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x1c]
 ; X86-AVX1-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x09]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x18]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x18]
 ; X86-AVX1-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0a]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x14]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x14]
 ; X86-AVX1-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0b]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x10]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x10]
 ; X86-AVX1-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0c]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x0c]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x0c]
 ; X86-AVX1-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0d]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x08]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x08]
 ; X86-AVX1-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0e]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x04]
 ; X86-AVX1-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0f]
 ; X86-AVX1-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX512-LABEL: test_mm_set_epi8:
 ; X86-AVX512:       # %bb.0:
 ; X86-AVX512-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x3c]
 ; X86-AVX512-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx # encoding: [0x0f,0xb6,0x4c,0x24,0x40]
 ; X86-AVX512-NEXT:    vmovd %ecx, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc1]

 ; X64-SSE-NEXT:    punpckldq %xmm3, %xmm0 # encoding: [0x66,0x0f,0x62,0xc3]
 ; X64-SSE-NEXT:    # xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
 ; X64-SSE-NEXT:    punpcklqdq %xmm1, %xmm0 # encoding: [0x66,0x0f,0x6c,0xc1]
 ; X64-SSE-NEXT:    # xmm0 = xmm0[0],xmm1[0]
 ; X64-SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; X64-AVX1-LABEL: test_mm_set_epi8:
 ; X64-AVX1:       # %bb.0:
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %r10d # encoding: [0x44,0x0f,0xb6,0x54,0x24,0x48]
 ; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x50]
 ; X64-AVX1-NEXT:    vmovd %eax, %xmm0 # encoding: [0xc5,0xf9,0x6e,0xc0]
-; X64-AVX1-NEXT:    vpinsrb $1, %r10d, %xmm0, %xmm0 # encoding: [0xc4,0xc3,0x79,0x20,0xc2,0x01]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x40]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x48]
+; X64-AVX1-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x01]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x40]
 ; X64-AVX1-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x02]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x38]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x38]
 ; X64-AVX1-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x03]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x30]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x30]
 ; X64-AVX1-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x04]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x28]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x28]
 ; X64-AVX1-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x05]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x20]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x20]
 ; X64-AVX1-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x06]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x18]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x18]
 ; X64-AVX1-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x07]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x10]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x10]
 ; X64-AVX1-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x08]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x08]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x08]
 ; X64-AVX1-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x09]
-; X64-AVX1-NEXT:    movzbl %r9b, %eax # encoding: [0x41,0x0f,0xb6,0xc1]
-; X64-AVX1-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0a]
-; X64-AVX1-NEXT:    movzbl %r8b, %eax # encoding: [0x41,0x0f,0xb6,0xc0]
-; X64-AVX1-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0b]
-; X64-AVX1-NEXT:    movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
-; X64-AVX1-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0c]
-; X64-AVX1-NEXT:    movzbl %dl, %eax # encoding: [0x0f,0xb6,0xc2]
-; X64-AVX1-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0d]
-; X64-AVX1-NEXT:    movzbl %sil, %eax # encoding: [0x40,0x0f,0xb6,0xc6]
-; X64-AVX1-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0e]
-; X64-AVX1-NEXT:    movzbl %dil, %eax # encoding: [0x40,0x0f,0xb6,0xc7]
-; X64-AVX1-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0f]
+; X64-AVX1-NEXT:    vpinsrb $10, %r9d, %xmm0, %xmm0 # encoding: [0xc4,0xc3,0x79,0x20,0xc1,0x0a]
+; X64-AVX1-NEXT:    vpinsrb $11, %r8d, %xmm0, %xmm0 # encoding: [0xc4,0xc3,0x79,0x20,0xc0,0x0b]
+; X64-AVX1-NEXT:    vpinsrb $12, %ecx, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc1,0x0c]
+; X64-AVX1-NEXT:    vpinsrb $13, %edx, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc2,0x0d]
+; X64-AVX1-NEXT:    vpinsrb $14, %esi, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc6,0x0e]
+; X64-AVX1-NEXT:    vpinsrb $15, %edi, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc7,0x0f]
 ; X64-AVX1-NEXT:    retq # encoding: [0xc3]
 ;
 ; X64-AVX512-LABEL: test_mm_set_epi8:
 ; X64-AVX512:       # %bb.0:
 ; X64-AVX512-NEXT:    movzbl {{[0-9]+}}(%rsp), %r10d # encoding: [0x44,0x0f,0xb6,0x54,0x24,0x48]
 ; X64-AVX512-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x50]
 ; X64-AVX512-NEXT:    vmovd %eax, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc0]
 ; X64-AVX512-NEXT:    vpinsrb $1, %r10d, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xc3,0x79,0x20,0xc2,0x01]

 ; X86-SSE-NEXT:    punpckldq %xmm3, %xmm0 # encoding: [0x66,0x0f,0x62,0xc3]
 ; X86-SSE-NEXT:    # xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
 ; X86-SSE-NEXT:    punpcklqdq %xmm1, %xmm0 # encoding: [0x66,0x0f,0x6c,0xc1]
 ; X86-SSE-NEXT:    # xmm0 = xmm0[0],xmm1[0]
 ; X86-SSE-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX1-LABEL: test_mm_setr_epi8:
 ; X86-AVX1:       # %bb.0:
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x08]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx # encoding: [0x0f,0xb6,0x4c,0x24,0x04]
-; X86-AVX1-NEXT:    vmovd %ecx, %xmm0 # encoding: [0xc5,0xf9,0x6e,0xc1]
+; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
+; X86-AVX1-NEXT:    vmovd %eax, %xmm0 # encoding: [0xc5,0xf9,0x6e,0xc0]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x08]
 ; X86-AVX1-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x01]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x0c]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x0c]
 ; X86-AVX1-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x02]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x10]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x10]
 ; X86-AVX1-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x03]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x14]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x14]
 ; X86-AVX1-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x04]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x18]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x18]
 ; X86-AVX1-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x05]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x1c]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x1c]
 ; X86-AVX1-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x06]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x20]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x20]
 ; X86-AVX1-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x07]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x24]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x24]
 ; X86-AVX1-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x08]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x28]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x28]
 ; X86-AVX1-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x09]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x2c]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x2c]
 ; X86-AVX1-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0a]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x30]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x30]
 ; X86-AVX1-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0b]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x34]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x34]
 ; X86-AVX1-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0c]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x38]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x38]
 ; X86-AVX1-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0d]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x3c]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x3c]
 ; X86-AVX1-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0e]
-; X86-AVX1-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x40]
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al # encoding: [0x8a,0x44,0x24,0x40]
 ; X86-AVX1-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0f]
 ; X86-AVX1-NEXT:    retl # encoding: [0xc3]
 ;
 ; X86-AVX512-LABEL: test_mm_setr_epi8:
 ; X86-AVX512:       # %bb.0:
 ; X86-AVX512-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x08]
 ; X86-AVX512-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx # encoding: [0x0f,0xb6,0x4c,0x24,0x04]
 ; X86-AVX512-NEXT:    vmovd %ecx, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc1]

 ; X64-SSE-NEXT:    punpckldq %xmm3, %xmm0 # encoding: [0x66,0x0f,0x62,0xc3]
 ; X64-SSE-NEXT:    # xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
 ; X64-SSE-NEXT:    punpcklqdq %xmm1, %xmm0 # encoding: [0x66,0x0f,0x6c,0xc1]
 ; X64-SSE-NEXT:    # xmm0 = xmm0[0],xmm1[0]
 ; X64-SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; X64-AVX1-LABEL: test_mm_setr_epi8:
 ; X64-AVX1:       # %bb.0:
-; X64-AVX1-NEXT:    movzbl %sil, %eax # encoding: [0x40,0x0f,0xb6,0xc6]
-; X64-AVX1-NEXT:    movzbl %dil, %esi # encoding: [0x40,0x0f,0xb6,0xf7]
-; X64-AVX1-NEXT:    vmovd %esi, %xmm0 # encoding: [0xc5,0xf9,0x6e,0xc6]
-; X64-AVX1-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x01]
-; X64-AVX1-NEXT:    movzbl %dl, %eax # encoding: [0x0f,0xb6,0xc2]
-; X64-AVX1-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x02]
-; X64-AVX1-NEXT:    movzbl %cl, %eax # encoding: [0x0f,0xb6,0xc1]
-; X64-AVX1-NEXT:    vpinsrb $3, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x03]
-; X64-AVX1-NEXT:    movzbl %r8b, %eax # encoding: [0x41,0x0f,0xb6,0xc0]
-; X64-AVX1-NEXT:    vpinsrb $4, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x04]
-; X64-AVX1-NEXT:    movzbl %r9b, %eax # encoding: [0x41,0x0f,0xb6,0xc1]
-; X64-AVX1-NEXT:    vpinsrb $5, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x05]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x08]
+; X64-AVX1-NEXT:    movzbl %dil, %eax # encoding: [0x40,0x0f,0xb6,0xc7]
+; X64-AVX1-NEXT:    vmovd %eax, %xmm0 # encoding: [0xc5,0xf9,0x6e,0xc0]
+; X64-AVX1-NEXT:    vpinsrb $1, %esi, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc6,0x01]
+; X64-AVX1-NEXT:    vpinsrb $2, %edx, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc2,0x02]
+; X64-AVX1-NEXT:    vpinsrb $3, %ecx, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc1,0x03]
+; X64-AVX1-NEXT:    vpinsrb $4, %r8d, %xmm0, %xmm0 # encoding: [0xc4,0xc3,0x79,0x20,0xc0,0x04]
+; X64-AVX1-NEXT:    vpinsrb $5, %r9d, %xmm0, %xmm0 # encoding: [0xc4,0xc3,0x79,0x20,0xc1,0x05]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x08]
 ; X64-AVX1-NEXT:    vpinsrb $6, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x06]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x10]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x10]
 ; X64-AVX1-NEXT:    vpinsrb $7, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x07]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x18]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x18]
 ; X64-AVX1-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x08]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x20]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x20]
 ; X64-AVX1-NEXT:    vpinsrb $9, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x09]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x28]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x28]
 ; X64-AVX1-NEXT:    vpinsrb $10, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0a]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x30]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x30]
 ; X64-AVX1-NEXT:    vpinsrb $11, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0b]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x38]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x38]
 ; X64-AVX1-NEXT:    vpinsrb $12, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0c]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x40]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x40]
 ; X64-AVX1-NEXT:    vpinsrb $13, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0d]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x48]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x48]
 ; X64-AVX1-NEXT:    vpinsrb $14, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0e]
-; X64-AVX1-NEXT:    movzbl {{[0-9]+}}(%rsp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x50]
+; X64-AVX1-NEXT:    movb {{[0-9]+}}(%rsp), %al # encoding: [0x8a,0x44,0x24,0x50]
 ; X64-AVX1-NEXT:    vpinsrb $15, %eax, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x20,0xc0,0x0f]
 ; X64-AVX1-NEXT:    retq # encoding: [0xc3]
 ;
 ; X64-AVX512-LABEL: test_mm_setr_epi8:
 ; X64-AVX512:       # %bb.0:
 ; X64-AVX512-NEXT:    movzbl %sil, %eax # encoding: [0x40,0x0f,0xb6,0xc6]
 ; X64-AVX512-NEXT:    movzbl %dil, %esi # encoding: [0x40,0x0f,0xb6,0xf7]
 ; X64-AVX512-NEXT:    vmovd %esi, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc6]

llvm/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll

 ; AVX-NEXT:    ret{{[l|q]}}
   %res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1, i32 1)
   ret <4 x float> %res
 }
 
 define <2 x i64> @test_mm_insert_epi8(<2 x i64> %a0, i8 %a1) {
 ; X86-SSE-LABEL: test_mm_insert_epi8:
 ; X86-SSE:       # %bb.0:
-; X86-SSE-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X86-SSE-NEXT:    pinsrb $1, %eax, %xmm0
 ; X86-SSE-NEXT:    retl
 ;
-; X86-AVX-LABEL: test_mm_insert_epi8:
-; X86-AVX:       # %bb.0:
-; X86-AVX-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
-; X86-AVX-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
-; X86-AVX-NEXT:    retl
+; X86-AVX1-LABEL: test_mm_insert_epi8:
+; X86-AVX1:       # %bb.0:
+; X86-AVX1-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-AVX1-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
+; X86-AVX1-NEXT:    retl
+;
+; X86-AVX512-LABEL: test_mm_insert_epi8:
+; X86-AVX512:       # %bb.0:
+; X86-AVX512-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X86-AVX512-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
+; X86-AVX512-NEXT:    retl
 ;
 ; X64-SSE-LABEL: test_mm_insert_epi8:
 ; X64-SSE:       # %bb.0:
-; X64-SSE-NEXT:    movzbl %dil, %eax
-; X64-SSE-NEXT:    pinsrb $1, %eax, %xmm0
+; X64-SSE-NEXT:    pinsrb $1, %edi, %xmm0
 ; X64-SSE-NEXT:    retq
 ;
-; X64-AVX-LABEL: test_mm_insert_epi8:
-; X64-AVX:       # %bb.0:
-; X64-AVX-NEXT:    movzbl %dil, %eax
-; X64-AVX-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
-; X64-AVX-NEXT:    retq
+; X64-AVX1-LABEL: test_mm_insert_epi8:
+; X64-AVX1:       # %bb.0:
+; X64-AVX1-NEXT:    vpinsrb $1, %edi, %xmm0, %xmm0
+; X64-AVX1-NEXT:    retq
+;
+; X64-AVX512-LABEL: test_mm_insert_epi8:
+; X64-AVX512:       # %bb.0:
+; X64-AVX512-NEXT:    movzbl %dil, %eax
+; X64-AVX512-NEXT:    vpinsrb $1, %eax, %xmm0, %xmm0
+; X64-AVX512-NEXT:    retq
   %arg0 = bitcast <2 x i64> %a0 to <16 x i8>
   %res = insertelement <16 x i8> %arg0, i8 %a1,i32 1
   %bc = bitcast <16 x i8> %res to <2 x i64>
   ret <2 x i64> %bc
 }
 
 define <2 x i64> @test_mm_insert_epi32(<2 x i64> %a0, i32 %a1) {
 ; X86-SSE-LABEL: test_mm_insert_epi32:

llvm/test/CodeGen/X86/vec_saddo.ll

 ;
 ; SSE41-LABEL: saddo_v2i128:
 ; SSE41:       # %bb.0:
 ; SSE41-NEXT:    pushq %rbp
 ; SSE41-NEXT:    pushq %rbx
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r11
 ; SSE41-NEXT:    addq {{[0-9]+}}(%rsp), %rdx
-; SSE41-NEXT:    movq %rcx, %rax
-; SSE41-NEXT:    adcq %r11, %rax
+; SSE41-NEXT:    movq %rcx, %rbp
+; SSE41-NEXT:    adcq %r11, %rbp
 ; SSE41-NEXT:    setns %bl
 ; SSE41-NEXT:    testq %rcx, %rcx
 ; SSE41-NEXT:    setns %cl
 ; SSE41-NEXT:    cmpb %bl, %cl
-; SSE41-NEXT:    setne %bpl
+; SSE41-NEXT:    setne %al
 ; SSE41-NEXT:    testq %r11, %r11
 ; SSE41-NEXT:    setns %bl
 ; SSE41-NEXT:    cmpb %bl, %cl
 ; SSE41-NEXT:    sete %cl
-; SSE41-NEXT:    andb %bpl, %cl
-; SSE41-NEXT:    movzbl %cl, %ebp
+; SSE41-NEXT:    andb %al, %cl
 ; SSE41-NEXT:    testq %r9, %r9
 ; SSE41-NEXT:    setns %bl
 ; SSE41-NEXT:    testq %rsi, %rsi
-; SSE41-NEXT:    setns %cl
-; SSE41-NEXT:    cmpb %bl, %cl
+; SSE41-NEXT:    setns %al
+; SSE41-NEXT:    cmpb %bl, %al
 ; SSE41-NEXT:    sete %r11b
 ; SSE41-NEXT:    addq %r8, %rdi
 ; SSE41-NEXT:    adcq %r9, %rsi
 ; SSE41-NEXT:    setns %bl
-; SSE41-NEXT:    cmpb %bl, %cl
-; SSE41-NEXT:    setne %cl
-; SSE41-NEXT:    andb %r11b, %cl
-; SSE41-NEXT:    movzbl %cl, %ecx
-; SSE41-NEXT:    movd %ecx, %xmm0
-; SSE41-NEXT:    pinsrb $8, %ebp, %xmm0
+; SSE41-NEXT:    cmpb %bl, %al
+; SSE41-NEXT:    setne %al
+; SSE41-NEXT:    andb %r11b, %al
+; SSE41-NEXT:    movzbl %al, %eax
+; SSE41-NEXT:    movd %eax, %xmm0
+; SSE41-NEXT:    pinsrb $8, %ecx, %xmm0
 ; SSE41-NEXT:    movq %rdx, 16(%r10)
 ; SSE41-NEXT:    movq %rdi, (%r10)
-; SSE41-NEXT:    movq %rax, 24(%r10)
+; SSE41-NEXT:    movq %rbp, 24(%r10)
 ; SSE41-NEXT:    movq %rsi, 8(%r10)
 ; SSE41-NEXT:    psllq $63, %xmm0
 ; SSE41-NEXT:    psrad $31, %xmm0
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    popq %rbx
 ; SSE41-NEXT:    popq %rbp
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: saddo_v2i128:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    pushq %rbp
 ; AVX1-NEXT:    pushq %rbx
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r11
 ; AVX1-NEXT:    addq {{[0-9]+}}(%rsp), %rdx
-; AVX1-NEXT:    movq %rcx, %rax
-; AVX1-NEXT:    adcq %r11, %rax
+; AVX1-NEXT:    movq %rcx, %rbp
+; AVX1-NEXT:    adcq %r11, %rbp
 ; AVX1-NEXT:    setns %bl
 ; AVX1-NEXT:    testq %rcx, %rcx
 ; AVX1-NEXT:    setns %cl
 ; AVX1-NEXT:    cmpb %bl, %cl
-; AVX1-NEXT:    setne %bpl
+; AVX1-NEXT:    setne %al
 ; AVX1-NEXT:    testq %r11, %r11
 ; AVX1-NEXT:    setns %bl
 ; AVX1-NEXT:    cmpb %bl, %cl
 ; AVX1-NEXT:    sete %cl
-; AVX1-NEXT:    andb %bpl, %cl
-; AVX1-NEXT:    movzbl %cl, %ebp
+; AVX1-NEXT:    andb %al, %cl
 ; AVX1-NEXT:    testq %r9, %r9
 ; AVX1-NEXT:    setns %bl
 ; AVX1-NEXT:    testq %rsi, %rsi
-; AVX1-NEXT:    setns %cl
-; AVX1-NEXT:    cmpb %bl, %cl
+; AVX1-NEXT:    setns %al
+; AVX1-NEXT:    cmpb %bl, %al
 ; AVX1-NEXT:    sete %r11b
 ; AVX1-NEXT:    addq %r8, %rdi
 ; AVX1-NEXT:    adcq %r9, %rsi
 ; AVX1-NEXT:    setns %bl
-; AVX1-NEXT:    cmpb %bl, %cl
-; AVX1-NEXT:    setne %cl
-; AVX1-NEXT:    andb %r11b, %cl
-; AVX1-NEXT:    movzbl %cl, %ecx
-; AVX1-NEXT:    vmovd %ecx, %xmm0
-; AVX1-NEXT:    vpinsrb $8, %ebp, %xmm0, %xmm0
+; AVX1-NEXT:    cmpb %bl, %al
+; AVX1-NEXT:    setne %al
+; AVX1-NEXT:    andb %r11b, %al
+; AVX1-NEXT:    movzbl %al, %eax
+; AVX1-NEXT:    vmovd %eax, %xmm0
+; AVX1-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
 ; AVX1-NEXT:    movq %rdx, 16(%r10)
 ; AVX1-NEXT:    movq %rdi, (%r10)
-; AVX1-NEXT:    movq %rax, 24(%r10)
+; AVX1-NEXT:    movq %rbp, 24(%r10)
 ; AVX1-NEXT:    movq %rsi, 8(%r10)
 ; AVX1-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    popq %rbx
 ; AVX1-NEXT:    popq %rbp
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: saddo_v2i128:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    pushq %rbp
 ; AVX2-NEXT:    pushq %rbx
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r11
 ; AVX2-NEXT:    addq {{[0-9]+}}(%rsp), %rdx
-; AVX2-NEXT:    movq %rcx, %rax
-; AVX2-NEXT:    adcq %r11, %rax
+; AVX2-NEXT:    movq %rcx, %rbp
+; AVX2-NEXT:    adcq %r11, %rbp
 ; AVX2-NEXT:    setns %bl
 ; AVX2-NEXT:    testq %rcx, %rcx
 ; AVX2-NEXT:    setns %cl
 ; AVX2-NEXT:    cmpb %bl, %cl
-; AVX2-NEXT:    setne %bpl
+; AVX2-NEXT:    setne %al
 ; AVX2-NEXT:    testq %r11, %r11
 ; AVX2-NEXT:    setns %bl
 ; AVX2-NEXT:    cmpb %bl, %cl
 ; AVX2-NEXT:    sete %cl
-; AVX2-NEXT:    andb %bpl, %cl
-; AVX2-NEXT:    movzbl %cl, %ebp
+; AVX2-NEXT:    andb %al, %cl
 ; AVX2-NEXT:    testq %r9, %r9
 ; AVX2-NEXT:    setns %bl
 ; AVX2-NEXT:    testq %rsi, %rsi
-; AVX2-NEXT:    setns %cl
-; AVX2-NEXT:    cmpb %bl, %cl
+; AVX2-NEXT:    setns %al
+; AVX2-NEXT:    cmpb %bl, %al
 ; AVX2-NEXT:    sete %r11b
 ; AVX2-NEXT:    addq %r8, %rdi
 ; AVX2-NEXT:    adcq %r9, %rsi
 ; AVX2-NEXT:    setns %bl
-; AVX2-NEXT:    cmpb %bl, %cl
-; AVX2-NEXT:    setne %cl
-; AVX2-NEXT:    andb %r11b, %cl
-; AVX2-NEXT:    movzbl %cl, %ecx
-; AVX2-NEXT:    vmovd %ecx, %xmm0
-; AVX2-NEXT:    vpinsrb $8, %ebp, %xmm0, %xmm0
+; AVX2-NEXT:    cmpb %bl, %al
+; AVX2-NEXT:    setne %al
+; AVX2-NEXT:    andb %r11b, %al
+; AVX2-NEXT:    movzbl %al, %eax
+; AVX2-NEXT:    vmovd %eax, %xmm0
+; AVX2-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
 ; AVX2-NEXT:    movq %rdx, 16(%r10)
 ; AVX2-NEXT:    movq %rdi, (%r10)
-; AVX2-NEXT:    movq %rax, 24(%r10)
+; AVX2-NEXT:    movq %rbp, 24(%r10)
 ; AVX2-NEXT:    movq %rsi, 8(%r10)
 ; AVX2-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX2-NEXT:    popq %rbx
 ; AVX2-NEXT:    popq %rbp
 ; AVX2-NEXT:    retq
 ;

llvm/test/CodeGen/X86/vec_smulo.ll

 ; SSE41-NEXT:    movq %rdx, %rbp
 ; SSE41-NEXT:    movq $0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    leaq {{[0-9]+}}(%rsp), %r8
 ; SSE41-NEXT:    movq %rbx, %rdi
 ; SSE41-NEXT:    movq %r14, %rsi
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
 ; SSE41-NEXT:    movq %r12, %rcx
 ; SSE41-NEXT:    callq __muloti4
-; SSE41-NEXT:    xorl %ecx, %ecx
 ; SSE41-NEXT:    cmpq $0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    setne %cl
 ; SSE41-NEXT:    xorl %esi, %esi
 ; SSE41-NEXT:    cmpq $0, {{[0-9]+}}(%rsp)
 ; SSE41-NEXT:    setne %sil
 ; SSE41-NEXT:    movd %esi, %xmm0
 ; SSE41-NEXT:    pinsrb $8, %ecx, %xmm0
 ; SSE41-NEXT:    movq %rdx, 24(%r15)

 ; AVX1-NEXT:    movq %rdx, %rbp
 ; AVX1-NEXT:    movq $0, {{[0-9]+}}(%rsp)
 ; AVX1-NEXT:    leaq {{[0-9]+}}(%rsp), %r8
 ; AVX1-NEXT:    movq %rbx, %rdi
 ; AVX1-NEXT:    movq %r14, %rsi
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
 ; AVX1-NEXT:    movq %r12, %rcx
 ; AVX1-NEXT:    callq __muloti4
-; AVX1-NEXT:    xorl %ecx, %ecx
 ; AVX1-NEXT:    cmpq $0, {{[0-9]+}}(%rsp)
 ; AVX1-NEXT:    setne %cl
 ; AVX1-NEXT:    xorl %esi, %esi
 ; AVX1-NEXT:    cmpq $0, {{[0-9]+}}(%rsp)
 ; AVX1-NEXT:    setne %sil
 ; AVX1-NEXT:    vmovd %esi, %xmm0
 ; AVX1-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
 ; AVX1-NEXT:    movq %rdx, 24(%r15)

 ; AVX2-NEXT:    movq %rdx, %rbp
 ; AVX2-NEXT:    movq $0, {{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    leaq {{[0-9]+}}(%rsp), %r8
 ; AVX2-NEXT:    movq %rbx, %rdi
 ; AVX2-NEXT:    movq %r14, %rsi
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
 ; AVX2-NEXT:    movq %r12, %rcx
 ; AVX2-NEXT:    callq __muloti4
-; AVX2-NEXT:    xorl %ecx, %ecx
 ; AVX2-NEXT:    cmpq $0, {{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    setne %cl
 ; AVX2-NEXT:    xorl %esi, %esi
 ; AVX2-NEXT:    cmpq $0, {{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    setne %sil
 ; AVX2-NEXT:    vmovd %esi, %xmm0
 ; AVX2-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
 ; AVX2-NEXT:    movq %rdx, 24(%r15)

llvm/test/CodeGen/X86/vec_ssubo.ll

 ;
 ; SSE41-LABEL: ssubo_v2i128:
 ; SSE41:       # %bb.0:
 ; SSE41-NEXT:    pushq %rbp
 ; SSE41-NEXT:    pushq %rbx
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r11
 ; SSE41-NEXT:    subq {{[0-9]+}}(%rsp), %rdx
-; SSE41-NEXT:    movq %rcx, %rax
-; SSE41-NEXT:    sbbq %r11, %rax
+; SSE41-NEXT:    movq %rcx, %rbp
+; SSE41-NEXT:    sbbq %r11, %rbp
 ; SSE41-NEXT:    setns %bl
 ; SSE41-NEXT:    testq %rcx, %rcx
 ; SSE41-NEXT:    setns %cl
 ; SSE41-NEXT:    cmpb %bl, %cl
-; SSE41-NEXT:    setne %bpl
+; SSE41-NEXT:    setne %al
 ; SSE41-NEXT:    testq %r11, %r11
 ; SSE41-NEXT:    setns %bl
 ; SSE41-NEXT:    cmpb %bl, %cl
 ; SSE41-NEXT:    setne %cl
-; SSE41-NEXT:    andb %bpl, %cl
-; SSE41-NEXT:    movzbl %cl, %ebp
+; SSE41-NEXT:    andb %al, %cl
 ; SSE41-NEXT:    testq %r9, %r9
 ; SSE41-NEXT:    setns %bl
 ; SSE41-NEXT:    testq %rsi, %rsi
-; SSE41-NEXT:    setns %cl
-; SSE41-NEXT:    cmpb %bl, %cl
+; SSE41-NEXT:    setns %al
+; SSE41-NEXT:    cmpb %bl, %al
 ; SSE41-NEXT:    setne %r11b
 ; SSE41-NEXT:    subq %r8, %rdi
 ; SSE41-NEXT:    sbbq %r9, %rsi
 ; SSE41-NEXT:    setns %bl
-; SSE41-NEXT:    cmpb %bl, %cl
-; SSE41-NEXT:    setne %cl
-; SSE41-NEXT:    andb %r11b, %cl
-; SSE41-NEXT:    movzbl %cl, %ecx
-; SSE41-NEXT:    movd %ecx, %xmm0
-; SSE41-NEXT:    pinsrb $8, %ebp, %xmm0
+; SSE41-NEXT:    cmpb %bl, %al
+; SSE41-NEXT:    setne %al
+; SSE41-NEXT:    andb %r11b, %al
+; SSE41-NEXT:    movzbl %al, %eax
+; SSE41-NEXT:    movd %eax, %xmm0
+; SSE41-NEXT:    pinsrb $8, %ecx, %xmm0
 ; SSE41-NEXT:    movq %rdx, 16(%r10)
 ; SSE41-NEXT:    movq %rdi, (%r10)
-; SSE41-NEXT:    movq %rax, 24(%r10)
+; SSE41-NEXT:    movq %rbp, 24(%r10)
 ; SSE41-NEXT:    movq %rsi, 8(%r10)
 ; SSE41-NEXT:    psllq $63, %xmm0
 ; SSE41-NEXT:    psrad $31, %xmm0
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    popq %rbx
 ; SSE41-NEXT:    popq %rbp
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: ssubo_v2i128:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    pushq %rbp
 ; AVX1-NEXT:    pushq %rbx
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r11
 ; AVX1-NEXT:    subq {{[0-9]+}}(%rsp), %rdx
-; AVX1-NEXT:    movq %rcx, %rax
-; AVX1-NEXT:    sbbq %r11, %rax
+; AVX1-NEXT:    movq %rcx, %rbp
+; AVX1-NEXT:    sbbq %r11, %rbp
 ; AVX1-NEXT:    setns %bl
 ; AVX1-NEXT:    testq %rcx, %rcx
 ; AVX1-NEXT:    setns %cl
 ; AVX1-NEXT:    cmpb %bl, %cl
-; AVX1-NEXT:    setne %bpl
+; AVX1-NEXT:    setne %al
 ; AVX1-NEXT:    testq %r11, %r11
 ; AVX1-NEXT:    setns %bl
 ; AVX1-NEXT:    cmpb %bl, %cl
 ; AVX1-NEXT:    setne %cl
-; AVX1-NEXT:    andb %bpl, %cl
-; AVX1-NEXT:    movzbl %cl, %ebp
+; AVX1-NEXT:    andb %al, %cl
 ; AVX1-NEXT:    testq %r9, %r9
 ; AVX1-NEXT:    setns %bl
 ; AVX1-NEXT:    testq %rsi, %rsi
-; AVX1-NEXT:    setns %cl
-; AVX1-NEXT:    cmpb %bl, %cl
+; AVX1-NEXT:    setns %al
+; AVX1-NEXT:    cmpb %bl, %al
 ; AVX1-NEXT:    setne %r11b
 ; AVX1-NEXT:    subq %r8, %rdi
 ; AVX1-NEXT:    sbbq %r9, %rsi
 ; AVX1-NEXT:    setns %bl
-; AVX1-NEXT:    cmpb %bl, %cl
-; AVX1-NEXT:    setne %cl
-; AVX1-NEXT:    andb %r11b, %cl
-; AVX1-NEXT:    movzbl %cl, %ecx
-; AVX1-NEXT:    vmovd %ecx, %xmm0
-; AVX1-NEXT:    vpinsrb $8, %ebp, %xmm0, %xmm0
+; AVX1-NEXT:    cmpb %bl, %al
+; AVX1-NEXT:    setne %al
+; AVX1-NEXT:    andb %r11b, %al
+; AVX1-NEXT:    movzbl %al, %eax
+; AVX1-NEXT:    vmovd %eax, %xmm0
+; AVX1-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
 ; AVX1-NEXT:    movq %rdx, 16(%r10)
 ; AVX1-NEXT:    movq %rdi, (%r10)
-; AVX1-NEXT:    movq %rax, 24(%r10)
+; AVX1-NEXT:    movq %rbp, 24(%r10)
 ; AVX1-NEXT:    movq %rsi, 8(%r10)
 ; AVX1-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    popq %rbx
 ; AVX1-NEXT:    popq %rbp
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: ssubo_v2i128:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    pushq %rbp
 ; AVX2-NEXT:    pushq %rbx
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r11
 ; AVX2-NEXT:    subq {{[0-9]+}}(%rsp), %rdx
-; AVX2-NEXT:    movq %rcx, %rax
-; AVX2-NEXT:    sbbq %r11, %rax
+; AVX2-NEXT:    movq %rcx, %rbp
+; AVX2-NEXT:    sbbq %r11, %rbp
 ; AVX2-NEXT:    setns %bl
 ; AVX2-NEXT:    testq %rcx, %rcx
 ; AVX2-NEXT:    setns %cl
 ; AVX2-NEXT:    cmpb %bl, %cl
-; AVX2-NEXT:    setne %bpl
+; AVX2-NEXT:    setne %al
 ; AVX2-NEXT:    testq %r11, %r11
 ; AVX2-NEXT:    setns %bl
 ; AVX2-NEXT:    cmpb %bl, %cl
 ; AVX2-NEXT:    setne %cl
-; AVX2-NEXT:    andb %bpl, %cl
-; AVX2-NEXT:    movzbl %cl, %ebp
+; AVX2-NEXT:    andb %al, %cl
 ; AVX2-NEXT:    testq %r9, %r9
 ; AVX2-NEXT:    setns %bl
 ; AVX2-NEXT:    testq %rsi, %rsi
-; AVX2-NEXT:    setns %cl
-; AVX2-NEXT:    cmpb %bl, %cl
+; AVX2-NEXT:    setns %al
+; AVX2-NEXT:    cmpb %bl, %al
 ; AVX2-NEXT:    setne %r11b
 ; AVX2-NEXT:    subq %r8, %rdi
 ; AVX2-NEXT:    sbbq %r9, %rsi
 ; AVX2-NEXT:    setns %bl
-; AVX2-NEXT:    cmpb %bl, %cl
-; AVX2-NEXT:    setne %cl
-; AVX2-NEXT:    andb %r11b, %cl
-; AVX2-NEXT:    movzbl %cl, %ecx
-; AVX2-NEXT:    vmovd %ecx, %xmm0
-; AVX2-NEXT:    vpinsrb $8, %ebp, %xmm0, %xmm0
+; AVX2-NEXT:    cmpb %bl, %al
+; AVX2-NEXT:    setne %al
+; AVX2-NEXT:    andb %r11b, %al
+; AVX2-NEXT:    movzbl %al, %eax
+; AVX2-NEXT:    vmovd %eax, %xmm0
+; AVX2-NEXT:    vpinsrb $8, %ecx, %xmm0, %xmm0
 ; AVX2-NEXT:    movq %rdx, 16(%r10)
 ; AVX2-NEXT:    movq %rdi, (%r10)
-; AVX2-NEXT:    movq %rax, 24(%r10)
+; AVX2-NEXT:    movq %rbp, 24(%r10)
 ; AVX2-NEXT:    movq %rsi, 8(%r10)
 ; AVX2-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX2-NEXT:    popq %rbx
 ; AVX2-NEXT:    popq %rbp
 ; AVX2-NEXT:    retq
 ;

llvm/test/CodeGen/X86/vec_uaddo.ll

 ; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: uaddo_v2i128:
 ; SSE41:       # %bb.0:
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; SSE41-NEXT:    addq {{[0-9]+}}(%rsp), %rdx
 ; SSE41-NEXT:    adcq {{[0-9]+}}(%rsp), %rcx
-; SSE41-NEXT:    setb %al
-; SSE41-NEXT:    movzbl %al, %r11d
+; SSE41-NEXT:    setb %r11b
 ; SSE41-NEXT:    addq %r8, %rdi
 ; SSE41-NEXT:    adcq %r9, %rsi
 ; SSE41-NEXT:    setb %al
 ; SSE41-NEXT:    movzbl %al, %eax
 ; SSE41-NEXT:    movd %eax, %xmm0
 ; SSE41-NEXT:    pinsrb $8, %r11d, %xmm0
 ; SSE41-NEXT:    movq %rdx, 16(%r10)
 ; SSE41-NEXT:    movq %rdi, (%r10)
 ; SSE41-NEXT:    movq %rcx, 24(%r10)
 ; SSE41-NEXT:    movq %rsi, 8(%r10)
 ; SSE41-NEXT:    psllq $63, %xmm0
 ; SSE41-NEXT:    psrad $31, %xmm0
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: uaddo_v2i128:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX1-NEXT:    addq {{[0-9]+}}(%rsp), %rdx
 ; AVX1-NEXT:    adcq {{[0-9]+}}(%rsp), %rcx
-; AVX1-NEXT:    setb %al
-; AVX1-NEXT:    movzbl %al, %r11d
+; AVX1-NEXT:    setb %r11b
 ; AVX1-NEXT:    addq %r8, %rdi
 ; AVX1-NEXT:    adcq %r9, %rsi
 ; AVX1-NEXT:    setb %al
 ; AVX1-NEXT:    movzbl %al, %eax
 ; AVX1-NEXT:    vmovd %eax, %xmm0
 ; AVX1-NEXT:    vpinsrb $8, %r11d, %xmm0, %xmm0
 ; AVX1-NEXT:    movq %rdx, 16(%r10)
 ; AVX1-NEXT:    movq %rdi, (%r10)
 ; AVX1-NEXT:    movq %rcx, 24(%r10)
 ; AVX1-NEXT:    movq %rsi, 8(%r10)
 ; AVX1-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: uaddo_v2i128:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX2-NEXT:    addq {{[0-9]+}}(%rsp), %rdx
 ; AVX2-NEXT:    adcq {{[0-9]+}}(%rsp), %rcx
-; AVX2-NEXT:    setb %al
-; AVX2-NEXT:    movzbl %al, %r11d
+; AVX2-NEXT:    setb %r11b
 ; AVX2-NEXT:    addq %r8, %rdi
 ; AVX2-NEXT:    adcq %r9, %rsi
 ; AVX2-NEXT:    setb %al
 ; AVX2-NEXT:    movzbl %al, %eax
 ; AVX2-NEXT:    vmovd %eax, %xmm0
 ; AVX2-NEXT:    vpinsrb $8, %r11d, %xmm0, %xmm0
 ; AVX2-NEXT:    movq %rdx, 16(%r10)
 ; AVX2-NEXT:    movq %rdi, (%r10)

llvm/test/CodeGen/X86/vec_umulo.ll

 ; SSE41-LABEL: umulo_v2i128:
 ; SSE41:       # %bb.0:
 ; SSE41-NEXT:    pushq %rbp
 ; SSE41-NEXT:    pushq %r15
 ; SSE41-NEXT:    pushq %r14
 ; SSE41-NEXT:    pushq %r13
 ; SSE41-NEXT:    pushq %r12
 ; SSE41-NEXT:    pushq %rbx
+; SSE41-NEXT:    movq %r8, %r14
 ; SSE41-NEXT:    movq %rcx, %rax
 ; SSE41-NEXT:    movq %rdx, %r12
+; SSE41-NEXT:    movq %rsi, %r8
 ; SSE41-NEXT:    movq %rdi, %r11
-; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r14
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r15
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; SSE41-NEXT:    testq %r10, %r10
 ; SSE41-NEXT:    setne %dl
 ; SSE41-NEXT:    testq %rcx, %rcx
 ; SSE41-NEXT:    setne %r13b
 ; SSE41-NEXT:    andb %dl, %r13b
 ; SSE41-NEXT:    mulq %r15
 ; SSE41-NEXT:    movq %rax, %rdi
 ; SSE41-NEXT:    seto %bpl
 ; SSE41-NEXT:    movq %r10, %rax
 ; SSE41-NEXT:    mulq %r12
 ; SSE41-NEXT:    movq %rax, %rbx
 ; SSE41-NEXT:    seto %cl
 ; SSE41-NEXT:    orb %bpl, %cl
 ; SSE41-NEXT:    addq %rdi, %rbx
 ; SSE41-NEXT:    movq %r12, %rax
 ; SSE41-NEXT:    mulq %r15
 ; SSE41-NEXT:    movq %rax, %r10
 ; SSE41-NEXT:    movq %rdx, %r15
 ; SSE41-NEXT:    addq %rbx, %r15
-; SSE41-NEXT:    setb %al
-; SSE41-NEXT:    orb %cl, %al
-; SSE41-NEXT:    orb %r13b, %al
-; SSE41-NEXT:    movzbl %al, %ebp
+; SSE41-NEXT:    setb %sil
+; SSE41-NEXT:    orb %cl, %sil
+; SSE41-NEXT:    orb %r13b, %sil
 ; SSE41-NEXT:    testq %r9, %r9
 ; SSE41-NEXT:    setne %al
-; SSE41-NEXT:    testq %rsi, %rsi
-; SSE41-NEXT:    setne %r13b
-; SSE41-NEXT:    andb %al, %r13b
-; SSE41-NEXT:    movq %rsi, %rax
-; SSE41-NEXT:    mulq %r8
-; SSE41-NEXT:    movq %rax, %rsi
-; SSE41-NEXT:    seto %r12b
+; SSE41-NEXT:    testq %r8, %r8
+; SSE41-NEXT:    setne %r12b
+; SSE41-NEXT:    andb %al, %r12b
+; SSE41-NEXT:    movq %r8, %rax
+; SSE41-NEXT:    mulq %r14
+; SSE41-NEXT:    movq %rax, %rbx
+; SSE41-NEXT:    seto %bpl
 ; SSE41-NEXT:    movq %r9, %rax
 ; SSE41-NEXT:    mulq %r11
 ; SSE41-NEXT:    movq %rax, %rdi
-; SSE41-NEXT:    seto %bl
-; SSE41-NEXT:    orb %r12b, %bl
-; SSE41-NEXT:    addq %rsi, %rdi
+; SSE41-NEXT:    seto %cl
+; SSE41-NEXT:    orb %bpl, %cl
+; SSE41-NEXT:    addq %rbx, %rdi
 ; SSE41-NEXT:    movq %r11, %rax
-; SSE41-NEXT:    mulq %r8
+; SSE41-NEXT:    mulq %r14
 ; SSE41-NEXT:    addq %rdi, %rdx
-; SSE41-NEXT:    setb %cl
-; SSE41-NEXT:    orb %bl, %cl
-; SSE41-NEXT:    orb %r13b, %cl
-; SSE41-NEXT:    movzbl %cl, %ecx
+; SSE41-NEXT:    setb %bl
+; SSE41-NEXT:    orb %cl, %bl
+; SSE41-NEXT:    orb %r12b, %bl
+; SSE41-NEXT:    movzbl %bl, %ecx
 ; SSE41-NEXT:    movd %ecx, %xmm0
-; SSE41-NEXT:    pinsrb $8, %ebp, %xmm0
-; SSE41-NEXT:    movq %r10, 16(%r14)
-; SSE41-NEXT:    movq %rax, (%r14)
-; SSE41-NEXT:    movq %r15, 24(%r14)
-; SSE41-NEXT:    movq %rdx, 8(%r14)
+; SSE41-NEXT:    pinsrb $8, %esi, %xmm0
+; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
+; SSE41-NEXT:    movq %r10, 16(%rcx)
+; SSE41-NEXT:    movq %rax, (%rcx)
+; SSE41-NEXT:    movq %r15, 24(%rcx)
+; SSE41-NEXT:    movq %rdx, 8(%rcx)
 ; SSE41-NEXT:    psllq $63, %xmm0
 ; SSE41-NEXT:    psrad $31, %xmm0
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    popq %rbx
 ; SSE41-NEXT:    popq %r12
 ; SSE41-NEXT:    popq %r13
 ; SSE41-NEXT:    popq %r14
 ; SSE41-NEXT:    popq %r15
 ; SSE41-NEXT:    popq %rbp
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: umulo_v2i128:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    pushq %rbp
 ; AVX1-NEXT:    pushq %r15
 ; AVX1-NEXT:    pushq %r14
 ; AVX1-NEXT:    pushq %r13
 ; AVX1-NEXT:    pushq %r12
 ; AVX1-NEXT:    pushq %rbx
+; AVX1-NEXT:    movq %r8, %r14
 ; AVX1-NEXT:    movq %rcx, %rax
 ; AVX1-NEXT:    movq %rdx, %r12
+; AVX1-NEXT:    movq %rsi, %r8
 ; AVX1-NEXT:    movq %rdi, %r11
-; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r14
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r15
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX1-NEXT:    testq %r10, %r10
 ; AVX1-NEXT:    setne %dl
 ; AVX1-NEXT:    testq %rcx, %rcx
 ; AVX1-NEXT:    setne %r13b
 ; AVX1-NEXT:    andb %dl, %r13b
 ; AVX1-NEXT:    mulq %r15
 ; AVX1-NEXT:    movq %rax, %rdi
 ; AVX1-NEXT:    seto %bpl
 ; AVX1-NEXT:    movq %r10, %rax
 ; AVX1-NEXT:    mulq %r12
 ; AVX1-NEXT:    movq %rax, %rbx
 ; AVX1-NEXT:    seto %cl
 ; AVX1-NEXT:    orb %bpl, %cl
 ; AVX1-NEXT:    addq %rdi, %rbx
 ; AVX1-NEXT:    movq %r12, %rax
 ; AVX1-NEXT:    mulq %r15
 ; AVX1-NEXT:    movq %rax, %r10
 ; AVX1-NEXT:    movq %rdx, %r15
 ; AVX1-NEXT:    addq %rbx, %r15
-; AVX1-NEXT:    setb %al
-; AVX1-NEXT:    orb %cl, %al
-; AVX1-NEXT:    orb %r13b, %al
-; AVX1-NEXT:    movzbl %al, %ebp
+; AVX1-NEXT:    setb %sil
+; AVX1-NEXT:    orb %cl, %sil
+; AVX1-NEXT:    orb %r13b, %sil
 ; AVX1-NEXT:    testq %r9, %r9
 ; AVX1-NEXT:    setne %al
-; AVX1-NEXT:    testq %rsi, %rsi
-; AVX1-NEXT:    setne %r13b
-; AVX1-NEXT:    andb %al, %r13b
-; AVX1-NEXT:    movq %rsi, %rax
-; AVX1-NEXT:    mulq %r8
-; AVX1-NEXT:    movq %rax, %rsi
-; AVX1-NEXT:    seto %r12b
+; AVX1-NEXT:    testq %r8, %r8
+; AVX1-NEXT:    setne %r12b
+; AVX1-NEXT:    andb %al, %r12b
+; AVX1-NEXT:    movq %r8, %rax
+; AVX1-NEXT:    mulq %r14
+; AVX1-NEXT:    movq %rax, %rbx
+; AVX1-NEXT:    seto %bpl
 ; AVX1-NEXT:    movq %r9, %rax
 ; AVX1-NEXT:    mulq %r11
 ; AVX1-NEXT:    movq %rax, %rdi
 ; AVX1-NEXT:    seto %cl
-; AVX1-NEXT:    orb %r12b, %cl
-; AVX1-NEXT:    addq %rsi, %rdi
+; AVX1-NEXT:    orb %bpl, %cl
+; AVX1-NEXT:    addq %rbx, %rdi
 ; AVX1-NEXT:    movq %r11, %rax
-; AVX1-NEXT:    mulq %r8
+; AVX1-NEXT:    mulq %r14
 ; AVX1-NEXT:    addq %rdi, %rdx
 ; AVX1-NEXT:    setb %bl
 ; AVX1-NEXT:    orb %cl, %bl
-; AVX1-NEXT:    orb %r13b, %bl
+; AVX1-NEXT:    orb %r12b, %bl
 ; AVX1-NEXT:    movzbl %bl, %ecx
 ; AVX1-NEXT:    vmovd %ecx, %xmm0
-; AVX1-NEXT:    vpinsrb $8, %ebp, %xmm0, %xmm0
-; AVX1-NEXT:    movq %r10, 16(%r14)
-; AVX1-NEXT:    movq %rax, (%r14)
-; AVX1-NEXT:    movq %r15, 24(%r14)
-; AVX1-NEXT:    movq %rdx, 8(%r14)
+; AVX1-NEXT:    vpinsrb $8, %esi, %xmm0, %xmm0
+; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
+; AVX1-NEXT:    movq %r10, 16(%rcx)
+; AVX1-NEXT:    movq %rax, (%rcx)
+; AVX1-NEXT:    movq %r15, 24(%rcx)
+; AVX1-NEXT:    movq %rdx, 8(%rcx)
 ; AVX1-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    popq %rbx
 ; AVX1-NEXT:    popq %r12
 ; AVX1-NEXT:    popq %r13
 ; AVX1-NEXT:    popq %r14
 ; AVX1-NEXT:    popq %r15
 ; AVX1-NEXT:    popq %rbp
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: umulo_v2i128:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    pushq %rbp
 ; AVX2-NEXT:    pushq %r15
 ; AVX2-NEXT:    pushq %r14
 ; AVX2-NEXT:    pushq %r13
 ; AVX2-NEXT:    pushq %r12
 ; AVX2-NEXT:    pushq %rbx
+; AVX2-NEXT:    movq %r8, %r14
 ; AVX2-NEXT:    movq %rcx, %rax
 ; AVX2-NEXT:    movq %rdx, %r12
+; AVX2-NEXT:    movq %rsi, %r8
 ; AVX2-NEXT:    movq %rdi, %r11
-; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r14
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r15
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX2-NEXT:    testq %r10, %r10
 ; AVX2-NEXT:    setne %dl
 ; AVX2-NEXT:    testq %rcx, %rcx
 ; AVX2-NEXT:    setne %r13b
 ; AVX2-NEXT:    andb %dl, %r13b
 ; AVX2-NEXT:    mulq %r15
 ; AVX2-NEXT:    movq %rax, %rdi
 ; AVX2-NEXT:    seto %bpl
 ; AVX2-NEXT:    movq %r10, %rax
 ; AVX2-NEXT:    mulq %r12
 ; AVX2-NEXT:    movq %rax, %rbx
 ; AVX2-NEXT:    seto %cl
 ; AVX2-NEXT:    orb %bpl, %cl
 ; AVX2-NEXT:    addq %rdi, %rbx
 ; AVX2-NEXT:    movq %r12, %rax
 ; AVX2-NEXT:    mulq %r15
 ; AVX2-NEXT:    movq %rax, %r10
 ; AVX2-NEXT:    movq %rdx, %r15
 ; AVX2-NEXT:    addq %rbx, %r15
-; AVX2-NEXT:    setb %al
-; AVX2-NEXT:    orb %cl, %al
-; AVX2-NEXT:    orb %r13b, %al
-; AVX2-NEXT:    movzbl %al, %ebp
+; AVX2-NEXT:    setb %sil
+; AVX2-NEXT:    orb %cl, %sil
+; AVX2-NEXT:    orb %r13b, %sil
 ; AVX2-NEXT:    testq %r9, %r9
 ; AVX2-NEXT:    setne %al
-; AVX2-NEXT:    testq %rsi, %rsi
-; AVX2-NEXT:    setne %r13b
-; AVX2-NEXT:    andb %al, %r13b
-; AVX2-NEXT:    movq %rsi, %rax
-; AVX2-NEXT:    mulq %r8
-; AVX2-NEXT:    movq %rax, %rsi
-; AVX2-NEXT:    seto %r12b
+; AVX2-NEXT:    testq %r8, %r8
+; AVX2-NEXT:    setne %r12b
+; AVX2-NEXT:    andb %al, %r12b
+; AVX2-NEXT:    movq %r8, %rax
+; AVX2-NEXT:    mulq %r14
+; AVX2-NEXT:    movq %rax, %rbx
+; AVX2-NEXT:    seto %bpl
 ; AVX2-NEXT:    movq %r9, %rax
 ; AVX2-NEXT:    mulq %r11
 ; AVX2-NEXT:    movq %rax, %rdi
 ; AVX2-NEXT:    seto %cl
-; AVX2-NEXT:    orb %r12b, %cl
-; AVX2-NEXT:    addq %rsi, %rdi
+; AVX2-NEXT:    orb %bpl, %cl
+; AVX2-NEXT:    addq %rbx, %rdi
 ; AVX2-NEXT:    movq %r11, %rax
-; AVX2-NEXT:    mulq %r8
+; AVX2-NEXT:    mulq %r14
 ; AVX2-NEXT:    addq %rdi, %rdx
 ; AVX2-NEXT:    setb %bl
 ; AVX2-NEXT:    orb %cl, %bl
-; AVX2-NEXT:    orb %r13b, %bl
+; AVX2-NEXT:    orb %r12b, %bl
 ; AVX2-NEXT:    movzbl %bl, %ecx
 ; AVX2-NEXT:    vmovd %ecx, %xmm0
-; AVX2-NEXT:    vpinsrb $8, %ebp, %xmm0, %xmm0
-; AVX2-NEXT:    movq %r10, 16(%r14)
-; AVX2-NEXT:    movq %rax, (%r14)
-; AVX2-NEXT:    movq %r15, 24(%r14)
-; AVX2-NEXT:    movq %rdx, 8(%r14)
+; AVX2-NEXT:    vpinsrb $8, %esi, %xmm0, %xmm0
+; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
+; AVX2-NEXT:    movq %r10, 16(%rcx)
+; AVX2-NEXT:    movq %rax, (%rcx)
+; AVX2-NEXT:    movq %r15, 24(%rcx)
+; AVX2-NEXT:    movq %rdx, 8(%rcx)
 ; AVX2-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX2-NEXT:    popq %rbx
 ; AVX2-NEXT:    popq %r12
 ; AVX2-NEXT:    popq %r13
 ; AVX2-NEXT:    popq %r14
 ; AVX2-NEXT:    popq %r15

llvm/test/CodeGen/X86/vec_usubo.ll

 ; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; SSSE3-NEXT:    retq
 ;
 ; SSE41-LABEL: usubo_v2i128:
 ; SSE41:       # %bb.0:
 ; SSE41-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; SSE41-NEXT:    subq {{[0-9]+}}(%rsp), %rdx
 ; SSE41-NEXT:    sbbq {{[0-9]+}}(%rsp), %rcx
-; SSE41-NEXT:    setb %al
-; SSE41-NEXT:    movzbl %al, %r11d
+; SSE41-NEXT:    setb %r11b
 ; SSE41-NEXT:    subq %r8, %rdi
 ; SSE41-NEXT:    sbbq %r9, %rsi
 ; SSE41-NEXT:    setb %al
 ; SSE41-NEXT:    movzbl %al, %eax
 ; SSE41-NEXT:    movd %eax, %xmm0
 ; SSE41-NEXT:    pinsrb $8, %r11d, %xmm0
 ; SSE41-NEXT:    movq %rdx, 16(%r10)
 ; SSE41-NEXT:    movq %rdi, (%r10)
 ; SSE41-NEXT:    movq %rcx, 24(%r10)
 ; SSE41-NEXT:    movq %rsi, 8(%r10)
 ; SSE41-NEXT:    psllq $63, %xmm0
 ; SSE41-NEXT:    psrad $31, %xmm0
 ; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
 ; SSE41-NEXT:    retq
 ;
 ; AVX1-LABEL: usubo_v2i128:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX1-NEXT:    subq {{[0-9]+}}(%rsp), %rdx
 ; AVX1-NEXT:    sbbq {{[0-9]+}}(%rsp), %rcx
-; AVX1-NEXT:    setb %al
-; AVX1-NEXT:    movzbl %al, %r11d
+; AVX1-NEXT:    setb %r11b
 ; AVX1-NEXT:    subq %r8, %rdi
 ; AVX1-NEXT:    sbbq %r9, %rsi
 ; AVX1-NEXT:    setb %al
 ; AVX1-NEXT:    movzbl %al, %eax
 ; AVX1-NEXT:    vmovd %eax, %xmm0
 ; AVX1-NEXT:    vpinsrb $8, %r11d, %xmm0, %xmm0
 ; AVX1-NEXT:    movq %rdx, 16(%r10)
 ; AVX1-NEXT:    movq %rdi, (%r10)
 ; AVX1-NEXT:    movq %rcx, 24(%r10)
 ; AVX1-NEXT:    movq %rsi, 8(%r10)
 ; AVX1-NEXT:    vpsllq $63, %xmm0, %xmm0
 ; AVX1-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: usubo_v2i128:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %r10
 ; AVX2-NEXT:    subq {{[0-9]+}}(%rsp), %rdx
 ; AVX2-NEXT:    sbbq {{[0-9]+}}(%rsp), %rcx
-; AVX2-NEXT:    setb %al
-; AVX2-NEXT:    movzbl %al, %r11d
+; AVX2-NEXT:    setb %r11b
 ; AVX2-NEXT:    subq %r8, %rdi
 ; AVX2-NEXT:    sbbq %r9, %rsi
 ; AVX2-NEXT:    setb %al
 ; AVX2-NEXT:    movzbl %al, %eax
 ; AVX2-NEXT:    vmovd %eax, %xmm0
 ; AVX2-NEXT:    vpinsrb $8, %r11d, %xmm0, %xmm0
 ; AVX2-NEXT:    movq %rdx, 16(%r10)
 ; AVX2-NEXT:    movq %rdi, (%r10)