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Differential D58695

[AMDGPU] Fixed hang during DAG combine
ClosedPublic

Authored by rampitec on Feb 26 2019, 12:51 PM.

Details

Reviewers
arsenm
scott.linder
Commits
rGda1628eb679d: [AMDGPU] Fixed hang during DAG combine
rL354926: [AMDGPU] Fixed hang during DAG combine
Summary

SITargetLowering::reassociateScalarOps() does not touch constants
so that DAGCombiner::ReassociateOps() does not revert the combine.
However a global address is not a ConstantSDNode.

Switched to the method used by DAGCombiner::ReassociateOps() itself
to detect constants.

Diff Detail

Event Timeline

rampitec created this revision.Feb 26 2019, 12:51 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptFeb 26 2019, 12:51 PM
arsenm accepted this revision.Feb 26 2019, 12:54 PM

LGTM

This revision is now accepted and ready to land.Feb 26 2019, 12:54 PM
Closed by commit rL354926: [AMDGPU] Fixed hang during DAG combine (authored by rampitec). · Explain WhyFeb 26 2019, 12:55 PM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptFeb 26 2019, 12:55 PM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
3 lines
test/
CodeGen/
AMDGPU/
16 lines

Diff 188445

lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,471 Lines • ▼ Show 20 LinesSDValue SITargetLowering::reassociateScalarOps(SDNode *N,
if (!(Op1->isDivergent() ^ Op2->isDivergent())) if (!(Op1->isDivergent() ^ Op2->isDivergent()))
return SDValue(); return SDValue();
if (Op1->isDivergent()) if (Op1->isDivergent())
std::swap(Op1, Op2); std::swap(Op1, Op2);
// If either operand is constant this will conflict with // If either operand is constant this will conflict with
// DAGCombiner::ReassociateOps(). // DAGCombiner::ReassociateOps().
if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) if (DAG.isConstantIntBuildVectorOrConstantInt(Op0) ||
DAG.isConstantIntBuildVectorOrConstantInt(Op1))
return SDValue(); return SDValue();
SDLoc SL(N); SDLoc SL(N);
SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1); SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1);
return DAG.getNode(Opc, SL, VT, Add1, Op2); return DAG.getNode(Opc, SL, VT, Add1, Op2);
} }
static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL, static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL,
▲ Show 20 Lines • Show All 1,338 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/reassoc-scalar.ll

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Linesbb:
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%add1 = add i32 %tid, 42 %add1 = add i32 %tid, 42
%add2 = add i32 %add1, %x %add2 = add i32 %add1, %x
store volatile i32 %add1, i32 addrspace(1)* %arg, align 4 store volatile i32 %add1, i32 addrspace(1)* %arg, align 4
store volatile i32 %add2, i32 addrspace(1)* %arg, align 4 store volatile i32 %add2, i32 addrspace(1)* %arg, align 4
ret void ret void
} }
@var = common hidden local_unnamed_addr addrspace(1) global [4 x i32] zeroinitializer, align 4
; GCN-LABEL: reassoc_i32_ga:
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, var@rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, var@rel32@hi+4
; GCN: s_endpgm
define amdgpu_kernel void @reassoc_i32_ga(i64 %x) {
bb:
%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%t64 = zext i32 %tid to i64
%add1 = getelementptr [4 x i32], [4 x i32] addrspace(1)* @var, i64 0, i64 %t64
%add2 = getelementptr i32, i32 addrspace(1)* %add1, i64 %x
store volatile i32 1, i32 addrspace(1)* %add2, align 4
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.workitem.id.y() declare i32 @llvm.amdgcn.workitem.id.y()