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Enablement for AMD znver2 architecture - skeleton patch
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Authored by GGanesh on Feb 18 2019, 4:25 AM.

Details

Summary

This patch enables the following

  1. AMD family 17h "znver2" tune flag (-march, -mcpu).
  2. ISAs that are enabled for "znver2" architecture.
  3. For the time being, it uses the znver1 scheduler model.
  4. Tests are updated.

Diff Detail

Repository
rL LLVM

Event Timeline

GGanesh created this revision.Feb 18 2019, 4:25 AM
GGanesh added a child revision: Restricted Differential Revision.Feb 18 2019, 4:34 AM
craig.topper added inline comments.Feb 18 2019, 9:02 AM
include/llvm/Support/X86TargetParser.def
93 ↗(On Diff #187218)

This list must be kept in the same order as libgcc's implementation for __builtin_cpu_is. New entries can't be added in the middle. If libgcc doesn't support znver2 yet, then you should use X86_CPU_SUBTYPE instead of X86_CPU_SUBTYPE_COMPAT.

lib/Target/X86/X86.td
1188 ↗(On Diff #187218)

Why is CLZERO not in ZNFeatures? Looks common to both znver1 and znver2

craig.topper added inline comments.Feb 18 2019, 9:04 AM
include/llvm/Support/X86TargetParser.def
93 ↗(On Diff #187218)

Looks like libgcc does support it. It should be just below ICELAKE_SERVER. https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/i386/cpuinfo.h

GGanesh updated this revision to Diff 187340.Feb 19 2019, 3:28 AM

Addressed the comments from Craig Topper

Herald added a project: Restricted Project. · View Herald TranscriptFeb 19 2019, 3:28 AM
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I think you uploaded the clang patch into the llvm review?

GGanesh updated this revision to Diff 187386.Feb 19 2019, 8:56 AM
GGanesh updated this revision to Diff 187389.Feb 19 2019, 9:03 AM
This revision is now accepted and ready to land.Feb 19 2019, 9:05 AM
Closed by commit rL354897: [X86] AMD znver2 enablement (authored by ggopala, committed by ). · Explain WhyFeb 26 2019, 8:55 AM
This revision was automatically updated to reflect the committed changes.