[GlobalISel][NFC] Gardening: Factor out more intrinsics into simple intrinsics

[paquette]

Summary

Found another place where we can just factor out a bunch of intrinsics and make it a bit easier to add more of these. The only difference between a "simple intrinsic" and, say, the overflow intrinsics is that simple intrinsics only have a single result.

This teaches translateSimpleIntrinsic to handle an arbitrary number of destination registers. Then we can factor out all of the overflow intrinsics, and delete translateOverflowIntrinsic entirely. Also makes the overflow intrinsics respect IR flags, which weren't being copied over in translateOverflowIntrinsic.

By doing this, we can add IRTranslator support for any intrinsic that can be "straight-line" translated by adding it to getSimpleIntrinsicOpcode.

[arsenm]

lib/CodeGen/GlobalISel/IRTranslator.cpp

859

I don't think you need to copy the ArrayRef to a SmallVector, you should be able to use the ArrayRef as is

[arsenm]

lib/CodeGen/GlobalISel/IRTranslator.cpp

859

Actually since this is DstOp, and not unsigned, you do. Maybe this should be moved as an overload in MachineIRBuilder though. You also don't need the llvm::

[aemerson]

lib/CodeGen/GlobalISel/IRTranslator.cpp

859

Seems like SrcOp and DstOp should be inside MachineIRBuilder instead of in the llvm namespace anyway.

[arsenm]

Is this still needed?

[arsenm]

LGTM

include/llvm/CodeGen/GlobalISel/IRTranslator.h

private:
   bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
 
   /// Translate an LLVM string intrinsic (memcpy, memset, ...).
   bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
                         unsigned ID);
 
   void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
 
-  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
-                                  MachineIRBuilder &MIRBuilder);
-
   /// Helper function for translateSimpleIntrinsic.
   /// \return The generic opcode for \p IntrinsicID if \p IntrinsicID is a
   /// simple intrinsic (ceil, fabs, etc.). Otherwise, returns
   /// Intrinsic::not_intrinsic.
   unsigned getSimpleIntrinsicOpcode(Intrinsic::ID ID);
 
   /// Translates the intrinsics defined in getSimpleIntrinsicOpcode.
   /// \return true if the translation succeeded.

lib/CodeGen/GlobalISel/IRTranslator.cpp

void IRTranslator::getStackGuard(unsigned DstReg,
   auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
                MachineMemOperand::MODereferenceable;
   MachineMemOperand *MemRef =
       MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
                                DL->getPointerABIAlignment(0));
   MIB.setMemRefs({MemRef});
 }
 
-bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
-                                              MachineIRBuilder &MIRBuilder) {
-  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(CI);
-  MIRBuilder.buildInstr(Op)
-      .addDef(ResRegs[0])
-      .addDef(ResRegs[1])
-      .addUse(getOrCreateVReg(*CI.getOperand(0)))
-      .addUse(getOrCreateVReg(*CI.getOperand(1)));
-
-  return true;
-}
-
 unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
   switch (ID) {
     default:
       break;
     case Intrinsic::bswap:
       return TargetOpcode::G_BSWAP;
     case Intrinsic::ceil:
       return TargetOpcode::G_FCEIL;
switch (ID) {
     case Intrinsic::round:
       return TargetOpcode::G_INTRINSIC_ROUND;
     case Intrinsic::sin:
       return TargetOpcode::G_FSIN;
     case Intrinsic::sqrt:
       return TargetOpcode::G_FSQRT;
     case Intrinsic::trunc:
       return TargetOpcode::G_INTRINSIC_TRUNC;
+    case Intrinsic::uadd_with_overflow:
+      return TargetOpcode::G_UADDO;
+    case Intrinsic::sadd_with_overflow:
+      return TargetOpcode::G_SADDO;
+    case Intrinsic::usub_with_overflow:
+      return TargetOpcode::G_USUBO;
+    case Intrinsic::ssub_with_overflow:
+      return TargetOpcode::G_SSUBO;
+    case Intrinsic::umul_with_overflow:
+      return TargetOpcode::G_UMULO;
+    case Intrinsic::smul_with_overflow:
+      return TargetOpcode::G_SMULO;
     }
   return Intrinsic::not_intrinsic;
 }
 
 bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
                                             Intrinsic::ID ID,
                                             MachineIRBuilder &MIRBuilder) {
 
   unsigned Op = getSimpleIntrinsicOpcode(ID);
 
   // Is this a simple intrinsic?
   if (Op == Intrinsic::not_intrinsic)
     return false;
 
   // Yes. Let's translate it.
-  SmallVector<llvm::SrcOp, 4> VRegs;
+  // Our intrinsic looks something like this:
+  //
+  // [dst 1, dst2, ..., dst n] = llvm.something(src1, src2, ..., src m)
+  //
+  // Get or create vregs for all of the sources and destinations, and attach
+  // those to a generic instruction.
+
+  SmallVector<llvm::SrcOp, 4> SrcOps;
   for (auto &Arg : CI.arg_operands())
-    VRegs.push_back(getOrCreateVReg(*Arg));
+    SrcOps.push_back(getOrCreateVReg(*Arg));
 
-  MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
+  ArrayRef<unsigned> DstRegs = getOrCreateVRegs(CI);
+  SmallVector<llvm::DstOp, 4> DstOps(DstRegs.begin(), DstRegs.end());
+
+  MIRBuilder.buildInstr(Op, DstOps, SrcOps,
                         MachineInstr::copyFlagsFromInstruction(CI));
   return true;
 }
 
 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
                                            MachineIRBuilder &MIRBuilder) {
 
   // If this is a simple intrinsic (that is, we just need to add a def of
if (!V) {
       // FIXME: This does not handle register-indirect values at offset 0. The
       // direct/indirect thing shouldn't really be handled by something as
       // implicit as reg+noreg vs reg+imm in the first palce, but it seems
       // pretty baked in right now.
       MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
     }
     return true;
   }
-  case Intrinsic::uadd_with_overflow:
-    return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
-  case Intrinsic::sadd_with_overflow:
-    return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
-  case Intrinsic::usub_with_overflow:
-    return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
-  case Intrinsic::ssub_with_overflow:
-    return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
-  case Intrinsic::umul_with_overflow:
-    return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
-  case Intrinsic::smul_with_overflow:
-    return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
   case Intrinsic::fmuladd: {
     const TargetMachine &TM = MF->getTarget();
     const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
     unsigned Dst = getOrCreateVReg(CI);
     unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
     unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
     unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
     if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&