[GlobalISel][AArch64] Select llvm.bswap* for non-vector types

[paquette]

Summary

This teaches the IRTranslator to emit G_BSWAP when it runs into Intrinsic::bswap. This allows us to select G_BSWAP for non-vector types in AArch64.

Add a select-bswap.mir test, and add global isel checks to a couple existing tests in test/CodeGen/AArch64.

This doesn't handle every bswap case, since some of these rely on known bits stuff. This just lets us handle the naive case.

[arsenm]

LGTM

lib/Target/AArch64/select-bswap.mir

10–12 ↗

(On Diff #186354)

You can drop the register sections

41 ↗

(On Diff #186354)

Extra space before =

[paquette]

Updating diff to address comments on test before committing

[eugenis]

Hi,

you have a test file under lib/Target/AArch64.
Is it intentional? I don't think it does anything...

llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp

bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
   return true;
 }
 
 unsigned
 IRTranslator::getSimpleUnaryIntrinsicOpcode(Intrinsic::ID ID) {
   switch (ID) {
     default:
       break;
+    case Intrinsic::bswap:
+      return TargetOpcode::G_BSWAP;
     case Intrinsic::ceil:
       return TargetOpcode::G_FCEIL;
     case Intrinsic::cos:
       return TargetOpcode::G_FCOS;
     case Intrinsic::ctpop:
       return TargetOpcode::G_CTPOP;
     case Intrinsic::exp:
       return TargetOpcode::G_FEXP;

llvm/trunk/lib/Target/AArch64/select-bswap.mir

+# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
+# RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
+# RUN: | FileCheck %s
+...
+---
+name:            bswap_s32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            bswap_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
+    ; CHECK: $w0 = COPY [[REVWr]]
+    liveins: $s0
+    %0:gpr(s32) = COPY $w0
+    %1:gpr(s32) = G_BSWAP %0
+    $w0 = COPY %1(s32)
+
+...
+---
+name:            bswap_s64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name:            bswap_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
+    ; CHECK: $x0 = COPY [[REVXr]]
+    liveins: $x0
+    %0:gpr(s64) = COPY $d0
+    %1:gpr(s64) = G_BSWAP %0
+    $x0 = COPY %1(s64)
+
+...

llvm/trunk/test/CodeGen/AArch64/arm64-rev.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=FALLBACK,GISEL
 
+; FALLBACK-NOT: remark{{.*}}test_rev_w
 define i32 @test_rev_w(i32 %a) nounwind {
 ; CHECK-LABEL: test_rev_w:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    rev w0, w0
 ; CHECK-NEXT:    ret
+; GISEL-LABEL: test_rev_w:
+; GISEL:       // %bb.0: // %entry
+; GISEL-NEXT:    rev w0, w0
+; GISEL-NEXT:    ret
 entry:
   %0 = tail call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %0
 }
 
+; FALLBACK-NOT: remark{{.*}}test_rev_x
 define i64 @test_rev_x(i64 %a) nounwind {
 ; CHECK-LABEL: test_rev_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    rev x0, x0
 ; CHECK-NEXT:    ret
+; GISEL-LABEL: test_rev_x:
+; GISEL:       // %bb.0: // %entry
+; GISEL-NEXT:    rev x0, x0
+; GISEL-NEXT:    ret
 entry:
   %0 = tail call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %0
 }
 
 ; Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16-bits
 ; of %a are zero. This optimizes rev + lsr 16 to rev16.
 define i32 @test_rev_w_srl16(i16 %a) {

llvm/trunk/test/CodeGen/AArch64/dp1.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
+; RUN: llc -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=FALLBACK,GISEL
 
 @var32 = global i32 0
 @var64 = global i64 0
 
+; FALLBACK-NOT: remark{{.*}}rev_i32
 define void @rev_i32() {
 ; CHECK-LABEL: rev_i32:
+; GISEL-LABEL: rev_i32:
     %val0_tmp = load i32, i32* @var32
     %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
 ; CHECK: rev  {{w[0-9]+}}, {{w[0-9]+}}
+; GISEL: rev  {{w[0-9]+}}, {{w[0-9]+}}
     store volatile i32 %val1_tmp, i32* @var32
     ret void
 }
 
+; FALLBACK-NOT: remark{{.*}}rev_i64
 define void @rev_i64() {
 ; CHECK-LABEL: rev_i64:
+; GISEL-LABEL: rev_i64:
     %val0_tmp = load i64, i64* @var64
     %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
 ; CHECK: rev  {{x[0-9]+}}, {{x[0-9]+}}
+; GISEL: rev  {{x[0-9]+}}, {{x[0-9]+}}
     store volatile i64 %val1_tmp, i64* @var64
     ret void
 }
 
 define void @rev32_i64() {
 ; CHECK-LABEL: rev32_i64:
     %val0_tmp = load i64, i64* @var64
     %val1_tmp = shl i64 %val0_tmp, 32

 declare i32 @llvm.bswap.i32(i32)
 declare i64 @llvm.bswap.i64(i64)
 declare i32  @llvm.ctlz.i32 (i32, i1)
 declare i64  @llvm.ctlz.i64 (i64, i1)
 declare i32  @llvm.cttz.i32 (i32, i1)
 declare i64  @llvm.cttz.i64 (i64, i1)
 declare i32  @llvm.ctpop.i32 (i32)
 declare i64  @llvm.ctpop.i64 (i64)
-