[AArch64][GlobalSel] Add isel support for a couple vector exts/truncs

[paquette]

Summary

Add support for

• v4s16 <-> v4s32
• v2s64 <-> v2s32

And update tests that use them to show that we generate the correct instructions.

[aemerson]

I think if you're going to have a new separate test, you might as well make it a MIR test for the selector (just use update_mir_test_checks.py) instead of an IR test which already exists in arm64-vcvt_f.ll.

[paquette]

Updated existing .mir test instead of adding a .ll test

[arsenm]

test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

5–7 ↗

(On Diff #186288)

You shouldn't need the IR section at all in this test. Maybe a pre-commit to remove this?

[paquette]

test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

5–7 ↗

(On Diff #186288)

Good idea. r353731.

[paquette]

Rebased after removing redundant IR from existing .mir test

[aemerson]

LGTM.

llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

getActionDefinitionsBuilder(G_FCMP)
       .widenScalarToNextPow2(1);
 
   // Extensions
   getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
       .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32});
 
   // FP conversions
   getActionDefinitionsBuilder(G_FPTRUNC).legalFor(
-      {{s16, s32}, {s16, s64}, {s32, s64}});
+      {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}});
   getActionDefinitionsBuilder(G_FPEXT).legalFor(
-      {{s32, s16}, {s64, s16}, {s64, s32}});
+      {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}});
 
   // Conversions
   getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
       .legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(0)
       .clampScalar(1, s32, s64)
       .widenScalarToNextPow2(1);

llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

bb.0:
     ; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
     ; CHECK: $s0 = COPY [[FCVTSDr]]
     %0(s64) = COPY $d0
     %1(s32) = G_FPTRUNC %0
     $s0 = COPY %1(s32)
 ...
 
 ---
+name:            fptrunc_v4s16_v4s32_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[FCVTNv4i16:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+    ; CHECK: $d0 = COPY [[FCVTNv4i16]]
+    %0(<4 x s32>) = COPY $q0
+    %1(<4 x s16>) = G_FPTRUNC %0
+    $d0 = COPY %1(<4 x s16>)
+...
+
+---
+name:            fptrunc_v2s32_v2s64_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK: [[FCVTNv2i32:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+    ; CHECK: $d0 = COPY [[FCVTNv2i32]]
+    %0(<2 x s64>) = COPY $q0
+    %1(<2 x s32>) = G_FPTRUNC %0
+    $d0 = COPY %1(<2 x s32>)
+...
+
+---
 name:            fpext_s32_s16_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
bb.0:
     ; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
     ; CHECK: $d0 = COPY [[FCVTDSr]]
     %0(s32) = COPY $s0
     %1(s64) = G_FPEXT %0
     $d0 = COPY %1(s64)
 ...
 
 ---
+name:            fpext_v4s32_v4s16_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[FCVTLv4i16:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+    ; CHECK: $q0 = COPY [[FCVTLv4i16]]
+    %0(<4 x s16>) = COPY $d0
+    %1(<4 x s32>) = G_FPEXT %0
+    $q0 = COPY %1(<4 x s32>)
+...
+
+---
+name:            fpext_v2s64_v2s32_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK: [[FCVTLv2i32:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+    ; CHECK: $q0 = COPY [[FCVTLv2i32]]
+    %0(<2 x s32>) = COPY $d0
+    %1(<2 x s64>) = G_FPEXT %0
+    $q0 = COPY %1(<2 x s64>)
+...
+
+---
 name:            sitofp_s32_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 

llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 ; RUN: llc < %s -O0 -fast-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* \
+; RUN:          -mtriple=arm64-eabi -aarch64-neon-syntax=apple \
+; RUN:          | FileCheck %s --check-prefixes=GISEL,FALLBACK
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f64_f32)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f64_f32)
 define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_f64_f32:
+; GISEL-LABEL: test_vcvt_f64_f32:
   %vcvt1.i = fpext <2 x float> %x to <2 x double>
 ; CHECK: fcvtl  v0.2d, v0.2s
+; GISEL: fcvtl  v0.2d, v0.2s
   ret <2 x double> %vcvt1.i
 ; CHECK: ret
+; GISEL: ret
 }
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f64_f32)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f64_f32)
 define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_high_f64_f32:
+; GISEL-LABEL: test_vcvt_high_f64_f32:
   %cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>
   %vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>
 ; CHECK: fcvtl2 v0.2d, v0.4s
+; GISEL: fcvtl2 v0.2d, v0.4s
   ret <2 x double> %vcvt1.i
 ; CHECK: ret
+; GISEL: ret
 }
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f32_f64)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f32_f64)
 define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_f32_f64:
+; GISEL-LABEL: test_vcvt_f32_f64:
   %vcvt1.i = fptrunc <2 x double> %v to <2 x float>
 ; CHECK: fcvtn
+; GISEL: fcvtn
   ret <2 x float> %vcvt1.i
 ; CHECK: ret
+; GISEL: ret
 }
 
+; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f32_f64)
+; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f32_f64)
 define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvt_high_f32_f64:
-
+; GISEL-LABEL: test_vcvt_high_f32_f64:
   %cvt = fptrunc <2 x double> %v to <2 x float>
   %vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 ; CHECK: fcvtn2
+; GISEL: fcvtn2
   ret <4 x float> %vcvt2.i
 ; CHECK: ret
+; GISEL: ret
 }
 
 define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {
 ; CHECK-LABEL: test_vcvtx_f32_f64:
   %vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
 ; CHECK: fcvtxn
   ret <2 x float> %vcvtx1.i
 ; CHECK: ret