[WebAssembly] Fix a regression selecting negative build_vector lanes

[tlively]

Summary

The custom lowering introduced in rL352592 creates build_vector nodes
with negative i32 operands, but these operands did not meet the value
range constraints necessary to match build_vector nodes. This CL fixes
the issue by removing the unnecessary constraints.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

34

Is this unnecessary or incorrect because it assumes an unsigned integer? Looks like there are ways to specify signed immediate too: example1 example2

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

34

It's not incorrect, per se, but the alternative fix would be to change the custom build_vector lowering logic to mask all the build_vector operands it produces to make them unsigned, matching the expectation here. It seemed simpler to save a few cycles and just remove this predicate.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

34

Sorry I don't understand. What I meant was to change the definition of ImmI8 and ImmI16 from unsigned to signed immediates. In that case why do we need to make operands unsigned?

[tlively]

• Make ImmI8 and ImmI16 match signed immediates

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

34

Oh I understand. I like that idea.

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 defm "" : ARGUMENT<V128, v16i8>;
 defm "" : ARGUMENT<V128, v8i16>;
 defm "" : ARGUMENT<V128, v4i32>;
 defm "" : ARGUMENT<V128, v2i64>;
 defm "" : ARGUMENT<V128, v4f32>;
 defm "" : ARGUMENT<V128, v2f64>;
 
 // Constrained immediate argument types
-foreach SIZE = [8, 16] in
-def ImmI#SIZE : ImmLeaf<i32,
-  "return ((uint64_t)Imm & ((1UL << "#SIZE#") - 1)) == (uint64_t)Imm;"
->;
 foreach SIZE = [2, 4, 8, 16, 32] in
 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
 
 //===----------------------------------------------------------------------===//
 // Load and store
 //===----------------------------------------------------------------------===//
 
 // Load: v128.load
defm "" : ConstVec<v16i8,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
                         vec_i8imm_op:$i2, vec_i8imm_op:$i3,
                         vec_i8imm_op:$i4, vec_i8imm_op:$i5,
                         vec_i8imm_op:$i6, vec_i8imm_op:$i7,
                         vec_i8imm_op:$i8, vec_i8imm_op:$i9,
                         vec_i8imm_op:$iA, vec_i8imm_op:$iB,
                         vec_i8imm_op:$iC, vec_i8imm_op:$iD,
                         vec_i8imm_op:$iE, vec_i8imm_op:$iF),
-                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
-                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
-                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
-                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
+                   (build_vector
+                     (i32 imm:$i0), (i32 imm:$i1), (i32 imm:$i2), (i32 imm:$i3),
+                     (i32 imm:$i4), (i32 imm:$i5), (i32 imm:$i6), (i32 imm:$i7),
+                     (i32 imm:$i8), (i32 imm:$i9), (i32 imm:$iA), (i32 imm:$iB),
+                     (i32 imm:$iC), (i32 imm:$iD), (i32 imm:$iE), (i32 imm:$iF)),
                    !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
                               "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
 defm "" : ConstVec<v8i16,
                    (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
                         vec_i16imm_op:$i2, vec_i16imm_op:$i3,
                         vec_i16imm_op:$i4, vec_i16imm_op:$i5,
                         vec_i16imm_op:$i6, vec_i16imm_op:$i7),
                    (build_vector
-                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
-                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
+                     (i32 imm:$i0), (i32 imm:$i1), (i32 imm:$i2), (i32 imm:$i3),
+                     (i32 imm:$i4), (i32 imm:$i5), (i32 imm:$i6), (i32 imm:$i7)),
                    "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
 defm "" : ConstVec<v4i32,
                    (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
                         vec_i32imm_op:$i2, vec_i32imm_op:$i3),
                    (build_vector (i32 imm:$i0), (i32 imm:$i1),
                                  (i32 imm:$i2), (i32 imm:$i3)),
                    "$i0, $i1, $i2, $i3">;
 defm "" : ConstVec<v2i64,

llvm/test/CodeGen/WebAssembly/simd-build-vector.ll

 
 ; CHECK-LABEL: different_const_one_replaced_i8x16:
 ; CHECK-NEXT:  .functype       different_const_one_replaced_i8x16 (i32) -> (v128)
 ; CHECK-NEXT:  v128.const      $push[[L0:[0-9]+]]=, 1, 2, 3, 4, 5, 0, 7, 8
 ; CHECK-NEXT:  i16x8.replace_lane      $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
 ; CHECK-NEXT:  return          $pop[[L1]]
 define <8 x i16> @different_const_one_replaced_i8x16(i16 %x) {
   %v = insertelement
-    <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>,
+    <8 x i16> <i16 1, i16 -2, i16 3, i16 -4, i16 5, i16 -6, i16 7, i16 -8>,
     i16 %x,
     i32 5
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: same_const_one_replaced_f32x4:
 ; CHECK-NEXT:  .functype       same_const_one_replaced_f32x4 (f32) -> (v128)
 ; CHECK-NEXT:  f32.const       $push[[L0:[0-9]+]]=, 0x1.5p5