[AArch64][GlobalISel] Unmerge into scalars from a vector should use FPR bank

[aemerson]

Summary

This currently shows up as a selection fallback since the dest regs were given GPR banks but the source was a vector FPR reg.

[arsenm]

llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir

17–20

registers and the IR section are unnecessary

[paquette]

LGTM

llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

auto HasFPConstraints = [&TRI, &MRI, this](MachineInstr &MI) {
       if (Op != TargetOpcode::COPY && !MI.isPHI())
         return false;
 
       // MI is copy-like. Return true if it's using an FPR.
       return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
              &AArch64::FPRRegBank;
     };
 
-    if (any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
+    LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
+    // UNMERGE into scalars from a vector should always use FPR.
+    // Likewise if any of the uses are FP instructions.
+    if (SrcTy.isVector() ||
+        any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
                [&](MachineInstr &MI) { return HasFPConstraints(MI); })) {
       // Set the register bank of every operand to FPR.
       for (unsigned Idx = 0, NumOperands = MI.getNumOperands();
            Idx < NumOperands; ++Idx)
         OpRegBankIdx[Idx] = PMI_FirstFPR;
     }
     break;
   }

llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64"
+
+  define i64 @unmerge(<2 x double> %p) {
+    ret i64 undef
+  }
+
+...
+---
+name:            unmerge
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $q0
+
+    ; Ensure that the dest regs have FPR since we're unmerging from a vector
+    ; CHECK-LABEL: name: unmerge
+    ; CHECK: liveins: $q0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
+    ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+    ; CHECK: $x0 = COPY [[UV]](s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %0:_(<2 x s64>) = COPY $q0
+    %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
+    $x0 = COPY %1(s64)
+    RET_ReallyLR implicit $x0
+
+...