[RISCV] Allow parsing immediates that use tilde & exclaim

[lewis-revill]

Summary

This patch allows immediates (and CSR alias immediates) which start with a tilde token or an exclaim (!) token to be parsed as intended.

[jrtc27]

There's also AsmToken::Exclaim for logical not that we could allow (although that's not one I've ever seen in real-world assembly). Please add tests for the CSR change?

[lewis-revill]

In D57320#1373431, @jrtc27 wrote:

There's also AsmToken::Exclaim for logical not that we could allow (although that's not one I've ever seen in real-world assembly). Please add tests for the CSR change?

It would probably be good to add that for completeness. machine-csr-names.s seems a good place to add CSR tests?

[asb]

In D57320#1373523, @lewis-revill wrote:

In D57320#1373431, @jrtc27 wrote:

There's also AsmToken::Exclaim for logical not that we could allow (although that's not one I've ever seen in real-world assembly). Please add tests for the CSR change?

It would probably be good to add that for completeness. machine-csr-names.s seems a good place to add CSR tests?

I'd put it in rv32i-valid.s.

[lewis-revill]

Also parse exlaim (!) as a valid token to start an immediate. Add some CSR tests.

[asb]

LGTM, thanks!

test/MC/RISCV/rv32i-valid.s

343 ↗

(On Diff #183863)

Should be updated to csrrw s0, fflags, s1 to match current HEAD behaviour.

llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
   const MCExpr *Res;
 
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;
   case AsmToken::LParen:
   case AsmToken::Minus:
   case AsmToken::Plus:
+  case AsmToken::Exclaim:
+  case AsmToken::Tilde:
   case AsmToken::Integer:
   case AsmToken::String: {
     if (getParser().parseExpression(Res))
       return MatchOperand_ParseFail;
 
     auto *CE = dyn_cast<MCConstantExpr>(Res);
     if (CE) {
       int64_t Imm = CE->getValue();
OperandMatchResultTy RISCVAsmParser::parseImmediate(OperandVector &Operands) {
   const MCExpr *Res;
 
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;
   case AsmToken::LParen:
   case AsmToken::Minus:
   case AsmToken::Plus:
+  case AsmToken::Exclaim:
+  case AsmToken::Tilde:
   case AsmToken::Integer:
   case AsmToken::String:
   case AsmToken::Identifier:
     if (getParser().parseExpression(Res))
       return MatchOperand_ParseFail;
     break;
   case AsmToken::Percent:
     return parseOperandWithModifier(Operands);

llvm/trunk/test/MC/RISCV/rv32i-valid.s

 # CHECK-ASM: encoding: [0x6f,0x04,0xc0,0x09]
 jal s0, (0xff-99)
 
 # CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
 # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
 jalr a0, a1, -2048
 # CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
 # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
+jalr a0, a1, ~2047
+# CHECK-ASM-AND-OBJ: jalr a0, a1, 0
+# CHECK-ASM: encoding: [0x67,0x85,0x05,0x00]
+jalr a0, a1, !1
+# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
+# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
 jalr a0, a1, %lo(2048)
 # CHECK-ASM-AND-OBJ: jalr t2, t1, 2047
 # CHECK-ASM: encoding: [0xe7,0x03,0xf3,0x7f]
 jalr t2, t1, 2047
 # CHECK-ASM-AND-OBJ: jalr sp, zero, 256
 # CHECK-ASM: encoding: [0x67,0x01,0x00,0x10]
 jalr sp, zero, 256
 # CHECK-ASM-AND-OBJ: jalr a1, a2, 30

 # CHECK-ASM-AND-OBJ: lb s3, 4(ra)
 # CHECK-ASM: encoding: [0x83,0x89,0x40,0x00]
 lb s3, +4(ra)
 # CHECK-ASM-AND-OBJ: lh t1, -2048(zero)
 # CHECK-ASM: encoding: [0x03,0x13,0x00,0x80]
 lh t1, -2048(zero)
 # CHECK-ASM-AND-OBJ: lh t1, -2048(zero)
 # CHECK-ASM: encoding: [0x03,0x13,0x00,0x80]
+lh t1, ~2047(zero)
+# CHECK-ASM-AND-OBJ: lh t1, 0(zero)
+# CHECK-ASM: encoding: [0x03,0x13,0x00,0x00]
+lh t1, !1(zero)
+# CHECK-ASM-AND-OBJ: lh t1, -2048(zero)
+# CHECK-ASM: encoding: [0x03,0x13,0x00,0x80]
 lh t1, %lo(2048)(zero)
 # CHECK-ASM-AND-OBJ: lh sp, 2047(a0)
 # CHECK-ASM: encoding: [0x03,0x11,0xf5,0x7f]
 lh sp, 2047(a0)
 # CHECK-ASM-AND-OBJ: lw a0, 97(a2)
 # CHECK-ASM: encoding: [0x03,0x25,0x16,0x06]
 lw a0, 97(a2)
 # CHECK-ASM: lbu s5, %lo(foo)(s6)

 # CHECK-ASM-AND-OBJ: sb a0, 2047(a2)
 # CHECK-ASM: encoding: [0xa3,0x0f,0xa6,0x7e]
 sb a0, 2047(a2)
 # CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
 # CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
 sh t3, -2048(t5)
 # CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
 # CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
+sh t3, ~2047(t5)
+# CHECK-ASM-AND-OBJ: sh t3, 0(t5)
+# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x01]
+sh t3, !1(t5)
+# CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
+# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
 sh t3, %lo(2048)(t5)
 # CHECK-ASM-AND-OBJ: sw ra, 999(zero)
 # CHECK-ASM: encoding: [0xa3,0x23,0x10,0x3e]
 sw ra, 999(zero)
 # CHECK-ASM-AND-OBJ: sw a0, 30(t0)
 # CHECK-ASM: encoding: [0x23,0xaf,0xa2,0x00]
 sw a0, CONST(t0)
 # CHECK-ASM-AND-OBJ: sw s0, 0(s1)

 # CHECK-ASM-AND-OBJ: xori tp, t1, -99
 # CHECK-ASM: encoding: [0x13,0x42,0xd3,0xf9]
 xori tp, t1, -99
 # CHECK-ASM-AND-OBJ: ori a0, a1, -2048
 # CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80]
 ori a0, a1, -2048
 # CHECK-ASM-AND-OBJ: ori a0, a1, -2048
 # CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80]
+ori a0, a1, ~2047
+# CHECK-ASM-AND-OBJ: ori a0, a1, 0
+# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x00]
+ori a0, a1, !1
+# CHECK-ASM-AND-OBJ: ori a0, a1, -2048
+# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80]
 ori a0, a1, %lo(2048)
 # CHECK-ASM-AND-OBJ: andi ra, sp, 2047
 # CHECK-ASM: encoding: [0x93,0x70,0xf1,0x7f]
 andi ra, sp, 2047
 # CHECK-ASM-AND-OBJ: andi ra, sp, 2047
 # CHECK-ASM: encoding: [0x93,0x70,0xf1,0x7f]
 andi x1, x2, 2047
 

 # CHECK-ASM: encoding: [0x73,0x10,0x00,0xc0]
 unimp
 
 .equ CONST, 16
 
 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
 # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]
 csrrw t0, 0xfff, t1
+# CHECK-ASM-AND-OBJ: csrrw s0, 4095, s1
+# CHECK-ASM: encoding: [0x73,0x94,0xf4,0xff]
+csrrw s0, ~(-4096), s1
+# CHECK-ASM-AND-OBJ: csrrw s0, fflags, s1
+# CHECK-ASM: encoding: [0x73,0x94,0x14,0x00]
+csrrw s0, !0, s1
 # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
 # CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
 csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
 # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
 csrrs s3, 0x001, s5
 # CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
 # CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]