[X86][BdVer2] Transfer delays from the integer to the floating point unit.

[lebedev.ri]

Summary

I'm unable to find this number in the "AMD SOG for family 15h".
llvm-exegesis measures the latencies of these instructions as 2,
which matches the latencies specified in "AMD SOG for family 15h".

However if we look at Agner, Microarchitecture, "AMD Bulldozer, Piledriver,
Steamroller and Excavator pipeline", "Data delay between different execution
domains", the int->ivec transfer is listed as 8..10cy of additional latency.

Also, Agner's "Instruction tables", for Piledriver, lists their latencies as 12,
which is consistent with 2cy from exegesis / AMD SOG + 10cy transfer delay.

Additional data point comes from the fact that Agner's "Instruction tables",
for Jaguar, lists their latencies as 8; and "AMD SOG for family 16h" does
state the +6cy int->ivec delay, which is consistent with instr latency of 1 or 2.

[andreadb]

I'm unable to find this number in the "AMD SOG for family 15h".
llvm-exegesis measures the latencies of these instructions as 2,
which matches the latencies specified in "AMD SOG for family 15h".

Can you print out the code snippet used by llvm-exegesis to measure that latency?

[lebedev.ri]

In D57300#1375180, @andreadb wrote:

I'm unable to find this number in the "AMD SOG for family 15h".
llvm-exegesis measures the latencies of these instructions as 2,
which matches the latencies specified in "AMD SOG for family 15h".

Can you print out the code snippet used by llvm-exegesis to measure that latency?

Sure, i should have done that.

$ ./bin/llvm-exegesis -mode=latency -opcode-name=VPINSRBrr
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-639c95.o
---
mode:            latency
key:             
  instructions:    
    - 'VPINSRBrr XMM7 XMM7 R15D i_0x1'
  config:          ''
  register_initial_values: 
    - 'XMM7=0x0'
    - 'R15D=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 2.0296, per_snippet_value: 2.0296 }
error:           ''
info:            Repeating a single explicitly serial instruction
assembled_snippet: 41574883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F3C244883C41041BF00000000C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01C4C34120FF01415FC3

snippet-639c95.o59 KBDownload

$ /usr/bin/objdump -d /tmp/snippet-639c95.o 

/tmp/snippet-639c95.o:     file format elf64-x86-64


Disassembly of section .text:

0000000000000000 <foo>:
       0:       41 57                   push   %r15
       2:       48 83 ec 10             sub    $0x10,%rsp
       6:       c7 04 24 00 00 00 00    movl   $0x0,(%rsp)
       d:       c7 44 24 04 00 00 00    movl   $0x0,0x4(%rsp)
      14:       00 
      15:       c7 44 24 08 00 00 00    movl   $0x0,0x8(%rsp)
      1c:       00 
      1d:       c7 44 24 0c 00 00 00    movl   $0x0,0xc(%rsp)
      24:       00 
      25:       c5 fa 6f 3c 24          vmovdqu (%rsp),%xmm7
      2a:       48 83 c4 10             add    $0x10,%rsp
      2e:       41 bf 00 00 00 00       mov    $0x0,%r15d
      34:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
      3a:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
....
    ea88:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
    ea8e:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
    ea94:       41 5f                   pop    %r15
    ea96:       c3                      retq   

I have additionally tried measuring the actual MCA snippets:

$ cat /tmp/snippet.s
# LLVM-EXEGESIS-LIVEIN EAX
# LLVM-EXEGESIS-LIVEIN XMM0
vpinsrb $0, %eax, %xmm0, %xmm0
vpinsrb $1, %eax, %xmm0, %xmm0
$ ./bin/llvm-exegesis -mode=latency -snippets-file=/tmp/snippet.s
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-67eb60.o
---
mode:            latency
key:             
  instructions:    
    - 'VPINSRBrr XMM0 XMM0 EAX i_0x0'
    - 'VPINSRBrr XMM0 XMM0 EAX i_0x1'
  config:          ''
  register_initial_values: []
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 2.0317, per_snippet_value: 4.0634 }
error:           ''
info:            ''
assembled_snippet: C4E37920C000C4E37920C001C4E37920C000C4E37920C001C4E37920C000C4E37920C001C4E37920C000C4E37920C001C4E37920C000C4E37920C001C4E37920C000C4E37920C001C4E37920C000C4E37920C001C4E37920C000C4E37920C001C3
...

and

$ cat /tmp/snippet.s
# LLVM-EXEGESIS-LIVEIN EAX
# LLVM-EXEGESIS-LIVEIN XMM0
add %eax, %eax
vpinsrb $0, %eax, %xmm0, %xmm0
vpinsrb $1, %eax, %xmm0, %xmm0
$ ./bin/llvm-exegesis -mode=latency -snippets-file=/tmp/snippet.s
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-562e79.o
---
mode:            latency
key:             
  instructions:    
    - 'ADD32rr EAX EAX EAX'
    - 'VPINSRBrr XMM0 XMM0 EAX i_0x0'
    - 'VPINSRBrr XMM0 XMM0 EAX i_0x1'
  config:          ''
  register_initial_values: []
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 1.4034, per_snippet_value: 4.2102 }
error:           ''
info:            ''
assembled_snippet: 01C0C4E37920C000C4E37920C00101C0C4E37920C000C4E37920C00101C0C4E37920C000C4E37920C00101C0C4E37920C000C4E37920C00101C0C4E37920C000C4E37920C00101C0C3

Am i holding llvm-exegesis wrong, or does this mean the info in Agner incorrect here?

[andreadb]

      2e:       41 bf 00 00 00 00       mov    $0x0,%r15d
      34:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
      3a:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
....
    ea88:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7

If there is really a bypass delay, then that code snippet is not going to expose it.
The real bottleneck in that code snippet is the dependency on %xmm7. R15 is only set once at the beginning by a zero-move, and then never updated again.

In this case, we have that each cycle the scheduler issues a uOp to moves R15 to the FPU. However, the vpinsrd can only be issued every other cycle due to the dependency on XMM7. That means, in the long run, any bypass delay is going to be hidden by the latency caused by the data dependency on XMM7.
Basically, that code snippet is not good to measure those kinds of delays...

[andreadb]

(I edited my previous comment. However, the system didn't send another email.)

[lebedev.ri]

In D57300#1375602, @andreadb wrote:

      2e:       41 bf 00 00 00 00       mov    $0x0,%r15d
      34:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
      3a:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7
....
    ea88:       c4 c3 41 20 ff 01       vpinsrb $0x1,%r15d,%xmm7,%xmm7

If there is really a bypass delay, then that code snippet is not going to expose it.
The real bottleneck in that code snippet is the dependency on %xmm7. R15 is only set once at the beginning by a zero-move, and then never updated again.

In this case, we have that each cycle the scheduler issues a uOp to moves R15 to the FPU. However, the vpinsrd can only be issued every other cycle due to the dependency on XMM7. That means, in the long run, any bypass delay is going to be hidden by the latency caused by the data dependency on XMM7.
Basically, that code snippet is not good to measure those kinds of delays...

Very nice observation.
Let's try something better.

$ cat /tmp/snippet.s ; ./bin/llvm-exegesis -mode=latency -snippets-file=/tmp/snippet.s
# LLVM-EXEGESIS-DEFREG EAX 0
# LLVM-EXEGESIS-DEFREG XMM0 0
# LLVM-EXEGESIS-DEFREG XMM1 0
vpinsrb $0, %eax, %xmm0, %xmm1
vpextrb $0, %xmm1, %eax
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-a71a33.o
---
mode:            latency
key:             
  instructions:    
    - 'VPINSRBrr XMM1 XMM0 EAX i_0x0'
    - 'VPEXTRBrr EAX XMM1 i_0x0'
  config:          ''
  register_initial_values: 
    - 'EAX=0x0'
    - 'XMM0=0x0'
    - 'XMM1=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 11.0282, per_snippet_value: 22.0564 }
error:           ''
info:            ''
assembled_snippet: B8000000004883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F0C244883C410C4E37920C800C4E37914C800C4E37920C800C4E37914C800C4E37920C800C4E37914C800C4E37920C800C4E37914C800C4E37920C800C4E37914C800C4E37920C800C4E37914C800C4E37920C800C4E37914C800C4E37920C800C4E37914C800C3
...
$ /usr/bin/objdump -d /tmp/snippet-a71a33.o

/tmp/snippet-a71a33.o:     file format elf64-x86-64


Disassembly of section .text:

0000000000000000 <foo>:
       0:       b8 00 00 00 00          mov    $0x0,%eax
       5:       48 83 ec 10             sub    $0x10,%rsp
       9:       c7 04 24 00 00 00 00    movl   $0x0,(%rsp)
      10:       c7 44 24 04 00 00 00    movl   $0x0,0x4(%rsp)
      17:       00 
      18:       c7 44 24 08 00 00 00    movl   $0x0,0x8(%rsp)
      1f:       00 
      20:       c7 44 24 0c 00 00 00    movl   $0x0,0xc(%rsp)
      27:       00 
      28:       c5 fa 6f 04 24          vmovdqu (%rsp),%xmm0
      2d:       48 83 c4 10             add    $0x10,%rsp
      31:       48 83 ec 10             sub    $0x10,%rsp
      35:       c7 04 24 00 00 00 00    movl   $0x0,(%rsp)
      3c:       c7 44 24 04 00 00 00    movl   $0x0,0x4(%rsp)
      43:       00 
      44:       c7 44 24 08 00 00 00    movl   $0x0,0x8(%rsp)
      4b:       00 
      4c:       c7 44 24 0c 00 00 00    movl   $0x0,0xc(%rsp)
      53:       00 
      54:       c5 fa 6f 0c 24          vmovdqu (%rsp),%xmm1
      59:       48 83 c4 10             add    $0x10,%rsp
      5d:       c4 e3 79 20 c8 00       vpinsrb $0x0,%eax,%xmm0,%xmm1
      63:       c4 e3 79 14 c8 00       vpextrb $0x0,%xmm1,%eax
...
    eab1:       c4 e3 79 20 c8 00       vpinsrb $0x0,%eax,%xmm0,%xmm1
    eab7:       c4 e3 79 14 c8 00       vpextrb $0x0,%xmm1,%eax
    eabd:       c3                      retq   

Though i suppose that still have the dependency on xmm1.

[andreadb]

Thanks for running that experiment. There is clearly an 8-10cy delay.

Out of curiosity, do you get the same latency if the insertion/extract is at index $1 (I.e. not at index 0)?

That being said. I think this change is good, and it is consistent with the latency value defined for the WriteVecMoveToGpr and WriteVecMoveFromGpr. So, LGTM

[lebedev.ri]

In D57300#1380363, @andreadb wrote:

Thanks for running that experiment. There is clearly an 8-10cy delay.

Out of curiosity, do you get the same latency if the insertion/extract is at index $1 (I.e. not at index 0)?

I did, the results appear to be consistent:

$ cat /tmp/snippet.s ; ./bin/llvm-exegesis -mode=latency -snippets-file=/tmp/snippet.s
# LLVM-EXEGESIS-DEFREG EAX 0
# LLVM-EXEGESIS-DEFREG XMM0 0
# LLVM-EXEGESIS-DEFREG XMM1 0
vpinsrb $1, %eax, %xmm0, %xmm1
vpextrb $1, %xmm1, %eax
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-2b8c21.o
---
mode:            latency
key:             
  instructions:    
    - 'VPINSRBrr XMM1 XMM0 EAX i_0x1'
    - 'VPEXTRBrr EAX XMM1 i_0x1'
  config:          ''
  register_initial_values: 
    - 'EAX=0x0'
    - 'XMM0=0x0'
    - 'XMM1=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 11.0372, per_snippet_value: 22.0744 }
error:           ''
info:            ''
assembled_snippet: B8000000004883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F0C244883C410C4E37920C801C4E37914C801C4E37920C801C4E37914C801C4E37920C801C4E37914C801C4E37920C801C4E37914C801C4E37920C801C4E37914C801C4E37920C801C4E37914C801C4E37920C801C4E37914C801C4E37920C801C4E37914C801C3
...
$ cat /tmp/snippet.s ; ./bin/llvm-exegesis -mode=latency -snippets-file=/tmp/snippet.s
# LLVM-EXEGESIS-DEFREG EAX 0
# LLVM-EXEGESIS-DEFREG XMM0 0
# LLVM-EXEGESIS-DEFREG XMM1 0
vpinsrb $0, %eax, %xmm0, %xmm1
vpextrb $1, %xmm1, %eax
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-3b8c6f.o
---
mode:            latency
key:             
  instructions:    
    - 'VPINSRBrr XMM1 XMM0 EAX i_0x0'
    - 'VPEXTRBrr EAX XMM1 i_0x1'
  config:          ''
  register_initial_values: 
    - 'EAX=0x0'
    - 'XMM0=0x0'
    - 'XMM1=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 11.0304, per_snippet_value: 22.0608 }
error:           ''
info:            ''
assembled_snippet: B8000000004883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F0C244883C410C4E37920C800C4E37914C801C4E37920C800C4E37914C801C4E37920C800C4E37914C801C4E37920C800C4E37914C801C4E37920C800C4E37914C801C4E37920C800C4E37914C801C4E37920C800C4E37914C801C4E37920C800C4E37914C801C3
...
$ cat /tmp/snippet.s ; ./bin/llvm-exegesis -mode=latency -snippets-file=/tmp/snippet.s
# LLVM-EXEGESIS-DEFREG EAX 0
# LLVM-EXEGESIS-DEFREG XMM0 0
# LLVM-EXEGESIS-DEFREG XMM1 0
vpinsrb $1, %eax, %xmm0, %xmm1
vpextrb $0, %xmm1, %eax
Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-5f6929.o
---
mode:            latency
key:             
  instructions:    
    - 'VPINSRBrr XMM1 XMM0 EAX i_0x1'
    - 'VPEXTRBrr EAX XMM1 i_0x0'
  config:          ''
  register_initial_values: 
    - 'EAX=0x0'
    - 'XMM0=0x0'
    - 'XMM1=0x0'
cpu_name:        bdver2
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 11.0333, per_snippet_value: 22.0666 }
error:           ''
info:            ''
assembled_snippet: B8000000004883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F04244883C4104883EC10C7042400000000C744240400000000C744240800000000C744240C00000000C5FA6F0C244883C410C4E37920C801C4E37914C800C4E37920C801C4E37914C800C4E37920C801C4E37914C800C4E37920C801C4E37914C800C4E37920C801C4E37914C800C4E37920C801C4E37914C800C4E37920C801C4E37914C800C4E37920C801C4E37914C800C3
...

That being said. I think this change is good, and it is consistent with the latency value defined for the WriteVecMoveToGpr and WriteVecMoveFromGpr.

I suspect ReadFpu2Int will too be introduced?

So, LGTM

Thank you for the review.

llvm/trunk/lib/Target/X86/X86ScheduleBdVer2.td

 def : ReadAdvance<ReadAfterLd, 4>;
 
 // Vector loads are 5 cycles, so ReadAfterVec*Ld registers needn't be available
 // until 5 cycles after the memory operand.
 def : ReadAdvance<ReadAfterVecLd, 5>;
 def : ReadAdvance<ReadAfterVecXLd, 5>;
 def : ReadAdvance<ReadAfterVecYLd, 5>;
 
-def : ReadAdvance<ReadInt2Fpu, 0>;
+// Transfer from int domain to ivec domain incurs additional latency of 8..10cy
+// Reference: Agner, Microarchitecture, "AMD Bulldozer, Piledriver, Steamroller
+// and Excavator pipeline", "Data delay between different execution domains"
+def : ReadAdvance<ReadInt2Fpu, -10>;
 
 // A folded store needs a cycle on the PdStore for the store data.
 def : WriteRes<WriteRMW, [PdStore]>;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Loads, stores, and moves, not folded with other operations.
 ////////////////////////////////////////////////////////////////////////////////
 

llvm/trunk/test/CodeGen/X86/mmx-schedule.ll

 ; SKX-NEXT:    movswl (%rsi), %eax # sched: [5:0.50]
 ; SKX-NEXT:    pinsrw $1, %eax, %mm0 # sched: [2:2.00]
 ; SKX-NEXT:    movq %mm0, %rax # sched: [2:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BDVER2-LABEL: test_pinsrw:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    movswl (%rsi), %eax # sched: [5:0.50]
-; BDVER2-NEXT:    pinsrw $0, %edi, %mm0 # sched: [2:0.50]
-; BDVER2-NEXT:    pinsrw $1, %eax, %mm0 # sched: [2:0.50]
+; BDVER2-NEXT:    pinsrw $0, %edi, %mm0 # sched: [12:0.50]
+; BDVER2-NEXT:    pinsrw $1, %eax, %mm0 # sched: [12:0.50]
 ; BDVER2-NEXT:    movq %mm0, %rax # sched: [10:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-LABEL: test_pinsrw:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    movswl (%rsi), %eax # sched: [4:1.00]
 ; BTVER2-NEXT:    pinsrw $0, %edi, %mm0 # sched: [7:0.50]
 ; BTVER2-NEXT:    pinsrw $1, %eax, %mm0 # sched: [7:0.50]

llvm/trunk/test/CodeGen/X86/sse-schedule.ll

 ; SKX-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [5:1.00]
 ; SKX-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; SKX-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BDVER2-SSE-LABEL: test_cvtsi2ss:
 ; BDVER2-SSE:       # %bb.0:
 ; BDVER2-SSE-NEXT:    cvtsi2ssl (%rsi), %xmm0 # sched: [9:1.00]
-; BDVER2-SSE-NEXT:    cvtsi2ssl %edi, %xmm1 # sched: [4:1.00]
+; BDVER2-SSE-NEXT:    cvtsi2ssl %edi, %xmm1 # sched: [14:1.00]
 ; BDVER2-SSE-NEXT:    addss %xmm1, %xmm0 # sched: [5:1.00]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_cvtsi2ss:
 ; BDVER2:       # %bb.0:
-; BDVER2-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [4:1.00]
+; BDVER2-NEXT:    vcvtsi2ssl %edi, %xmm0, %xmm0 # sched: [14:1.00]
 ; BDVER2-NEXT:    vcvtsi2ssl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2ss:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    cvtsi2ssl (%rsi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2ssl %edi, %xmm1 # sched: [10:1.00]

 ; BDVER2-SSE:       # %bb.0:
 ; BDVER2-SSE-NEXT:    cvtsi2ssq %rdi, %xmm1 # sched: [13:1.00]
 ; BDVER2-SSE-NEXT:    cvtsi2ssq (%rsi), %xmm0 # sched: [9:1.00]
 ; BDVER2-SSE-NEXT:    addss %xmm1, %xmm0 # sched: [5:1.00]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_cvtsi2ssq:
 ; BDVER2:       # %bb.0:
-; BDVER2-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [4:1.00]
+; BDVER2-NEXT:    vcvtsi2ssq %rdi, %xmm0, %xmm0 # sched: [14:1.00]
 ; BDVER2-NEXT:    vcvtsi2ssq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddss %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2ssq:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    cvtsi2ssq (%rsi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2ssq %rdi, %xmm1 # sched: [10:1.00]

llvm/trunk/test/CodeGen/X86/sse2-schedule.ll

 ; SKX-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [5:1.00]
 ; SKX-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; SKX-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BDVER2-SSE-LABEL: test_cvtsi2sd:
 ; BDVER2-SSE:       # %bb.0:
 ; BDVER2-SSE-NEXT:    cvtsi2sdl (%rsi), %xmm0 # sched: [9:1.00]
-; BDVER2-SSE-NEXT:    cvtsi2sdl %edi, %xmm1 # sched: [4:1.00]
+; BDVER2-SSE-NEXT:    cvtsi2sdl %edi, %xmm1 # sched: [14:1.00]
 ; BDVER2-SSE-NEXT:    addsd %xmm1, %xmm0 # sched: [5:1.00]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_cvtsi2sd:
 ; BDVER2:       # %bb.0:
-; BDVER2-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [4:1.00]
+; BDVER2-NEXT:    vcvtsi2sdl %edi, %xmm0, %xmm0 # sched: [14:1.00]
 ; BDVER2-NEXT:    vcvtsi2sdl (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2sd:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    cvtsi2sdl (%rsi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2sdl %edi, %xmm1 # sched: [10:1.00]

 ; BDVER2-SSE:       # %bb.0:
 ; BDVER2-SSE-NEXT:    cvtsi2sdq %rdi, %xmm1 # sched: [13:1.00]
 ; BDVER2-SSE-NEXT:    cvtsi2sdq (%rsi), %xmm0 # sched: [9:1.00]
 ; BDVER2-SSE-NEXT:    addsd %xmm1, %xmm0 # sched: [5:1.00]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_cvtsi2sdq:
 ; BDVER2:       # %bb.0:
-; BDVER2-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [4:1.00]
+; BDVER2-NEXT:    vcvtsi2sdq %rdi, %xmm0, %xmm0 # sched: [14:1.00]
 ; BDVER2-NEXT:    vcvtsi2sdq (%rsi), %xmm1, %xmm1 # sched: [9:1.00]
 ; BDVER2-NEXT:    vaddsd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_cvtsi2sdq:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    cvtsi2sdq (%rsi), %xmm0 # sched: [9:1.00]
 ; BTVER2-SSE-NEXT:    cvtsi2sdq %rdi, %xmm1 # sched: [10:1.00]

 ; SKX-LABEL: test_pinsrw:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]
 ; SKX-NEXT:    vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BDVER2-SSE-LABEL: test_pinsrw:
 ; BDVER2-SSE:       # %bb.0:
-; BDVER2-SSE-NEXT:    pinsrw $1, %edi, %xmm0 # sched: [2:0.50]
+; BDVER2-SSE-NEXT:    pinsrw $1, %edi, %xmm0 # sched: [12:0.50]
 ; BDVER2-SSE-NEXT:    pinsrw $3, (%rsi), %xmm0 # sched: [6:0.50]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_pinsrw:
 ; BDVER2:       # %bb.0:
-; BDVER2-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [2:0.50]
+; BDVER2-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [12:0.50]
 ; BDVER2-NEXT:    vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_pinsrw:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    pinsrw $1, %edi, %xmm0 # sched: [7:0.50]
 ; BTVER2-SSE-NEXT:    pinsrw $3, (%rsi), %xmm0 # sched: [4:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]

llvm/trunk/test/CodeGen/X86/sse41-schedule.ll

 ; SKX-LABEL: test_pinsrb:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpinsrb $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]
 ; SKX-NEXT:    vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BDVER2-SSE-LABEL: test_pinsrb:
 ; BDVER2-SSE:       # %bb.0:
-; BDVER2-SSE-NEXT:    pinsrb $1, %edi, %xmm0 # sched: [2:0.50]
+; BDVER2-SSE-NEXT:    pinsrb $1, %edi, %xmm0 # sched: [12:0.50]
 ; BDVER2-SSE-NEXT:    pinsrb $3, (%rsi), %xmm0 # sched: [6:0.50]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_pinsrb:
 ; BDVER2:       # %bb.0:
-; BDVER2-NEXT:    vpinsrb $1, %edi, %xmm0, %xmm0 # sched: [2:0.50]
+; BDVER2-NEXT:    vpinsrb $1, %edi, %xmm0, %xmm0 # sched: [12:0.50]
 ; BDVER2-NEXT:    vpinsrb $3, (%rsi), %xmm0, %xmm0 # sched: [6:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_pinsrb:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    pinsrb $1, %edi, %xmm0 # sched: [7:0.50]
 ; BTVER2-SSE-NEXT:    pinsrb $3, (%rsi), %xmm0 # sched: [4:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]

 ; SKX-LABEL: test_pinsrd:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpinsrd $1, %edi, %xmm0, %xmm0 # sched: [2:2.00]
 ; SKX-NEXT:    vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BDVER2-SSE-LABEL: test_pinsrd:
 ; BDVER2-SSE:       # %bb.0:
-; BDVER2-SSE-NEXT:    pinsrd $1, %edi, %xmm0 # sched: [2:0.50]
+; BDVER2-SSE-NEXT:    pinsrd $1, %edi, %xmm0 # sched: [12:0.50]
 ; BDVER2-SSE-NEXT:    pinsrd $3, (%rsi), %xmm0 # sched: [6:0.50]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_pinsrd:
 ; BDVER2:       # %bb.0:
-; BDVER2-NEXT:    vpinsrd $1, %edi, %xmm0, %xmm0 # sched: [2:0.50]
+; BDVER2-NEXT:    vpinsrd $1, %edi, %xmm0, %xmm0 # sched: [12:0.50]
 ; BDVER2-NEXT:    vpinsrd $3, (%rsi), %xmm0, %xmm0 # sched: [6:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_pinsrd:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    pinsrd $1, %edi, %xmm0 # sched: [7:0.50]
 ; BTVER2-SSE-NEXT:    pinsrd $3, (%rsi), %xmm0 # sched: [4:1.00]
 ; BTVER2-SSE-NEXT:    retq # sched: [4:1.00]

 ; SKX-NEXT:    vpinsrq $1, %rdi, %xmm0, %xmm0 # sched: [2:2.00]
 ; SKX-NEXT:    vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [6:1.00]
 ; SKX-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BDVER2-SSE-LABEL: test_pinsrq:
 ; BDVER2-SSE:       # %bb.0:
 ; BDVER2-SSE-NEXT:    pinsrq $1, (%rsi), %xmm1 # sched: [6:0.50]
-; BDVER2-SSE-NEXT:    pinsrq $1, %rdi, %xmm0 # sched: [2:0.50]
+; BDVER2-SSE-NEXT:    pinsrq $1, %rdi, %xmm0 # sched: [12:0.50]
 ; BDVER2-SSE-NEXT:    paddq %xmm1, %xmm0 # sched: [2:0.50]
 ; BDVER2-SSE-NEXT:    retq # sched: [5:1.00]
 ;
 ; BDVER2-LABEL: test_pinsrq:
 ; BDVER2:       # %bb.0:
 ; BDVER2-NEXT:    vpinsrq $1, (%rsi), %xmm1, %xmm1 # sched: [6:0.50]
-; BDVER2-NEXT:    vpinsrq $1, %rdi, %xmm0, %xmm0 # sched: [2:0.50]
+; BDVER2-NEXT:    vpinsrq $1, %rdi, %xmm0, %xmm0 # sched: [12:0.50]
 ; BDVER2-NEXT:    vpaddq %xmm1, %xmm0, %xmm0 # sched: [2:0.50]
 ; BDVER2-NEXT:    retq # sched: [5:1.00]
 ;
 ; BTVER2-SSE-LABEL: test_pinsrq:
 ; BTVER2-SSE:       # %bb.0:
 ; BTVER2-SSE-NEXT:    pinsrq $1, (%rsi), %xmm1 # sched: [4:1.00]
 ; BTVER2-SSE-NEXT:    pinsrq $1, %rdi, %xmm0 # sched: [7:0.50]
 ; BTVER2-SSE-NEXT:    paddq %xmm1, %xmm0 # sched: [1:0.50]

llvm/trunk/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-1.s

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      2     0.50                        vpinsrb $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT:  2      2     0.50                        vpinsrb $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrb $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrb $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      2     0.50                        vpinsrw $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT:  2      2     0.50                        vpinsrw $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrw $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrw $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      2     0.50                        vpinsrd $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT:  2      2     0.50                        vpinsrd $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrd $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrd $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      2     0.50                        vpinsrq $0, %rax, %xmm0, %xmm0
-# CHECK-NEXT:  2      2     0.50                        vpinsrq $1, %rax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrq $0, %rax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrq $1, %rax, %xmm0, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

llvm/trunk/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-2.s

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      4     1.00                        vcvtsi2ssl  %ecx, %xmm0, %xmm0
+# CHECK-NEXT:  2      14    1.00                        vcvtsi2ssl  %ecx, %xmm0, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      4     1.00                        vcvtsi2sdl  %ecx, %xmm0, %xmm0
+# CHECK-NEXT:  2      14    1.00                        vcvtsi2sdl  %ecx, %xmm0, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      4     1.00                        cvtsi2ssl %ecx, %xmm0
+# CHECK-NEXT:  2      14    1.00                        cvtsi2ssl %ecx, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  2      4     1.00                        cvtsi2sdl %ecx, %xmm0
+# CHECK-NEXT:  2      14    1.00                        cvtsi2sdl %ecx, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

llvm/trunk/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-3.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 add %eax, %eax
 vpinsrb $0, %eax, %xmm0, %xmm0
 vpinsrb $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      1500
-# CHECK-NEXT: Total Cycles:      2004
+# CHECK-NEXT: Total Cycles:      2014
 # CHECK-NEXT: Total uOps:        2500
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.25
-# CHECK-NEXT: IPC:               0.75
+# CHECK-NEXT: uOps Per Cycle:    1.24
+# CHECK-NEXT: IPC:               0.74
 # CHECK-NEXT: Block RThroughput: 1.3
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     0.50                        addl  %eax, %eax
-# CHECK-NEXT:  2      2     0.50                        vpinsrb $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT:  2      2     0.50                        vpinsrb $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrb $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT:  2      12    0.50                        vpinsrb $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0.0] - PdAGLU01
 # CHECK-NEXT: [0.1] - PdAGLU01
 # CHECK-NEXT: [1]   - PdBranch
 # CHECK-NEXT: [2]   - PdCount
 # CHECK-NEXT: [3]   - PdDiv
 # CHECK-NEXT: [4]   - PdEX0

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %eax, %eax
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     1.00    -      -      -      -      -      -      -     vpinsrb  $0, %eax, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     1.00    -      -      -      -      -      -      -      -     vpinsrb  $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012345
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT:                     0123456789
+# CHECK-NEXT: Index     0123456789          012345
 
-# CHECK:      [0,0]     DeER .    .    .   addl %eax, %eax
-# CHECK-NEXT: [0,1]     D=eeER    .    .   vpinsrb  $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [0,2]     .D==eeER  .    .   vpinsrb  $1, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [1,0]     .DeE---R  .    .   addl %eax, %eax
-# CHECK-NEXT: [1,1]     . D===eeER.    .   vpinsrb  $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [1,2]     . D=====eeER   .   vpinsrb  $1, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [2,0]     .  DeE-----R   .   addl %eax, %eax
-# CHECK-NEXT: [2,1]     .  D======eeER .   vpinsrb  $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [2,2]     .   D=======eeER   vpinsrb  $1, %eax, %xmm0, %xmm0
+# CHECK:      [0,0]     DeER .    .    .    .    .   addl %eax, %eax
+# CHECK-NEXT: [0,1]     D===========eeER    .    .   vpinsrb  $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [0,2]     .D============eeER  .    .   vpinsrb  $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [1,0]     .DeE-------------R  .    .   addl %eax, %eax
+# CHECK-NEXT: [1,1]     . D=============eeER.    .   vpinsrb  $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [1,2]     . D===============eeER   .   vpinsrb  $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [2,0]     .  DeE---------------R   .   addl %eax, %eax
+# CHECK-NEXT: [2,1]     .  D================eeER .   vpinsrb  $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [2,2]     .   D=================eeER   vpinsrb  $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     1.0    0.7    2.7       addl %eax, %eax
-# CHECK-NEXT: 1.     3     4.3    0.0    0.0       vpinsrb  $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT: 2.     3     5.7    0.0    0.0       vpinsrb  $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT: 0.     3     1.0    0.7    9.3       addl %eax, %eax
+# CHECK-NEXT: 1.     3     14.3   0.0    0.0       vpinsrb  $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT: 2.     3     15.7   0.0    0.0       vpinsrb  $1, %eax, %xmm0, %xmm0

llvm/trunk/test/tools/llvm-mca/X86/BdVer2/resources-avx1.s

 # CHECK-NEXT:  4      8     2.00                        vcvtps2pd %xmm0, %ymm2
 # CHECK-NEXT:  5      13    2.00    *                   vcvtps2pd (%rax), %ymm2
 # CHECK-NEXT:  2      13    1.00                        vcvtsd2si %xmm0, %ecx
 # CHECK-NEXT:  2      13    1.00                        vcvtsd2si %xmm0, %rcx
 # CHECK-NEXT:  2      18    1.00    *                   vcvtsd2si (%rax), %ecx
 # CHECK-NEXT:  2      18    1.00    *                   vcvtsd2si (%rax), %rcx
 # CHECK-NEXT:  1      4     1.00                        vcvtsd2ss %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   vcvtsd2ss (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      4     1.00                        vcvtsi2sdl  %ecx, %xmm0, %xmm2
-# CHECK-NEXT:  2      4     1.00                        vcvtsi2sdq  %rcx, %xmm0, %xmm2
+# CHECK-NEXT:  2      14    1.00                        vcvtsi2sdl  %ecx, %xmm0, %xmm2
+# CHECK-NEXT:  2      14    1.00                        vcvtsi2sdq  %rcx, %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   vcvtsi2sdl  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   vcvtsi2sdq  (%rax), %xmm0, %xmm2
-# CHECK-NEXT:  2      4     1.00                        vcvtsi2ssl  %ecx, %xmm0, %xmm2
-# CHECK-NEXT:  2      4     1.00                        vcvtsi2ssq  %rcx, %xmm0, %xmm2
+# CHECK-NEXT:  2      14    1.00                        vcvtsi2ssl  %ecx, %xmm0, %xmm2
+# CHECK-NEXT:  2      14    1.00                        vcvtsi2ssq  %rcx, %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   vcvtsi2ssl  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   vcvtsi2ssq  (%rax), %xmm0, %xmm2
 # CHECK-NEXT:  1      4     1.00                        vcvtss2sd %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   vcvtss2sd (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  2      13    1.00                        vcvtss2si %xmm0, %ecx
 # CHECK-NEXT:  2      13    1.00                        vcvtss2si %xmm0, %rcx
 # CHECK-NEXT:  2      18    1.00    *                   vcvtss2si (%rax), %ecx
 # CHECK-NEXT:  2      18    1.00    *                   vcvtss2si (%rax), %rcx

 # CHECK-NEXT:  2      4     1.00                        vphminposuw %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   vphminposuw (%rax), %xmm2
 # CHECK-NEXT:  3      5     0.50                        vphsubd %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  4      10    0.50    *                   vphsubd (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  3      5     0.50                        vphsubsw  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  4      10    0.50    *                   vphsubsw  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  3      5     0.50                        vphsubw %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  4      10    0.50    *                   vphsubw (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      2     0.50                        vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT:  2      12    0.50                        vpinsrb $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  2      6     0.50    *                   vpinsrb $1, (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      2     0.50                        vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT:  2      12    0.50                        vpinsrd $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  2      6     0.50    *                   vpinsrd $1, (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      2     0.50                        vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT:  2      12    0.50                        vpinsrq $1, %rax, %xmm1, %xmm2
 # CHECK-NEXT:  2      6     0.50    *                   vpinsrq $1, (%rax), %xmm1, %xmm2
-# CHECK-NEXT:  2      2     0.50                        vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT:  2      12    0.50                        vpinsrw $1, %eax, %xmm1, %xmm2
 # CHECK-NEXT:  2      6     0.50    *                   vpinsrw $1, (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      4     1.00                        vpmaddubsw  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   vpmaddubsw  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      4     1.00                        vpmaddwd  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   vpmaddwd  (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      2     0.50                        vpmaxsb %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   vpmaxsb (%rax), %xmm1, %xmm2
 # CHECK-NEXT:  1      2     0.50                        vpmaxsd %xmm0, %xmm1, %xmm2

llvm/trunk/test/tools/llvm-mca/X86/BdVer2/resources-sse1.s

 # CHECK-NEXT:  1      2     1.00                        cmpss $0, %xmm0, %xmm2
 # CHECK-NEXT:  1      7     1.00    *                   cmpss $0, (%rax), %xmm2
 # CHECK-NEXT:  2      1     1.00                        comiss  %xmm0, %xmm1
 # CHECK-NEXT:  2      6     1.00    *                   comiss  (%rax), %xmm1
 # CHECK-NEXT:  2      4     1.00                        cvtpi2ps  %mm0, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   cvtpi2ps  (%rax), %xmm2
 # CHECK-NEXT:  1      4     1.00                        cvtps2pi  %xmm0, %mm2
 # CHECK-NEXT:  1      9     1.00    *                   cvtps2pi  (%rax), %mm2
-# CHECK-NEXT:  2      4     1.00                        cvtsi2ssl %ecx, %xmm2
+# CHECK-NEXT:  2      14    1.00                        cvtsi2ssl %ecx, %xmm2
 # CHECK-NEXT:  2      13    1.00                        cvtsi2ssq %rcx, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   cvtsi2ssl (%rax), %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   cvtsi2ssl (%rax), %xmm2
 # CHECK-NEXT:  2      13    1.00                        cvtss2si  %xmm0, %ecx
 # CHECK-NEXT:  2      13    1.00                        cvtss2si  %xmm0, %rcx
 # CHECK-NEXT:  2      18    1.00    *                   cvtss2si  (%rax), %ecx
 # CHECK-NEXT:  2      18    1.00    *                   cvtss2si  (%rax), %rcx
 # CHECK-NEXT:  1      4     1.00                        cvttps2pi %xmm0, %mm2

 # CHECK-NEXT:  1      10    1.00    *                   mulss (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        orps  %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   orps  (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pavgb %mm0, %mm2
 # CHECK-NEXT:  1      7     0.50    *                   pavgb (%rax), %mm2
 # CHECK-NEXT:  1      2     0.50                        pavgw %mm0, %mm2
 # CHECK-NEXT:  1      7     0.50    *                   pavgw (%rax), %mm2
 # CHECK-NEXT:  2      13    1.00                        pextrw  $1, %mm0, %ecx
-# CHECK-NEXT:  2      2     0.50                        pinsrw  $1, %eax, %mm2
+# CHECK-NEXT:  2      12    0.50                        pinsrw  $1, %eax, %mm2
 # CHECK-NEXT:  2      6     0.50    *                   pinsrw  $1, (%rax), %mm2
 # CHECK-NEXT:  1      2     0.50                        pmaxsw  %mm0, %mm2
 # CHECK-NEXT:  1      7     0.50    *                   pmaxsw  (%rax), %mm2
 # CHECK-NEXT:  1      2     0.50                        pmaxub  %mm0, %mm2
 # CHECK-NEXT:  1      7     0.50    *                   pmaxub  (%rax), %mm2
 # CHECK-NEXT:  1      2     0.50                        pminsw  %mm0, %mm2
 # CHECK-NEXT:  1      7     0.50    *                   pminsw  (%rax), %mm2
 # CHECK-NEXT:  1      2     0.50                        pminub  %mm0, %mm2

llvm/trunk/test/tools/llvm-mca/X86/BdVer2/resources-sse2.s

 # CHECK-NEXT:  2      8     1.00                        cvtps2pd  %xmm0, %xmm2
 # CHECK-NEXT:  2      13    1.00    *                   cvtps2pd  (%rax), %xmm2
 # CHECK-NEXT:  2      13    1.00                        cvtsd2si  %xmm0, %ecx
 # CHECK-NEXT:  2      13    1.00                        cvtsd2si  %xmm0, %rcx
 # CHECK-NEXT:  2      18    1.00    *                   cvtsd2si  (%rax), %ecx
 # CHECK-NEXT:  2      18    1.00    *                   cvtsd2si  (%rax), %rcx
 # CHECK-NEXT:  1      4     1.00                        cvtsd2ss  %xmm0, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   cvtsd2ss  (%rax), %xmm2
-# CHECK-NEXT:  2      4     1.00                        cvtsi2sdl %ecx, %xmm2
+# CHECK-NEXT:  2      14    1.00                        cvtsi2sdl %ecx, %xmm2
 # CHECK-NEXT:  2      13    1.00                        cvtsi2sdq %rcx, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   cvtsi2sdl (%rax), %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   cvtsi2sdl (%rax), %xmm2
 # CHECK-NEXT:  1      4     1.00                        cvtss2sd  %xmm0, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   cvtss2sd  (%rax), %xmm2
 # CHECK-NEXT:  2      8     1.00                        cvttpd2dq %xmm0, %xmm2
 # CHECK-NEXT:  2      13    1.00    *                   cvttpd2dq (%rax), %xmm2
 # CHECK-NEXT:  2      6     1.00                        cvttpd2pi %xmm0, %mm2

 # CHECK-NEXT:  1      7     0.50    *                   pcmpeqw (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pcmpgtb %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pcmpgtb (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pcmpgtd %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pcmpgtd (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pcmpgtw %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pcmpgtw (%rax), %xmm2
 # CHECK-NEXT:  2      13    1.00                        pextrw  $1, %xmm0, %ecx
-# CHECK-NEXT:  2      2     0.50                        pinsrw  $1, %eax, %xmm0
+# CHECK-NEXT:  2      12    0.50                        pinsrw  $1, %eax, %xmm0
 # CHECK-NEXT:  2      6     0.50    *                   pinsrw  $1, (%rax), %xmm0
 # CHECK-NEXT:  1      4     1.00                        pmaddwd %xmm0, %xmm2
 # CHECK-NEXT:  1      9     1.00    *                   pmaddwd (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pmaxsw  %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pmaxsw  (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pmaxub  %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pmaxub  (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pminsw  %xmm0, %xmm2

llvm/trunk/test/tools/llvm-mca/X86/BdVer2/resources-sse41.s

 # CHECK-NEXT:  2      13    1.00           *            pextrb  $1, %xmm0, (%rax)
 # CHECK-NEXT:  2      13    1.00                        pextrd  $1, %xmm0, %ecx
 # CHECK-NEXT:  2      13    1.00           *            pextrd  $1, %xmm0, (%rax)
 # CHECK-NEXT:  2      13    1.00                        pextrq  $1, %xmm0, %rcx
 # CHECK-NEXT:  2      13    1.00           *            pextrq  $1, %xmm0, (%rax)
 # CHECK-NEXT:  2      13    1.00           *            pextrw  $1, %xmm0, (%rax)
 # CHECK-NEXT:  2      4     1.00                        phminposuw  %xmm0, %xmm2
 # CHECK-NEXT:  2      9     1.00    *                   phminposuw  (%rax), %xmm2
-# CHECK-NEXT:  2      2     0.50                        pinsrb  $1, %eax, %xmm1
+# CHECK-NEXT:  2      12    0.50                        pinsrb  $1, %eax, %xmm1
 # CHECK-NEXT:  2      6     0.50    *                   pinsrb  $1, (%rax), %xmm1
-# CHECK-NEXT:  2      2     0.50                        pinsrd  $1, %eax, %xmm1
+# CHECK-NEXT:  2      12    0.50                        pinsrd  $1, %eax, %xmm1
 # CHECK-NEXT:  2      6     0.50    *                   pinsrd  $1, (%rax), %xmm1
-# CHECK-NEXT:  2      2     0.50                        pinsrq  $1, %rax, %xmm1
+# CHECK-NEXT:  2      12    0.50                        pinsrq  $1, %rax, %xmm1
 # CHECK-NEXT:  2      6     0.50    *                   pinsrq  $1, (%rax), %xmm1
 # CHECK-NEXT:  1      2     0.50                        pmaxsb  %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pmaxsb  (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pmaxsd  %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pmaxsd  (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pmaxud  %xmm0, %xmm2
 # CHECK-NEXT:  1      7     0.50    *                   pmaxud  (%rax), %xmm2
 # CHECK-NEXT:  1      2     0.50                        pmaxuw  %xmm0, %xmm2