[WebAssembly] Lower SCALAR_TO_VECTOR to splats

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

240

Do we need truncation in these cases?

llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll

5

Adding DAG printed by -debug or some explanation on which part of the code becomes scalar_to_vector might help reading.

8

No need for -wasm

[tlively]

• Address comments

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

240

I don't think so. This should hopefully only extend arguments of the lane element type. These may be legalized to i32, but as far as I can tell the splat instructions just do the masking implicitly anyway.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

240

Ah, right. Thanks.

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 
 defm "" : Splat<v16i8, "i8x16", I32, splat16, 4>;
 defm "" : Splat<v8i16, "i16x8", I32, splat8, 8>;
 defm "" : Splat<v4i32, "i32x4", I32, splat4, 12>;
 defm "" : Splat<v2i64, "i64x2", I64, splat2, 15>;
 defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
 defm "" : Splat<v2f64, "f64x2", F64, splat2, 21>;
 
+// scalar_to_vector leaves high lanes undefined, so can be a splat
+class ScalarSplatPat<ValueType vec_t, ValueType lane_t,
+                     WebAssemblyRegClass reg_t> :
+  Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))),
+      (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>;
+
+def : ScalarSplatPat<v16i8, i32, I32>;
+def : ScalarSplatPat<v8i16, i32, I32>;
+def : ScalarSplatPat<v4i32, i32, I32>;
+def : ScalarSplatPat<v2i64, i64, I64>;
+def : ScalarSplatPat<v4f32, f32, F32>;
+def : ScalarSplatPat<v2f64, f64, F64>;
+
 //===----------------------------------------------------------------------===//
 // Accessing lanes
 //===----------------------------------------------------------------------===//
 
 // Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
 multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
                        WebAssemblyRegClass reg_t, bits<32> simdop,
                        string suffix = "", SDNode extract = vector_extract> {

llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll

+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
+
+; Test that scalar_to_vector is lowered into a splat correctly.
+; TODO: find small test cases that produce scalar_to_vector dag nodes
+; to make this test more readable and comprehensive.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown-wasm"
+
+; CHECK-LABEL: foo:
+; CHECK: i32x4.splat
+define void @foo() {
+entry:
+  %a = load <2 x i16>, <2 x i16>* undef, align 1
+  %b = shufflevector <2 x i16> %a, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %0 = bitcast <8 x i16> %b to <16 x i8>
+  %shuffle.i214 = shufflevector <16 x i8> %0, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+  %1 = bitcast <16 x i8> %shuffle.i214 to <8 x i16>
+  %add82 = add <8 x i16> %1, zeroinitializer
+  %2 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> %add82
+  %3 = bitcast <8 x i16> %2 to <16 x i8>
+  %shuffle.i204 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+  %4 = bitcast <16 x i8> %shuffle.i204 to <8 x i16>
+  %dst2.0.vec.extract = shufflevector <8 x i16> %4, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  store <4 x i16> %dst2.0.vec.extract, <4 x i16>* undef, align 1
+  ret void
+}