Page MenuHomePhabricator

[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
ClosedPublic

Authored by asb on Jan 23 2019, 5:56 AM.

Details

Summary

Follow the same custom legalisation strategy as used in D57085 for variable-length shifts (see that patch summary for more discussion). Although we may lose out on some late-stage DAG combines, I think this custom legalisation strategy is ultimately easier to reason about.

There are some codegen changes in rv64m-exhaustive-w-insts.ll but they are all neutral in terms of the number of instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

asb created this revision.Jan 23 2019, 5:56 AM

Adding target-specific nodes for this is a little unfortunate, but seems reasonable.

lib/Target/RISCV/RISCVInstrInfoM.td
66 ↗(On Diff #183092)

Since you have a custom DAG node, you might as well implement ComputeNumSignBitsForTargetNode instead of using a pattern like this.

asb updated this revision to Diff 183255.Jan 23 2019, 11:25 PM
asb marked an inline comment as done.

Update to implement ComputeNumSignBitsForTargetNode, simplifying the patterns in RISCVInstrInfoM.td. Thanks for the review feedback.

efriedma accepted this revision.Jan 24 2019, 11:16 AM
This revision is now accepted and ready to land.Jan 24 2019, 11:16 AM
This revision was automatically updated to reflect the committed changes.