GlobalISel: Verify load/store has a pointer input

[arsenm]

Summary

I expected this to be automatically verified, but it seems
nothing uses that the type index was declared as a "ptype"

[aemerson]

LGTM, thanks.

[arsenm]

r352319

lib/CodeGen/MachineVerifier.cpp

case TargetOpcode::G_FCONSTANT: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     if (DstTy.isVector())
       report("Instruction cannot use a vector result type", MI);
     break;
   }
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
   case TargetOpcode::G_ZEXTLOAD:
-  case TargetOpcode::G_SEXTLOAD:
+  case TargetOpcode::G_SEXTLOAD: {
+    LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
+    if (!PtrTy.isPointer())
+      report("Generic memory instruction must access a pointer", MI);
+
     // Generic loads and stores must have a single MachineMemOperand
     // describing that access.
     if (!MI->hasOneMemOperand()) {
       report("Generic instruction accessing memory must have one mem operand",
              MI);
     } else {
       if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
           MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
         const MachineMemOperand &MMO = **MI->memoperands_begin();
         LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
         if (MMO.getSize() * 8 >= DstTy.getSizeInBits()) {
           report("Generic extload must have a narrower memory type", MI);
         }
       }
     }
 
     break;
+  }
   case TargetOpcode::G_PHI: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     if (!DstTy.isValid() ||
         !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
                      [this, &DstTy](const MachineOperand &MO) {
                        if (!MO.isReg())
                          return true;
                        LLT Ty = MRI->getType(MO.getReg());

test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir

body: |
   bb.0:
     liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
     ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
     ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:vgpr(s32) = COPY $vgpr0
-    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+    %3:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; GCN: [[C1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
     ; GCN: [[C4096:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
     %4:sgpr(s32) = G_CONSTANT i32 1
     %5:sgpr(s32) = G_CONSTANT i32 4096
 
     ; ashr ss
     ; GCN: [[SS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SGPR0]], [[SGPR1]]
bb.0:
     ; VI: [[CV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VI]], [[C4096]]
     %16:vgpr(s32) = G_ASHR %5, %15
 
     ; ashr vc
     ; GCN: [[VC:%[-1-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[C4096]], [[CV]]
     %17:vgpr(s32) = G_ASHR %16, %5
 
 
-    G_STORE %17, %3 :: (store 4 into %ir.global0)
+    G_STORE %17, %3 :: (store 4 into %ir.global0, addrspace 1)
 
 ...
 ---

test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir

 # GCN: [[A:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 # GCN: [[B:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
 # GCN: FLAT_STORE_DWORD [[B]], [[A]]
 
 body: |
   bb.0:
     liveins: $sgpr0, $vgpr3_vgpr4
     %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s64) = COPY $vgpr3_vgpr4
+    %1:vgpr(p1) = COPY $vgpr3_vgpr4
     %2:vgpr(<2 x s16>) = G_BITCAST %0
     %3:vgpr(s32) = G_BITCAST %2
-    G_STORE %3, %1 :: (store 4 into %ir.global0)
+    G_STORE %3, %1 :: (store 4 into %ir.global0, addrspace 1)
 ...
 ---

test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
 
 --- |
   define amdgpu_kernel void @constant(i32 addrspace(1)* %global0, i64 addrspace(1)* %global1) {ret void}
 ...
 ---
 
 name:            constant
 legalized:       true
 regBankSelected: true
 
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
     ; GCN-LABEL: name: constant
-    %0:vgpr(s64) = COPY $vgpr0_vgpr1
-    %1:vgpr(s64) = COPY $vgpr2_vgpr3
+    %0:vgpr(p1) = COPY $vgpr0_vgpr1
+    %1:vgpr(p1) = COPY $vgpr2_vgpr3
 
     ; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1
     %2:sreg_32(s32) = G_CONSTANT i32 1
 
     ; GCN: [[LO0:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
     ; GCN: [[HI0:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
     ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1
     %3:sgpr(s64) = G_CONSTANT i64 4294967296
bb.0:
     ; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1065353216
     %8:vgpr(s32) = G_FCONSTANT float 1.0
 
     ; GCN: [[LO3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
     ; GCN: [[HI3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248
     ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
     %9:vgpr(s64) = G_FCONSTANT double 1.0
 
-    G_STORE %2, %0 :: (volatile store 4 into %ir.global0)
-    G_STORE %4, %0 :: (volatile store 4 into %ir.global0)
-    G_STORE %6, %0 :: (volatile store 4 into %ir.global0)
-    G_STORE %8, %0 :: (volatile store 4 into %ir.global0)
-    G_STORE %3, %1 :: (volatile store 8 into %ir.global1)
-    G_STORE %5, %1 :: (volatile store 8 into %ir.global1)
-    G_STORE %7, %1 :: (volatile store 8 into %ir.global1)
-    G_STORE %9, %1 :: (volatile store 8 into %ir.global1)
+    G_STORE %2, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
+    G_STORE %4, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
+    G_STORE %6, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
+    G_STORE %8, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
+    G_STORE %3, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
+    G_STORE %5, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
+    G_STORE %7, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
+    G_STORE %9, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
 ...
 ---

test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

 body: |
   bb.0:
     liveins: $sgpr2_sgpr3
     ; GCN-LABEL: name: copy
     ; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
     ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: FLAT_STORE_DWORD [[COPY1]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr
-    %0:sgpr(s64) = COPY $sgpr2_sgpr3
-    %1:vgpr(s64) = COPY %0
+    %0:sgpr(p1) = COPY $sgpr2_sgpr3
+    %1:vgpr(p1) = COPY %0
     %2:vgpr(s32) = G_IMPLICIT_DEF
     G_STORE %2, %1 :: (store 4 into %ir.global0)
 ...
 ---

test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir

 
 # GCN-LABEL: name: fadd
 body: |
   bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s32) = COPY $vgpr0
     %2:vgpr(s32) = COPY $vgpr1
-    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+    %3:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; fadd vs
     ; GCN: V_ADD_F32_e64
     %4:vgpr(s32) = G_FADD %1, %0
 
     ; fadd sv
     ; GCN: V_ADD_F32_e64
     %5:vgpr(s32) = G_FADD %0, %1

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

 
 # GCN-LABEL: name: fmul
 body: |
   bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s32) = COPY $vgpr0
     %2:vgpr(s32) = COPY $vgpr1
-    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+    %3:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; fmul vs
     ; GCN: V_MUL_F32_e64
     %4:vgpr(s32) = G_FMUL %1, %0
 
     ; fmul sv
     ; GCN: V_MUL_F32_e64
     %5:vgpr(s32) = G_FMUL %0, %1
 
     ; fmul vv
     ; GCN: V_MUL_F32_e64
     %6:vgpr(s32) = G_FMUL %1, %2
 
-    G_STORE %4, %3 :: (store 4 into %ir.global0)
-    G_STORE %5, %3 :: (store 4 into %ir.global0)
-    G_STORE %6, %3 :: (store 4 into %ir.global0)
+    G_STORE %4, %3 :: (store 4 into %ir.global0, addrspace 1)
+    G_STORE %5, %3 :: (store 4 into %ir.global0, addrspace 1)
+    G_STORE %6, %3 :: (store 4 into %ir.global0, addrspace 1)
 ...
 ---

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
 
     ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
     %0:sgpr(s32) = COPY $sgpr0
 
     ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr0
 
-    %2:vgpr(s64) = COPY $vgpr3_vgpr4
+    %2:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; fptoui s
     ; GCN: V_CVT_U32_F32_e64 0, [[SGPR]], 0, 0
     %3:vgpr(s32) = G_FPTOUI %0
 
     ; fptoui v
     ; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
     %4:vgpr(s32) = G_FPTOUI %1
 
     G_STORE %3, %2 :: (store 4 into %ir.global0)
     G_STORE %4, %2 :: (store 4 into %ir.global0)
 ...
 ---

test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
 
 ---
 
 name:            implicit_def_s32
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     liveins: $vgpr3_vgpr4
     ; GCN-LABEL: name: implicit_def_s32
     ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN: FLAT_STORE_DWORD [[COPY]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr
-    %0:vgpr(s64) = COPY $vgpr3_vgpr4
+    %0:vgpr(p1) = COPY $vgpr3_vgpr4
     %1:vgpr(s32) = G_IMPLICIT_DEF
-    G_STORE %1, %0 :: (store 4)
+    G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
 ---
 
 name:            implicit_def_s64
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     liveins: $vgpr3_vgpr4
     ; GCN-LABEL: name: implicit_def_s64
     ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: FLAT_STORE_DWORDX2 [[COPY]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr
-    %0:vgpr(s64) = COPY $vgpr3_vgpr4
+    %0:vgpr(p1) = COPY $vgpr3_vgpr4
     %1:vgpr(s64) = G_IMPLICIT_DEF
-    G_STORE %1, %0 :: (store 8)
+    G_STORE %1, %0 :: (store 8, addrspace 1)
 ---
 
 ---
 
 name:            implicit_def_p0
 legalized:       true
 regBankSelected: true
 

 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_def_p1
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p1) = G_IMPLICIT_DEF
     %1:vgpr(s32) = G_CONSTANT 4
-    G_STORE %1, %0 :: (store 4)
+    G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
 ---
 
 name:            implicit_def_p3
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_def_p3
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p3) = G_IMPLICIT_DEF
     %1:vgpr(s32) = G_CONSTANT 4
-    G_STORE %1, %0 :: (store 4)
+    G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
 ---
 
 name:            implicit_def_p4
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
     ; GCN-LABEL: name: implicit_def_p4
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p4) = G_IMPLICIT_DEF
     %1:vgpr(s32) = G_CONSTANT 4
-    G_STORE %1, %0 :: (store 4)
+    G_STORE %1, %0 :: (store 4, addrspace 1)
 ...

test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir

body: |
   bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
     ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
     ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s32) = COPY $vgpr0
     %2:vgpr(s32) = COPY $vgpr1
-    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+    %3:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; GCN: [[SGPR64_0:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
     ; GCN: [[VGPR64_0:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
     ; GCN: [[VGPR64_1:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
     %10:sgpr(s64) = COPY $sgpr10_sgpr11
     %11:vgpr(s64) = COPY $vgpr10_vgpr11
     %12:vgpr(s64) = COPY $vgpr12_vgpr13
 

test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir

body: |
   bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
     ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
     ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     %0:sgpr(s32) = COPY $sgpr0
     %1:vgpr(s32) = COPY $vgpr0
     %2:vgpr(s32) = COPY $vgpr1
-    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+    %3:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; GCN: [[SGPR64_0:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
     ; GCN: [[VGPR64_0:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
     ; GCN: [[VGPR64_1:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
     %10:sgpr(s64) = COPY $sgpr10_sgpr11
     %11:vgpr(s64) = COPY $vgpr10_vgpr11
     %12:vgpr(s64) = COPY $vgpr12_vgpr13
 

test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

body: |
   bb.0:
     liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
     ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
     ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:vgpr(s32) = COPY $vgpr0
-    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+    %3:vgpr(p1) = COPY $vgpr3_vgpr4
     %4:sgpr(s32) = G_CONSTANT i32 1
     %5:sgpr(s32) = G_CONSTANT i32 4096
 
     ; or ss
     ; GCN: [[SS:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[SGPR0]], [[SGPR1]]
     %6:sgpr(s32) = G_OR %0, %1
 
     ; or vs
     ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VGPR0]]
     %7:vgpr(s32) = G_OR %2, %6
 
     ; or sv
     ; GCN: [[SV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VS]]
     %8:vgpr(s32) = G_OR %6, %7
 
     ; or vv
     ; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SV]], [[VGPR0]]
     %9:vgpr(s32) = G_OR %8, %2
 
-    G_STORE %9, %3 :: (store 4 into %ir.global0)
+    G_STORE %9, %3 :: (store 4 into %ir.global0, addrspace 1)
 
 ...
 ---

test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir

bb.0:
     liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
 
     ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
     %0:sgpr(s32) = COPY $sgpr0
 
     ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr0
 
-    %2:vgpr(s64) = COPY $vgpr3_vgpr4
+    %2:vgpr(p1) = COPY $vgpr3_vgpr4
 
     ; sitofp s
     ; GCN: V_CVT_F32_I32_e64 [[SGPR]], 0, 0
     %3:vgpr(s32) = G_SITOFP %0
 
     ; sitofp v
     ; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0
     %4:vgpr(s32) = G_SITOFP %1
 
     G_STORE %3, %2 :: (store 4 into %ir.global0)
     G_STORE %4, %2 :: (store 4 into %ir.global0)
 ...
 ---

test/CodeGen/MIR/AArch64/invalid-extload.mir

-# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s 2>&1 | FileCheck %s
-
-# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
-# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
-# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
-# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
-# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
-# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
-
----
-name: invalid_extload_memory_sizes
-body: |
-  bb.0:
-
-    %0:_(p0) = COPY $x0
-    %1:_(s64) = G_ZEXTLOAD %0(p0) :: (load 8)
-    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 16)
-    %3:_(s64) = G_SEXTLOAD %0(p0) :: (load 8)
-    %4:_(s64) = G_SEXTLOAD %0(p0) :: (load 16)
-    %5:_(s64) = G_ZEXTLOAD %0(p0)
-    %6:_(s64) = G_SEXTLOAD %0(p0)
-
-...

test/Verifier/test_g_load.mir

+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_load
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    ; CHECK: Bad machine code: Generic memory instruction must access a pointer
+    %0:_(s64) = G_CONSTANT i32 0
+    %1:_(s32) = G_LOAD %0 :: (load 4)
+
+...

test/Verifier/test_g_sextload.mir

+# RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_sextload
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    ; CHECK: Bad machine code: Generic memory instruction must access a pointer
+    %0:_(s64) = G_CONSTANT i32 0
+    %1:_(s32) = G_SEXTLOAD %0 :: (load 1)
+
+    ; CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+    %2:_(p0) = G_IMPLICIT_DEF
+    %3:_(s64) = G_SEXTLOAD %2
+
+    ; CHECK: Bad machine code: Generic extload must have a narrower memory type
+    ; CHECK: Bad machine code: Generic extload must have a narrower memory type
+
+    %4:_(s64) = G_SEXTLOAD %2 :: (load 8)
+    %5:_(s64) = G_SEXTLOAD %2 :: (load 16)
+
+...

test/Verifier/test_g_store.mir

+# RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_store
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    ; CHECK: Bad machine code: Generic memory instruction must access a pointer
+    %0:_(s64) = G_CONSTANT i32 0
+    %1:_(s32) = G_CONSTANT i32 1
+    G_STORE %1, %0 :: (store 4)
+
+...

test/Verifier/test_g_zextload.mir

+# RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_zextload
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    ; CHECK: Bad machine code: Generic memory instruction must access a pointer
+    %0:_(s64) = G_CONSTANT i32 0
+    %1:_(s32) = G_ZEXTLOAD %0 :: (load 1)
+
+    ; CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+    %2:_(p0) = G_IMPLICIT_DEF
+    %3:_(s64) = G_ZEXTLOAD %2
+
+    ; CHECK: Bad machine code: Generic extload must have a narrower memory type
+    ; CHECK: Bad machine code: Generic extload must have a narrower memory type
+
+    %4:_(s64) = G_ZEXTLOAD %2 :: (load 8)
+    %5:_(s64) = G_ZEXTLOAD %2 :: (load 16)
+
+...