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Differential D56861

AMDGPU/GlobalISel: Cleanup legality for extensions
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Authored by arsenm on Jan 17 2019, 9:03 AM.

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Reviewers
rampitec
tstellar

Diff Detail

Event Timeline

arsenm created this revision.Jan 17 2019, 9:03 AM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptJan 17 2019, 9:03 AM
arsenm updated this revision to Diff 182310.Jan 17 2019, 9:15 AM

Attach test

tstellar accepted this revision.Jan 17 2019, 9:44 AM

LGTM.

This revision is now accepted and ready to land.Jan 17 2019, 9:44 AM
arsenm closed this revision.Jan 20 2019, 10:34 AM

r351691

Herald added a subscriber: volkan. · View Herald TranscriptJan 20 2019, 10:34 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
13 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
16 lines
34 lines
16 lines
16 lines

Diff 182310

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
getActionDefinitionsBuilder( getActionDefinitionsBuilder(
{ G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA}) { G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})
.legalFor({S32, S64}); .legalFor({S32, S64});
getActionDefinitionsBuilder(G_FPTRUNC) getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor({{S32, S64}}); .legalFor({{S32, S64}});
getActionDefinitionsBuilder(G_FPEXT)
.legalFor({{S64, S32}, {S32, S16}})
.lowerFor({{S64, S16}}); // FIXME: Implement
// Use actual fsub instruction // Use actual fsub instruction
setAction({G_FSUB, S32}, Legal); setAction({G_FSUB, S32}, Legal);
// Must use fadd + fneg // Must use fadd + fneg
setAction({G_FSUB, S64}, Lower); setAction({G_FSUB, S64}, Lower);
setAction({G_FCMP, S1}, Legal); setAction({G_FCMP, S1}, Legal);
setAction({G_FCMP, 1, S32}, Legal); setAction({G_FCMP, 1, S32}, Legal);
setAction({G_FCMP, 1, S64}, Legal); setAction({G_FCMP, 1, S64}, Legal);
getActionDefinitionsBuilder(G_ANYEXT) getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalFor({{S32, S16}, {S64, S32}, {S64, S16}}); .legalFor({{S64, S32}, {S32, S16}, {S64, S16}});
getActionDefinitionsBuilder(G_SEXT)
.legalFor({{S64, S32}});
getActionDefinitionsBuilder(G_ZEXT)
.legalFor({{S64, S32}});
setAction({G_FPTOSI, S32}, Legal); setAction({G_FPTOSI, S32}, Legal);
setAction({G_FPTOSI, 1, S32}, Legal); setAction({G_FPTOSI, 1, S32}, Legal);
setAction({G_SITOFP, S32}, Legal); setAction({G_SITOFP, S32}, Legal);
setAction({G_SITOFP, 1, S32}, Legal); setAction({G_SITOFP, 1, S32}, Legal);
setAction({G_UITOFP, S32}, Legal); setAction({G_UITOFP, S32}, Legal);
▲ Show 20 Lines • Show All 245 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_anyext_i32_to_i64 name: test_anyext_s32_to_s64
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_i32_to_i64 ; CHECK-LABEL: name: test_anyext_s32_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s64) = G_ANYEXT %0 %1:_(s64) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_anyext_i16_to_i64 name: test_anyext_s16_to_s64
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_i16_to_i64 ; CHECK-LABEL: name: test_anyext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s64) = G_ANYEXT %1 %2:_(s64) = G_ANYEXT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_anyext_i16_to_i32 name: test_anyext_s16_to_s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_i16_to_i32 ; CHECK-LABEL: name: test_anyext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_anyext_i1_to_i32 name: test_anyext_i1_to_s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_i1_to_i32 ; CHECK-LABEL: name: test_anyext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0 %1:_(s1) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_fpext_f16_to_f32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fpext_f16_to_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; CHECK: $vgpr0 = COPY [[FPEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_FPEXT %1
$vgpr0 = COPY %2
...
---
name: test_fpext_f32_to_f64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fpext_f32_to_f64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[FPEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = G_FPEXT %0
$vgpr0_vgpr1 = COPY %1
...

test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_sext_i32_to_i64 name: test_sext_s32_to_s64
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_i32_to_i64 ; CHECK-LABEL: name: test_sext_s32_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32) ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s64) = G_SEXT %0 %1:_(s64) = G_SEXT %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_sext_i16_to_i64 name: test_sext_s16_to_s64
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_i16_to_i64 ; CHECK-LABEL: name: test_sext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s64) = G_SEXT %1 %2:_(s64) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_sext_i16_to_i32 name: test_sext_s16_to_s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_i16_to_i32 ; CHECK-LABEL: name: test_sext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[ASHR]](s32) ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_sext_i1_to_i32 name: test_sext_i1_to_s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_i1_to_i32 ; CHECK-LABEL: name: test_sext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[ASHR]](s32) ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0 %1:_(s1) = G_TRUNC %0
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: test_zext_i32_to_i64 name: test_zext_s32_to_s64
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_zext_i32_to_i64 ; CHECK-LABEL: name: test_zext_s32_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s64) = G_ZEXT %0 %1:_(s64) = G_ZEXT %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_zext_i16_to_i64 name: test_zext_s16_to_s64
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_zext_i16_to_i64 ; CHECK-LABEL: name: test_zext_s16_to_s64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s64) = G_ZEXT %1 %2:_(s64) = G_ZEXT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_zext_i16_to_i32 name: test_zext_s16_to_s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_zext_i16_to_i32 ; CHECK-LABEL: name: test_zext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32) ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_zext_i1_to_i32 name: test_zext_i1_to_s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_zext_i1_to_i32 ; CHECK-LABEL: name: test_zext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32) ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0 %1:_(s1) = G_TRUNC %0
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...