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Differential D56691

[Nios2] Remove Nios2 backend
ClosedPublic

Authored by craig.topper on Jan 14 2019, 5:23 PM.

Details

Reviewers
hans
chandlerc
eli.friedman
efriedma
Commits
rG99fcbf67d04d: [Nios2] Remove Nios2 backend
rL351231: [Nios2] Remove Nios2 backend
Summary

As mentioned here http://lists.llvm.org/pipermail/llvm-dev/2019-January/129121.html This backend is incomplete and has not been maintained in several months.

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.Jan 14 2019, 5:23 PM
Herald added subscribers: dexonsmith, mgorny. · View Herald TranscriptJan 14 2019, 5:23 PM
chandlerc accepted this revision.Jan 14 2019, 5:37 PM

LGTM as a patch provided the -dev thread concludes on removing it (but hold off on submitting until that's clear obviously).

This revision is now accepted and ready to land.Jan 14 2019, 5:37 PM
efriedma accepted this revision.Jan 14 2019, 5:53 PM
efriedma added a subscriber: efriedma.

Looks like the backend is incomplete, and nobody has made any substantial changes in a year; clearly a candidate to be removed. LGTM (but give it a few days in case someone objects)

For reference, there are currently four experimental targets in trunk: ARC, AVR, Nios2, and RISCV.

Closed by commit rL351231: [Nios2] Remove Nios2 backend (authored by ctopper). · Explain WhyJan 15 2019, 12:04 PM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: kristina. · View Herald TranscriptJan 15 2019, 12:04 PM

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
ADT/
1 line
lib/
Support/
11 lines
Target/
1 line
Nios2/
30 lines
InstPrinter/
1 line
23 lines
49 lines
66 lines
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MCTargetDesc/
9 lines
26 lines
81 lines
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97 lines
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26 lines
18 lines
30 lines
TargetInfo/
1 line
23 lines
24 lines
test/
CodeGen/
Nios2/
19 lines
3 lines
27 lines
10 lines
9 lines
26 lines
11 lines
utils/
gn/
secondary/
clang/
lib/
Basic/
1 line

Diff 181849

llvm/trunk/include/llvm/ADT/Triple.h

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines enum ArchType {
bpfel, // eBPF or extended BPF or 64-bit BPF (little endian) bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian) bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
hexagon, // Hexagon: hexagon hexagon, // Hexagon: hexagon
mips, // MIPS: mips, mipsallegrex, mipsr6 mips, // MIPS: mips, mipsallegrex, mipsr6
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6 mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
msp430, // MSP430: msp430 msp430, // MSP430: msp430
nios2, // NIOSII: nios2
ppc, // PPC: powerpc ppc, // PPC: powerpc
ppc64, // PPC64: powerpc64, ppu ppc64, // PPC64: powerpc64, ppu
ppc64le, // PPC64LE: powerpc64le ppc64le, // PPC64LE: powerpc64le
r600, // R600: AMD GPUs HD2XXX - HD6XXX r600, // R600: AMD GPUs HD2XXX - HD6XXX
amdgcn, // AMDGCN: AMD GCN GPUs amdgcn, // AMDGCN: AMD GCN GPUs
riscv32, // RISC-V (32-bit): riscv32 riscv32, // RISC-V (32-bit): riscv32
riscv64, // RISC-V (64-bit): riscv64 riscv64, // RISC-V (64-bit): riscv64
sparc, // Sparc: sparc sparc, // Sparc: sparc
▲ Show 20 Lines • Show All 772 Lines • Show Last 20 Lines

llvm/trunk/lib/Support/Triple.cpp

Show All 29 LinesStringRef Triple::getArchTypeName(ArchType Kind) {
case bpfel: return "bpfel"; case bpfel: return "bpfel";
case bpfeb: return "bpfeb"; case bpfeb: return "bpfeb";
case hexagon: return "hexagon"; case hexagon: return "hexagon";
case mips: return "mips"; case mips: return "mips";
case mipsel: return "mipsel"; case mipsel: return "mipsel";
case mips64: return "mips64"; case mips64: return "mips64";
case mips64el: return "mips64el"; case mips64el: return "mips64el";
case msp430: return "msp430"; case msp430: return "msp430";
case nios2: return "nios2";
case ppc64: return "powerpc64"; case ppc64: return "powerpc64";
case ppc64le: return "powerpc64le"; case ppc64le: return "powerpc64le";
case ppc: return "powerpc"; case ppc: return "powerpc";
case r600: return "r600"; case r600: return "r600";
case amdgcn: return "amdgcn"; case amdgcn: return "amdgcn";
case riscv32: return "riscv32"; case riscv32: return "riscv32";
case riscv64: return "riscv64"; case riscv64: return "riscv64";
case sparc: return "sparc"; case sparc: return "sparc";
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 LinesStringRef Triple::getArchTypePrefix(ArchType Kind) {
case ppc64le: case ppc64le:
case ppc: return "ppc"; case ppc: return "ppc";
case mips: case mips:
case mipsel: case mipsel:
case mips64: case mips64:
case mips64el: return "mips"; case mips64el: return "mips";
case nios2: return "nios2";
case hexagon: return "hexagon"; case hexagon: return "hexagon";
case amdgcn: return "amdgcn"; case amdgcn: return "amdgcn";
case r600: return "r600"; case r600: return "r600";
case bpfel: case bpfel:
case bpfeb: return "bpf"; case bpfeb: return "bpf";
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines return StringSwitch<Triple::ArchType>(Name)
.Case("armeb", armeb) .Case("armeb", armeb)
.Case("avr", avr) .Case("avr", avr)
.StartsWith("bpf", BPFArch) .StartsWith("bpf", BPFArch)
.Case("mips", mips) .Case("mips", mips)
.Case("mipsel", mipsel) .Case("mipsel", mipsel)
.Case("mips64", mips64) .Case("mips64", mips64)
.Case("mips64el", mips64el) .Case("mips64el", mips64el)
.Case("msp430", msp430) .Case("msp430", msp430)
.Case("nios2", nios2)
.Case("ppc64", ppc64) .Case("ppc64", ppc64)
.Case("ppc32", ppc) .Case("ppc32", ppc)
.Case("ppc", ppc) .Case("ppc", ppc)
.Case("ppc64le", ppc64le) .Case("ppc64le", ppc64le)
.Case("r600", r600) .Case("r600", r600)
.Case("amdgcn", amdgcn) .Case("amdgcn", amdgcn)
.Case("riscv32", riscv32) .Case("riscv32", riscv32)
.Case("riscv64", riscv64) .Case("riscv64", riscv64)
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines auto AT = StringSwitch<Triple::ArchType>(ArchName)
.Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6", .Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6",
"mipsr6", Triple::mips) "mipsr6", Triple::mips)
.Cases("mipsel", "mipsallegrexel", "mipsisa32r6el", "mipsr6el", .Cases("mipsel", "mipsallegrexel", "mipsisa32r6el", "mipsr6el",
Triple::mipsel) Triple::mipsel)
.Cases("mips64", "mips64eb", "mipsn32", "mipsisa64r6", .Cases("mips64", "mips64eb", "mipsn32", "mipsisa64r6",
"mips64r6", "mipsn32r6", Triple::mips64) "mips64r6", "mipsn32r6", Triple::mips64)
.Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el", .Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el",
"mipsn32r6el", Triple::mips64el) "mipsn32r6el", Triple::mips64el)
.Case("nios2", Triple::nios2)
.Case("r600", Triple::r600) .Case("r600", Triple::r600)
.Case("amdgcn", Triple::amdgcn) .Case("amdgcn", Triple::amdgcn)
.Case("riscv32", Triple::riscv32) .Case("riscv32", Triple::riscv32)
.Case("riscv64", Triple::riscv64) .Case("riscv64", Triple::riscv64)
.Case("hexagon", Triple::hexagon) .Case("hexagon", Triple::hexagon)
.Cases("s390x", "systemz", Triple::systemz) .Cases("s390x", "systemz", Triple::systemz)
.Case("sparc", Triple::sparc) .Case("sparc", Triple::sparc)
.Case("sparcel", Triple::sparcel) .Case("sparcel", Triple::sparcel)
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Linesstatic Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
case Triple::kalimba: case Triple::kalimba:
case Triple::le32: case Triple::le32:
case Triple::le64: case Triple::le64:
case Triple::mips: case Triple::mips:
case Triple::mips64: case Triple::mips64:
case Triple::mips64el: case Triple::mips64el:
case Triple::mipsel: case Triple::mipsel:
case Triple::msp430: case Triple::msp430:
case Triple::nios2:
case Triple::nvptx: case Triple::nvptx:
case Triple::nvptx64: case Triple::nvptx64:
case Triple::ppc64le: case Triple::ppc64le:
case Triple::r600: case Triple::r600:
case Triple::renderscript32: case Triple::renderscript32:
case Triple::renderscript64: case Triple::renderscript64:
case Triple::riscv32: case Triple::riscv32:
case Triple::riscv64: case Triple::riscv64:
▲ Show 20 Lines • Show All 541 Lines • ▼ Show 20 Linesstatic unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::arc: case llvm::Triple::arc:
case llvm::Triple::arm: case llvm::Triple::arm:
case llvm::Triple::armeb: case llvm::Triple::armeb:
case llvm::Triple::hexagon: case llvm::Triple::hexagon:
case llvm::Triple::le32: case llvm::Triple::le32:
case llvm::Triple::mips: case llvm::Triple::mips:
case llvm::Triple::mipsel: case llvm::Triple::mipsel:
case llvm::Triple::nios2:
case llvm::Triple::nvptx: case llvm::Triple::nvptx:
case llvm::Triple::ppc: case llvm::Triple::ppc:
case llvm::Triple::r600: case llvm::Triple::r600:
case llvm::Triple::riscv32: case llvm::Triple::riscv32:
case llvm::Triple::sparc: case llvm::Triple::sparc:
case llvm::Triple::sparcel: case llvm::Triple::sparcel:
case llvm::Triple::tce: case llvm::Triple::tce:
case llvm::Triple::tcele: case llvm::Triple::tcele:
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 LinesTriple Triple::get32BitArchVariant() const {
case Triple::arc: case Triple::arc:
case Triple::arm: case Triple::arm:
case Triple::armeb: case Triple::armeb:
case Triple::hexagon: case Triple::hexagon:
case Triple::kalimba: case Triple::kalimba:
case Triple::le32: case Triple::le32:
case Triple::mips: case Triple::mips:
case Triple::mipsel: case Triple::mipsel:
case Triple::nios2:
case Triple::nvptx: case Triple::nvptx:
case Triple::ppc: case Triple::ppc:
case Triple::r600: case Triple::r600:
case Triple::riscv32: case Triple::riscv32:
case Triple::sparc: case Triple::sparc:
case Triple::sparcel: case Triple::sparcel:
case Triple::tce: case Triple::tce:
case Triple::tcele: case Triple::tcele:
Show All 32 LinesTriple Triple::get64BitArchVariant() const {
switch (getArch()) { switch (getArch()) {
case Triple::UnknownArch: case Triple::UnknownArch:
case Triple::arc: case Triple::arc:
case Triple::avr: case Triple::avr:
case Triple::hexagon: case Triple::hexagon:
case Triple::kalimba: case Triple::kalimba:
case Triple::lanai: case Triple::lanai:
case Triple::msp430: case Triple::msp430:
case Triple::nios2:
case Triple::r600: case Triple::r600:
case Triple::tce: case Triple::tce:
case Triple::tcele: case Triple::tcele:
case Triple::xcore: case Triple::xcore:
case Triple::sparcel: case Triple::sparcel:
case Triple::shave: case Triple::shave:
T.setArch(UnknownArch); T.setArch(UnknownArch);
break; break;
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 LinesTriple Triple::getBigEndianArchVariant() const {
case Triple::avr: case Triple::avr:
case Triple::hexagon: case Triple::hexagon:
case Triple::hsail64: case Triple::hsail64:
case Triple::hsail: case Triple::hsail:
case Triple::kalimba: case Triple::kalimba:
case Triple::le32: case Triple::le32:
case Triple::le64: case Triple::le64:
case Triple::msp430: case Triple::msp430:
case Triple::nios2:
case Triple::nvptx64: case Triple::nvptx64:
case Triple::nvptx: case Triple::nvptx:
case Triple::r600: case Triple::r600:
case Triple::riscv32: case Triple::riscv32:
case Triple::riscv64: case Triple::riscv64:
case Triple::shave: case Triple::shave:
case Triple::spir64: case Triple::spir64:
case Triple::spir: case Triple::spir:
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesbool Triple::isLittleEndian() const {
case Triple::hsail64: case Triple::hsail64:
case Triple::hsail: case Triple::hsail:
case Triple::kalimba: case Triple::kalimba:
case Triple::le32: case Triple::le32:
case Triple::le64: case Triple::le64:
case Triple::mips64el: case Triple::mips64el:
case Triple::mipsel: case Triple::mipsel:
case Triple::msp430: case Triple::msp430:
case Triple::nios2:
case Triple::nvptx64: case Triple::nvptx64:
case Triple::nvptx: case Triple::nvptx:
case Triple::ppc64le: case Triple::ppc64le:
case Triple::r600: case Triple::r600:
case Triple::riscv32: case Triple::riscv32:
case Triple::riscv64: case Triple::riscv64:
case Triple::shave: case Triple::shave:
case Triple::sparcel: case Triple::sparcel:
▲ Show 20 Lines • Show All 112 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/LLVMBuild.txt

Show All 24 Lines
AArch64 AArch64
AVR AVR
BPF BPF
Lanai Lanai
Hexagon Hexagon
MSP430 MSP430
NVPTX NVPTX
Mips Mips
Nios2
PowerPC PowerPC
RISCV RISCV
Sparc Sparc
SystemZ SystemZ
WebAssembly WebAssembly
X86 X86
XCore XCore
Show All 36 Lines

llvm/trunk/lib/Target/Nios2/CMakeLists.txt

set(LLVM_TARGET_DEFINITIONS Nios2.td)
tablegen(LLVM Nios2GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM Nios2GenCallingConv.inc -gen-callingconv)
tablegen(LLVM Nios2GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM Nios2GenInstrInfo.inc -gen-instr-info)
tablegen(LLVM Nios2GenRegisterInfo.inc -gen-register-info)
tablegen(LLVM Nios2GenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(Nios2CommonTableGen)
#Nios2CodeGen should match with LLVMBuild.txt Nios2CodeGen
add_llvm_target(Nios2CodeGen
Nios2AsmPrinter.cpp
Nios2FrameLowering.cpp
Nios2InstrInfo.cpp
Nios2ISelDAGToDAG.cpp
Nios2ISelLowering.cpp
Nios2MachineFunction.cpp
Nios2MCInstLower.cpp
Nios2RegisterInfo.cpp
Nios2Subtarget.cpp
Nios2TargetMachine.cpp
Nios2TargetObjectFile.cpp
)
#Should match with "subdirectories = InstPrinter MCTargetDesc TargetInfo" in LLVMBuild.txt
add_subdirectory(InstPrinter)
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)

llvm/trunk/lib/Target/Nios2/InstPrinter/CMakeLists.txt

add_llvm_library(LLVMNios2AsmPrinter Nios2InstPrinter.cpp)

llvm/trunk/lib/Target/Nios2/InstPrinter/LLVMBuild.txt

;===- ./lib/Target/Nios2/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = Nios2AsmPrinter
parent = Nios2
required_libraries = MC Support
add_to_library_groups = Nios2

llvm/trunk/lib/Target/Nios2/InstPrinter/Nios2InstPrinter.h

//= Nios2InstPrinter.h - Convert Nios2 MCInst to assembly syntax -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints a Nios2 MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_INSTPRINTER_NIOS2INSTPRINTER_H
#define LLVM_LIB_TARGET_NIOS2_INSTPRINTER_NIOS2INSTPRINTER_H
#include "llvm/MC/MCInstPrinter.h"
namespace llvm {
class Nios2InstPrinter : public MCInstPrinter {
public:
Nios2InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {}
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx,
const MCSubtargetInfo &STI, raw_ostream &O);
void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
raw_ostream &OS);
void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
raw_ostream &OS, const char *Modifier = nullptr);
};
} // end namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/InstPrinter/Nios2InstPrinter.cpp

//===-- Nios2InstPrinter.cpp - Convert Nios2 MCInst to assembly syntax-----===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an Nios2 MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#include "Nios2InstPrinter.h"
#include "Nios2InstrInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
#define PRINT_ALIAS_INSTR
#include "Nios2GenAsmWriter.inc"
void Nios2InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
}
void Nios2InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
// Try to print any aliases first.
if (!printAliasInstr(MI, STI, O))
printInstruction(MI, STI, O);
printAnnotation(O, Annot);
}
void Nios2InstPrinter::printOperand(const MCInst *MI, int OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
printRegName(O, Op.getReg());
return;
}
if (Op.isImm()) {
O << Op.getImm();
return;
}
assert(Op.isExpr() && "unknown operand kind in printOperand");
Op.getExpr()->print(O, &MAI, true);
}
void Nios2InstPrinter::printMemOperand(const MCInst *MI, int opNum,
const MCSubtargetInfo &STI,
raw_ostream &O, const char *Modifier) {
// Load/Store memory operands -- imm($reg)
printOperand(MI, opNum + 1, STI, O);
O << "(";
printOperand(MI, opNum, STI, O);
O << ")";
}

llvm/trunk/lib/Target/Nios2/LLVMBuild.txt

;===- ./lib/Target/Nios2/LLVMBuild.txt -------------------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
#Following comments extracted from http: // llvm.org/docs/LLVMBuild.html
[common]
subdirectories =
InstPrinter
MCTargetDesc
TargetInfo
[component_0]
#TargetGroup components are an extension of LibraryGroups, specifically for
#defining LLVM targets(which are handled specially in a few places).
type = TargetGroup
#The name of the component should always be the name of the target.(should
#match "def Nios2 : Target" in Nios2.td)
name = Nios2
#Nios2 component is located in directory Target /
parent = Target
#Whether this target defines an assembly parser, assembly printer, disassembler
#, and supports JIT compilation.They are optional.
has_asmprinter = 1
[component_1]
#component_1 is a Library type and name is Nios2CodeGen.After build it will
#in lib / libLLVMNios2CodeGen.a of your build command directory.
type = Library
name = Nios2CodeGen
#Nios2CodeGen component(Library) is located in directory Nios2 /
parent = Nios2
#If given, a list of the names of Library or LibraryGroup components which
#must also be linked in whenever this library is used.That is, the link time
#dependencies for this component.When tools are built, the build system will
#include the transitive closure of all required_libraries for the components
#the tool needs.
required_libraries = AsmPrinter
CodeGen
Core
GlobalISel
MC
Nios2AsmPrinter
Nios2Desc
Nios2Info
SelectionDAG
Support
Target
#end of required_libraries
#All LLVMBuild.txt in Target / Nios2 and subdirectory use 'add_to_library_groups
#= Nios2'
add_to_library_groups = Nios2

llvm/trunk/lib/Target/Nios2/MCTargetDesc/CMakeLists.txt

#MCTargetDesc / CMakeLists.txt
add_llvm_library(LLVMNios2Desc
Nios2AsmBackend.cpp
Nios2ELFObjectWriter.cpp
Nios2MCAsmInfo.cpp
Nios2MCExpr.cpp
Nios2MCTargetDesc.cpp
Nios2TargetStreamer.cpp)

llvm/trunk/lib/Target/Nios2/MCTargetDesc/LLVMBuild.txt

;===- ./lib/Target/Nios2/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = Nios2Desc
parent = Nios2
required_libraries = MC
Nios2AsmPrinter
Nios2Info
Support
add_to_library_groups = Nios2

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.h

//===-- Nios2AsmBackend.h - Nios2 Asm Backend ----------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the Nios2AsmBackend class.
//
//===----------------------------------------------------------------------===//
//
#ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2ASMBACKEND_H
#define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2ASMBACKEND_H
#include "MCTargetDesc/Nios2FixupKinds.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCAsmBackend.h"
namespace llvm {
class MCAssembler;
struct MCFixupKindInfo;
class Target;
class MCObjectWriter;
class Nios2AsmBackend : public MCAsmBackend {
Triple::OSType OSType;
public:
Nios2AsmBackend(const Target &T, Triple::OSType OSType)
: MCAsmBackend(support::little), OSType(OSType) {}
std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const override;
bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
uint64_t Value, bool IsResolved) const override;
Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
unsigned getNumFixupKinds() const override {
return Nios2::NumTargetFixupKinds;
}
/// MayNeedRelaxation - Check whether the given instruction may need
/// relaxation.
///
/// \param Inst - The instruction to test.
bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
/// fixupNeedsRelaxation - Target specific predicate for whether a given
/// fixup requires the associated instruction to be relaxed.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const override {
// FIXME.
llvm_unreachable("RelaxInstruction() unimplemented");
return false;
}
/// RelaxInstruction - Relax the instruction in the given fragment
/// to the next wider instruction.
///
/// \param Inst - The instruction to relax, which may be the same
/// as the output.
/// \param [out] Res On return, the relaxed instruction.
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
MCInst &Res) const override {}
}; // class Nios2AsmBackend
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.cpp

//===-- Nios2AsmBackend.cpp - Nios2 Asm Backend --------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the Nios2AsmBackend class.
//
//===----------------------------------------------------------------------===//
//
#include "MCTargetDesc/Nios2AsmBackend.h"
#include "MCTargetDesc/Nios2FixupKinds.h"
#include "MCTargetDesc/Nios2MCTargetDesc.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
using namespace llvm;
// Prepare value for the target space for it
static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value) {
unsigned Kind = Fixup.getKind();
// Add/subtract and shift
switch (Kind) {
default:
return 0;
case Nios2::fixup_Nios2_LO16:
break;
case Nios2::fixup_Nios2_HI16:
// Get the higher 16-bits. Also add 1 if bit 15 is 1.
Value = ((Value + 0x8000) >> 16) & 0xffff;
break;
}
return Value;
}
// Calculate index for Nios2 specific little endian byte order
static unsigned calculateLEIndex(unsigned i) {
assert(i <= 3 && "Index out of range!");
return (1 - i / 2) * 2 + i % 2;
}
/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
/// data fragment, at the offset specified by the fixup and following the
/// fixup kind as appropriate.
void Nios2AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target,
MutableArrayRef<char> Data, uint64_t Value,
bool IsResolved) const {
MCFixupKind Kind = Fixup.getKind();
Value = adjustFixupValue(Fixup, Value);
if (!Value)
return; // Doesn't change encoding.
// Where do we start in the object
unsigned Offset = Fixup.getOffset();
// Number of bytes we need to fixup
unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
// Grab current value, if any, from bits.
uint64_t CurVal = 0;
for (unsigned i = 0; i != NumBytes; ++i) {
unsigned Idx = calculateLEIndex(i);
CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i * 8);
}
uint64_t Mask = ((uint64_t)(-1) >> (64 - getFixupKindInfo(Kind).TargetSize));
CurVal |= Value & Mask;
// Write out the fixed up bytes back to the code/data bits.
for (unsigned i = 0; i != NumBytes; ++i) {
unsigned Idx = calculateLEIndex(i);
Data[Offset + Idx] = (uint8_t)((CurVal >> (i * 8)) & 0xff);
}
}
Optional<MCFixupKind> Nios2AsmBackend::getFixupKind(StringRef Name) const {
return StringSwitch<Optional<MCFixupKind>>(Name)
.Case("R_NIOS2_NONE", (MCFixupKind)Nios2::fixup_Nios2_32)
.Case("R_NIOS2_32", FK_Data_4)
.Default(MCAsmBackend::getFixupKind(Name));
}
//@getFixupKindInfo {
const MCFixupKindInfo &
Nios2AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[Nios2::NumTargetFixupKinds] = {
// This table *must* be in same the order of fixup_* kinds in
// Nios2FixupKinds.h.
//
// name offset bits flags
{"fixup_Nios2_32", 0, 32, 0},
{"fixup_Nios2_HI16", 0, 16, 0},
{"fixup_Nios2_LO16", 0, 16, 0}};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
return Infos[Kind - FirstTargetFixupKind];
}
std::unique_ptr<MCObjectTargetWriter>
Nios2AsmBackend::createObjectTargetWriter() const {
return createNios2ELFObjectWriter(MCELFObjectTargetWriter::getOSABI(OSType));
}
bool Nios2AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
return true;
}
// MCAsmBackend
MCAsmBackend *llvm::createNios2AsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
return new Nios2AsmBackend(T, STI.getTargetTriple().getOS());
}

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2BaseInfo.h

//===-- Nios2BaseInfo.h - Top level definitions for NIOS2 MC ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the Nios2 target useful for the compiler back-end and the MC libraries.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2BASEINFO_H
#define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2BASEINFO_H
namespace llvm {
/// Nios2FG - This namespace holds all of the target specific flags that
/// instruction info tracks.
namespace Nios2FG {
/// Target Operand Flag enum.
enum TOF {
//===------------------------------------------------------------------===//
// Nios2 Specific MachineOperand flags.
MO_NO_FLAG,
/// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
/// address.
MO_ABS_HI,
MO_ABS_LO,
};
} // namespace Nios2FG
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2ELFObjectWriter.cpp

//===-- Nios2ELFObjectWriter.cpp - Nios2 ELF Writer -----------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/Nios2FixupKinds.h"
#include "MCTargetDesc/Nios2MCExpr.h"
#include "MCTargetDesc/Nios2MCTargetDesc.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCObjectWriter.h"
using namespace llvm;
namespace {
class Nios2ELFObjectWriter : public MCELFObjectTargetWriter {
public:
Nios2ELFObjectWriter(uint8_t OSABI)
: MCELFObjectTargetWriter(false, OSABI, ELF::EM_ALTERA_NIOS2, false) {}
~Nios2ELFObjectWriter() override;
unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
const MCFixup &Fixup, bool IsPCRel) const override;
};
} // namespace
Nios2ELFObjectWriter::~Nios2ELFObjectWriter() {}
unsigned Nios2ELFObjectWriter::getRelocType(MCContext &Ctx,
const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
return 0;
}
std::unique_ptr<MCObjectTargetWriter>
llvm::createNios2ELFObjectWriter(uint8_t OSABI) {
return llvm::make_unique<Nios2ELFObjectWriter>(OSABI);
}

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2FixupKinds.h

//===-- Nios2FixupKinds.h - Nios2 Specific Fixup Entries --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2FIXUPKINDS_H
#define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2FIXUPKINDS_H
#include "llvm/MC/MCFixup.h"
namespace llvm {
namespace Nios2 {
// Although most of the current fixup types reflect a unique relocation
// one can have multiple fixup types for a given relocation and thus need
// to be uniquely named.
//
// This table *must* be in the save order of
// MCFixupKindInfo Infos[Nios2::NumTargetFixupKinds]
// in Nios2AsmBackend.cpp.
enum Fixups {
// Pure upper 32 bit fixup resulting in - R_NIOS2_32.
fixup_Nios2_32 = FirstTargetFixupKind,
// Pure upper 16 bit fixup resulting in - R_NIOS2_HI16.
fixup_Nios2_HI16,
// Pure lower 16 bit fixup resulting in - R_NIOS2_LO16.
fixup_Nios2_LO16,
// Marker
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
} // namespace Nios2
} // namespace llvm
#endif // LLVM_NIOS2_NIOS2FIXUPKINDS_H

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2MCAsmInfo.h

//===-- Nios2MCAsmInfo.h - Nios2 Asm Info ----------------------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the Nios2MCAsmInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCASMINFO_H
#define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCASMINFO_H
#include "llvm/MC/MCAsmInfoELF.h"
namespace llvm {
class Triple;
class Nios2MCAsmInfo : public MCAsmInfoELF {
void anchor() override;
public:
explicit Nios2MCAsmInfo(const Triple &TheTriple);
};
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2MCAsmInfo.cpp

//===-- Nios2MCAsmInfo.cpp - Nios2 Asm Properties -------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the declarations of the Nios2MCAsmInfo properties.
//
//===----------------------------------------------------------------------===//
#include "Nios2MCAsmInfo.h"
#include "llvm/ADT/Triple.h"
using namespace llvm;
void Nios2MCAsmInfo::anchor() {}
Nios2MCAsmInfo::Nios2MCAsmInfo(const Triple &TheTriple) {
if ((TheTriple.getArch() == Triple::nios2))
IsLittleEndian = true; // the default of IsLittleEndian is true
AlignmentIsInBytes = false;
Data16bitsDirective = "\t.2byte\t";
Data32bitsDirective = "\t.4byte\t";
Data64bitsDirective = "\t.8byte\t";
PrivateLabelPrefix = ".LC";
CommentString = "#";
ZeroDirective = "\t.space\t";
GPRel32Directive = "\t.gpword\t";
GPRel64Directive = "\t.gpdword\t";
WeakRefDirective = "\t.weak\t";
GlobalDirective = "\t.global\t";
AscizDirective = "\t.string\t";
UseAssignmentForEHBegin = true;
SupportsDebugInformation = true;
ExceptionsType = ExceptionHandling::DwarfCFI;
DwarfRegNumForCFI = true;
UsesELFSectionDirectiveForBSS = true;
}

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2MCExpr.h

//===-- Nios2MCExpr.h - Nios2 specific MC expression classes ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCEXPR_H
#define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCEXPR_H
#include "llvm/MC/MCAsmLayout.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCValue.h"
namespace llvm {
class Nios2MCExpr : public MCTargetExpr {
public:
enum Nios2ExprKind {
CEK_None,
CEK_ABS_HI,
CEK_ABS_LO,
CEK_Special,
};
private:
const Nios2ExprKind Kind;
const MCExpr *Expr;
explicit Nios2MCExpr(Nios2ExprKind Kind, const MCExpr *Expr)
: Kind(Kind), Expr(Expr) {}
public:
static const Nios2MCExpr *create(Nios2ExprKind Kind, const MCExpr *Expr,
MCContext &Ctx);
static const Nios2MCExpr *create(const MCSymbol *Symbol,
Nios2MCExpr::Nios2ExprKind Kind,
MCContext &Ctx);
/// Get the kind of this expression.
Nios2ExprKind getKind() const { return Kind; }
/// Get the child of this expression.
const MCExpr *getSubExpr() const { return Expr; }
void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
const MCFixup *Fixup) const override;
void visitUsedExpr(MCStreamer &Streamer) const override;
MCFragment *findAssociatedFragment() const override {
return getSubExpr()->findAssociatedFragment();
}
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
};
} // end namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2MCExpr.cpp

//===-- Nios2MCExpr.cpp - Nios2 specific MC expression classes ------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "Nios2.h"
#include "Nios2MCExpr.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCObjectStreamer.h"
#include "llvm/MC/MCSymbolELF.h"
using namespace llvm;
#define DEBUG_TYPE "nios2mcexpr"
const Nios2MCExpr *Nios2MCExpr::create(Nios2MCExpr::Nios2ExprKind Kind,
const MCExpr *Expr, MCContext &Ctx) {
return new (Ctx) Nios2MCExpr(Kind, Expr);
}
const Nios2MCExpr *Nios2MCExpr::create(const MCSymbol *Symbol,
Nios2MCExpr::Nios2ExprKind Kind,
MCContext &Ctx) {
const MCSymbolRefExpr *MCSym =
MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
return new (Ctx) Nios2MCExpr(Kind, MCSym);
}
void Nios2MCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
switch (Kind) {
case CEK_None:
case CEK_Special:
llvm_unreachable("CEK_None and CEK_Special are invalid");
break;
case CEK_ABS_HI:
OS << "%hiadj";
break;
case CEK_ABS_LO:
OS << "%lo";
break;
}
OS << '(';
Expr->print(OS, MAI, true);
OS << ')';
}
bool Nios2MCExpr::evaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup);
}
void Nios2MCExpr::visitUsedExpr(MCStreamer &Streamer) const {
Streamer.visitUsedExpr(*getSubExpr());
}
void Nios2MCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
switch (getKind()) {
case CEK_None:
case CEK_Special:
llvm_unreachable("CEK_None and CEK_Special are invalid");
break;
case CEK_ABS_HI:
case CEK_ABS_LO:
break;
}
}

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2MCTargetDesc.h

//===-- Nios2MCTargetDesc.h - Nios2 Target Descriptions ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Nios2 specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCTARGETDESC_H
#define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCTARGETDESC_H
#include <memory>
namespace llvm {
class MCAsmBackend;
class MCObjectTargetWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class Target;
class Triple;
class StringRef;
class raw_pwrite_stream;
Target &getTheNios2Target();
MCAsmBackend *createNios2AsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createNios2ELFObjectWriter(uint8_t OSABI);
} // namespace llvm
// Defines symbolic names for Nios2 registers. This defines a mapping from
// register name to register number.
#define GET_REGINFO_ENUM
#include "Nios2GenRegisterInfo.inc"
// Defines symbolic names for the Nios2 instructions.
#define GET_INSTRINFO_ENUM
#include "Nios2GenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "Nios2GenSubtargetInfo.inc"
#endif

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2MCTargetDesc.cpp

//===-- Nios2MCTargetDesc.cpp - Nios2 Target Descriptions -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Nios2 specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "Nios2MCTargetDesc.h"
#include "InstPrinter/Nios2InstPrinter.h"
#include "Nios2MCAsmInfo.h"
#include "Nios2TargetStreamer.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
#define GET_INSTRINFO_MC_DESC
#include "Nios2GenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "Nios2GenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "Nios2GenRegisterInfo.inc"
static MCInstrInfo *createNios2MCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitNios2MCInstrInfo(X); // defined in Nios2GenInstrInfo.inc
return X;
}
static MCRegisterInfo *createNios2MCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitNios2MCRegisterInfo(X, Nios2::R15); // defined in Nios2GenRegisterInfo.inc
return X;
}
static MCSubtargetInfo *
createNios2MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (CPU.empty() || CPU == "generic")
CPU = "nios2r1";
return createNios2MCSubtargetInfoImpl(TT, CPU, FS);
// createNios2MCSubtargetInfoImpl defined in Nios2GenSubtargetInfo.inc
}
static MCAsmInfo *createNios2MCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) {
MCAsmInfo *MAI = new Nios2MCAsmInfo(TT);
unsigned SP = MRI.getDwarfRegNum(Nios2::SP, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
MAI->addInitialFrameState(Inst);
return MAI;
}
static MCInstPrinter *createNios2MCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
const MCRegisterInfo &MRI) {
return new Nios2InstPrinter(MAI, MII, MRI);
}
static MCTargetStreamer *createNios2AsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS,
MCInstPrinter *InstPrint,
bool isVerboseAsm) {
return new Nios2TargetAsmStreamer(S, OS);
}
extern "C" void LLVMInitializeNios2TargetMC() {
Target *T = &getTheNios2Target();
// Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createNios2MCAsmInfo);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createNios2MCInstrInfo);
// Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createNios2MCRegisterInfo);
// Register the asm target streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createNios2AsmTargetStreamer);
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(*T, createNios2MCSubtargetInfo);
// Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createNios2MCInstPrinter);
// Register the asm backend.
TargetRegistry::RegisterMCAsmBackend(*T, createNios2AsmBackend);
}

llvm/trunk/lib/Target/Nios2/MCTargetDesc/Nios2TargetStreamer.cpp

//===-- Nios2TargetStreamer.cpp - Nios2 Target Streamer Methods -----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Nios2 specific target streamer methods.
//
//===----------------------------------------------------------------------===//
#include "Nios2TargetStreamer.h"
using namespace llvm;
Nios2TargetStreamer::Nios2TargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
Nios2TargetAsmStreamer::Nios2TargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS)
: Nios2TargetStreamer(S) {}

llvm/trunk/lib/Target/Nios2/Nios2.h

//===-- Nios2.h - Top-level interface for Nios2 representation --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in
// the LLVM Nios2 back-end.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2_H
#include "MCTargetDesc/Nios2MCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class FunctionPass;
class formatted_raw_ostream;
class Nios2TargetMachine;
class AsmPrinter;
class MachineInstr;
class MCInst;
FunctionPass *createNios2ISelDag(Nios2TargetMachine &TM,
CodeGenOpt::Level OptLevel);
void LowerNios2MachineInstToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP);
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/Nios2.td

//===-- Nios2.td - Describe the Nios2 Target Machine -------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
include "Nios2RegisterInfo.td"
include "Nios2Schedule.td"
include "Nios2InstrInfo.td"
include "Nios2CallingConv.td"
//===----------------------------------------------------------------------===//
// Nios2 Subtarget features
//===----------------------------------------------------------------------===//
def FeatureNios2r1 : SubtargetFeature<"nios2r1", "Nios2ArchVersion",
"Nios2r1", "Nios2 R1 ISA Support">;
def FeatureNios2r2 : SubtargetFeature<"nios2r2", "Nios2ArchVersion",
"Nios2r2", "Nios2 R2 ISA Support">;
//===----------------------------------------------------------------------===//
// Nios2 processors supported.
//===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, Nios2GenericItineraries, Features>;
def : Proc<"nios2r1", [FeatureNios2r1]>;
def : Proc<"nios2r2", [FeatureNios2r2]>;
def Nios2InstrInfo : InstrInfo;
def Nios2AsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
}
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
def Nios2AsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
int PassSubtarget = 1;
int Variant = 0;
}
def Nios2 : Target {
// def Nios2InstrInfo : InstrInfo as before.
let InstructionSet = Nios2InstrInfo;
let AssemblyParsers = [Nios2AsmParser];
let AssemblyWriters = [Nios2AsmWriter];
}

llvm/trunk/lib/Target/Nios2/Nios2AsmPrinter.cpp

//===-- Nios2AsmPrinter.cpp - Nios2 LLVM Assembly Printer -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
// of machine-dependent LLVM code to GAS-format NIOS2 assembly language.
//
//===----------------------------------------------------------------------===//
#include "InstPrinter/Nios2InstPrinter.h"
#include "MCTargetDesc/Nios2BaseInfo.h"
#include "Nios2.h"
#include "Nios2TargetMachine.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
#define DEBUG_TYPE "nios2-asm-printer"
namespace {
class Nios2AsmPrinter : public AsmPrinter {
public:
explicit Nios2AsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)) {}
StringRef getPassName() const override { return "Nios2 Assembly Printer"; }
//- EmitInstruction() must exists or will have run time error.
void EmitInstruction(const MachineInstr *MI) override;
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O) override;
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
void EmitFunctionEntryLabel() override;
};
} // namespace
//- EmitInstruction() must exists or will have run time error.
void Nios2AsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Print out both ordinary instruction and boudle instruction
MachineBasicBlock::const_instr_iterator I = MI->getIterator();
MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
do {
if (I->isPseudo()) {
llvm_unreachable("Pseudo opcode found in EmitInstruction()");
}
MCInst TmpInst0;
LowerNios2MachineInstToMCInst(&*I, TmpInst0, *this);
EmitToStreamer(*OutStreamer, TmpInst0);
} while ((++I != E) && I->isInsideBundle()); // Delay slot check
}
// .type main,@function
//-> .ent main # @main
// main:
void Nios2AsmPrinter::EmitFunctionEntryLabel() {
OutStreamer->EmitLabel(CurrentFnSym);
}
// Print out an operand for an inline asm expression.
bool Nios2AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant,
const char *ExtraCode, raw_ostream &O) {
printOperand(MI, OpNum, O);
return false;
}
bool Nios2AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNum, unsigned AsmVariant,
const char *ExtraCode,
raw_ostream &O) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isReg() && "unexpected inline asm memory operand");
O << "($" << Nios2InstPrinter::getRegisterName(MO.getReg()) << ")";
return false;
}
void Nios2AsmPrinter::printOperand(const MachineInstr *MI, int opNum,
raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(opNum);
bool closeP = false;
if (MO.getTargetFlags())
closeP = true;
switch (MO.getTargetFlags()) {
case Nios2FG::MO_ABS_HI:
O << "%hiadj(";
break;
case Nios2FG::MO_ABS_LO:
O << "%lo(";
break;
}
switch (MO.getType()) {
case MachineOperand::MO_Register:
O << '$'
<< StringRef(Nios2InstPrinter::getRegisterName(MO.getReg())).lower();
break;
case MachineOperand::MO_Immediate:
O << MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:
MO.getMBB()->getSymbol()->print(O, MAI);
return;
case MachineOperand::MO_GlobalAddress:
getSymbol(MO.getGlobal())->print(O, MAI);
break;
case MachineOperand::MO_BlockAddress:
O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
break;
case MachineOperand::MO_ExternalSymbol:
O << MO.getSymbolName();
break;
default:
llvm_unreachable("<unknown operand type>");
}
if (closeP)
O << ")";
}
// Force static initialization.
extern "C" void LLVMInitializeNios2AsmPrinter() {
RegisterAsmPrinter<Nios2AsmPrinter> X(getTheNios2Target());
}

llvm/trunk/lib/Target/Nios2/Nios2CallingConv.td

//===- Nios2CallingConv.td - Calling Conventions for Nios2 -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// This describes the calling conventions for Nios2 architecture.
//===----------------------------------------------------------------------===//
/// CCIfSubtarget - Match if the current subtarget has a feature F.
class CCIfSubtarget<string F, CCAction A>:
CCIf<!strconcat("State.getTarget().getSubtarget<Nios2Subtarget>().", F), A>;
def CC_Nios2 : CallingConv<[
// i32 f32 arguments get passed in integer registers if there is space.
CCIfType<[i32, f32], CCAssignToReg<[R4, R5, R6, R7]>>,
// Alternatively, they are assigned to the stack in 4-byte aligned units.
CCAssignToStack<4, 4>
]>;
def RetCC_Nios2EABI : CallingConv<[
// i32 are returned in registers R2, R3
CCIfType<[i32], CCAssignToReg<[R2, R3]>>,
// In case of floating point (FPH2 instr.) also use the same register set
CCIfType<[f32], CCAssignToReg<[R2, R3]>>,
CCIfByVal<CCPassByVal<4, 4>>,
// Stack parameter slots for i32 is 32-bit words and 4-byte aligned.
CCIfType<[i32], CCAssignToStack<4, 4>>
]>;
def CSR : CalleeSavedRegs<(add RA, FP, (sequence "R%u", 16, 23))>;

llvm/trunk/lib/Target/Nios2/Nios2FrameLowering.h

//===-- Nios2FrameLowering.h - Define frame lowering for Nios2 --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2FRAMELOWERING_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2FRAMELOWERING_H
#include "Nios2.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
namespace llvm {
class Nios2Subtarget;
class Nios2FrameLowering : public TargetFrameLowering {
protected:
const Nios2Subtarget &STI;
public:
explicit Nios2FrameLowering(const Nios2Subtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0, 4),
STI(sti) {}
bool hasFP(const MachineFunction &MF) const override;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
};
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/Nios2FrameLowering.cpp

//===-- Nios2FrameLowering.cpp - Nios2 Frame Information ------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Nios2 implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "Nios2FrameLowering.h"
#include "Nios2Subtarget.h"
#include "llvm/CodeGen/MachineFunction.h"
using namespace llvm;
bool Nios2FrameLowering::hasFP(const MachineFunction &MF) const { return true; }
void Nios2FrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {}
void Nios2FrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {}

llvm/trunk/lib/Target/Nios2/Nios2ISelDAGToDAG.cpp

//===-- Nios2ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Nios2 ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the NIOS2 target.
//
//===----------------------------------------------------------------------===//
#include "Nios2.h"
#include "Nios2TargetMachine.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Support/Debug.h"
using namespace llvm;
#define DEBUG_TYPE "nios2-isel"
//===----------------------------------------------------------------------===//
// Instruction Selector Implementation
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Nios2DAGToDAGISel - NIOS2 specific code to select NIOS2 machine
// instructions for SelectionDAG operations.
//===----------------------------------------------------------------------===//
namespace {
class Nios2DAGToDAGISel : public SelectionDAGISel {
/// Subtarget - Keep a pointer to the Nios2 Subtarget around so that we can
/// make the right decision when generating code for different targets.
const Nios2Subtarget *Subtarget;
public:
explicit Nios2DAGToDAGISel(Nios2TargetMachine &TM, CodeGenOpt::Level OL)
: SelectionDAGISel(TM, OL) {}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<Nios2Subtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
}
void Select(SDNode *N) override;
// Pass Name
StringRef getPassName() const override {
return "NIOS2 DAG->DAG Pattern Instruction Selection";
}
#include "Nios2GenDAGISel.inc"
};
} // namespace
// Select instructions not customized! Used for
// expanded, promoted and normal instructions
void Nios2DAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
Node->setNodeId(-1);
return;
}
// Select the default instruction
SelectCode(Node);
}
FunctionPass *llvm::createNios2ISelDag(Nios2TargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new Nios2DAGToDAGISel(TM, OptLevel);
}

llvm/trunk/lib/Target/Nios2/Nios2ISelLowering.h

//===-- Nios2ISelLowering.h - Nios2 DAG Lowering Interface ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the interfaces that Nios2 uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2ISELLOWERING_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2ISELLOWERING_H
#include "Nios2.h"
#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
class Nios2Subtarget;
namespace Nios2ISD {
enum NodeType {
// Start the numbering from where ISD NodeType finishes.
FIRST_NUMBER = ISD::BUILTIN_OP_END,
// Get the Higher 16 bits from a 32-bit immediate
// No relation with Nios2 Hi register
Hi,
// Get the Lower 16 bits from a 32-bit immediate
// No relation with Nios2 Lo register
Lo,
// Return
Ret
};
}
class Nios2TargetLowering : public TargetLowering {
const Nios2Subtarget *Subtarget;
public:
Nios2TargetLowering(const TargetMachine &TM, const Nios2Subtarget &STI);
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
const char *getTargetNodeName(unsigned Opcode) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
SelectionDAG &DAG) const override;
};
} // end namespace llvm
#endif // NIOS2_ISELLOWERING_H

llvm/trunk/lib/Target/Nios2/Nios2ISelLowering.cpp

//===-- Nios2ISelLowering.cpp - Nios2 DAG Lowering Implementation ---------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the interfaces that Nios2 uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//
#include "Nios2ISelLowering.h"
#include "Nios2MachineFunction.h"
#include "Nios2TargetMachine.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
#include "Nios2GenCallingConv.inc"
SDValue
Nios2TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SDLoc &DL, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of
// the return value to a location
SmallVector<CCValAssign, 16> RVLocs;
MachineFunction &MF = DAG.getMachineFunction();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
// Analyze return values.
CCInfo.CheckReturn(Outs, RetCC_Nios2EABI);
SDValue Flag;
SmallVector<SDValue, 4> RetOps(1, Chain);
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
SDValue Val = OutVals[i];
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
// Guarantee that all emitted copies are stuck together with flags.
Flag = Chain.getValue(1);
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
}
if (Flag.getNode())
RetOps.push_back(Flag);
return DAG.getNode(Nios2ISD::Ret, DL, MVT::Other, RetOps);
}
// addLiveIn - This helper function adds the specified physical register to the
// MachineFunction as a live in value. It also creates a corresponding
// virtual register for it.
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg,
const TargetRegisterClass *RC) {
unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
MF.getRegInfo().addLiveIn(PReg, VReg);
return VReg;
}
//===----------------------------------------------------------------------===//
// Formal Arguments Calling Convention Implementation
//===----------------------------------------------------------------------===//
// LowerFormalArguments - transform physical registers into virtual registers
// and generate load operations for arguments places on the stack.
SDValue Nios2TargetLowering::LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CC_Nios2);
// Used with vargs to acumulate store chains.
std::vector<SDValue> OutChains;
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
EVT ValVT = VA.getValVT();
// Arguments stored on registers
if (VA.isRegLoc()) {
MVT RegVT = VA.getLocVT();
unsigned ArgReg = VA.getLocReg();
const TargetRegisterClass *RC = getRegClassFor(RegVT);
// Transform the arguments stored on
// physical registers into virtual ones
unsigned Reg = addLiveIn(MF, ArgReg, RC);
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
// If this is an 8 or 16-bit value, it has been passed promoted
// to 32 bits. Insert an assert[sz]ext to capture this, then
// truncate to the right size.
if (VA.getLocInfo() != CCValAssign::Full) {
unsigned Opcode = 0;
if (VA.getLocInfo() == CCValAssign::SExt)
Opcode = ISD::AssertSext;
else if (VA.getLocInfo() == CCValAssign::ZExt)
Opcode = ISD::AssertZext;
if (Opcode)
ArgValue =
DAG.getNode(Opcode, DL, RegVT, ArgValue, DAG.getValueType(ValVT));
ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
}
// Handle floating point arguments passed in integer registers.
if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
(RegVT == MVT::i64 && ValVT == MVT::f64))
ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
InVals.push_back(ArgValue);
} else { // VA.isRegLoc()
MVT LocVT = VA.getLocVT();
// sanity check
assert(VA.isMemLoc());
// The stack pointer offset is relative to the caller stack frame.
int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
VA.getLocMemOffset(), true);
// Create load nodes to retrieve arguments from the stack
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
SDValue Load = DAG.getLoad(
LocVT, DL, Chain, FIN,
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
InVals.push_back(Load);
OutChains.push_back(Load.getValue(1));
}
}
if (!OutChains.empty()) {
OutChains.push_back(Chain);
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
}
return Chain;
}
//===----------------------------------------------------------------------===//
// TargetLowering Implementation
//===----------------------------------------------------------------------===//
Nios2TargetLowering::Nios2TargetLowering(const TargetMachine &TM,
const Nios2Subtarget &STI)
: TargetLowering(TM), Subtarget(&STI) {
addRegisterClass(MVT::i32, &Nios2::CPURegsRegClass);
computeRegisterProperties(Subtarget->getRegisterInfo());
}
const char *Nios2TargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
case Nios2ISD::Hi:
return "Nios2ISD::Hi";
case Nios2ISD::Lo:
return "Nios2ISD::Lo";
case Nios2ISD::Ret:
return "Nios2ISD::Ret";
}
return nullptr;
}

llvm/trunk/lib/Target/Nios2/Nios2InstrFormats.td

//===-- Nios2InstrFormats.td - Nios2 Instruction Formats ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Describe NIOS2 instructions format
//
//
//===----------------------------------------------------------------------===//
// Format specifies the encoding used by the instruction. This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
class Format<bits<6> val> {
bits<6> Value = val;
}
def Pseudo : Format<0>;
// Nios2 R1 instr formats:
def FrmI : Format<1>;
def FrmR : Format<2>;
def FrmJ : Format<3>;
def FrmOther : Format<4>; // Instruction w/ a custom format
// Nios2 R2 instr 32-bit formats:
def FrmL26 : Format<5>; // corresponds to J format in R1
def FrmF2I16 : Format<6>; // corresponds to I format in R1
def FrmF2X4I12 : Format<7>;
def FrmF1X4I12 : Format<8>;
def FrmF1X4L17 : Format<9>;
def FrmF3X6L5 : Format<10>; // corresponds to R format in R1
def FrmF2X6L10 : Format<11>;
def FrmF3X6 : Format<12>; // corresponds to R format in R1
def FrmF3X8 : Format<13>; // corresponds to custom format in R1
// Nios2 R2 instr 16-bit formats:
def FrmI10 : Format<14>;
def FrmT1I7 : Format<15>;
def FrmT2I4 : Format<16>;
def FrmT1X1I6 : Format<17>;
def FrmX1I7 : Format<18>;
def FrmL5I4X1 : Format<19>;
def FrmT2X1L3 : Format<20>;
def FrmT2X1I3 : Format<21>;
def FrmT3X1 : Format<22>;
def FrmT2X3 : Format<23>;
def FrmF1X1 : Format<24>;
def FrmX2L5 : Format<25>;
def FrmF1I5 : Format<26>;
def FrmF2 : Format<27>;
//===----------------------------------------------------------------------===//
// Instruction Predicates:
//===----------------------------------------------------------------------===//
def isNios2r1 : Predicate<"Subtarget->isNios2r1()">;
def isNios2r2 : Predicate<"Subtarget->isNios2r2()">;
class PredicateControl {
// Predicates related to specific target CPU features
list<Predicate> FeaturePredicates = [];
// Predicates for the instruction group membership in given ISA
list<Predicate> InstrPredicates = [];
list<Predicate> Predicates = !listconcat(FeaturePredicates, InstrPredicates);
}
//===----------------------------------------------------------------------===//
// Base classes for 32-bit, 16-bit and pseudo instructions
//===----------------------------------------------------------------------===//
class Nios2Inst32<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format f>: Instruction,
PredicateControl {
field bits<32> Inst;
Format Form = f;
let Namespace = "Nios2";
let Size = 4;
bits<6> Opcode = 0;
// Bottom 6 bits are the 'opcode' field
let Inst{5-0} = Opcode;
let OutOperandList = outs;
let InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
let Itinerary = itin;
// Attributes specific to Nios2 instructions:
// TSFlags layout should be kept in sync with Nios2InstrInfo.h.
let TSFlags{5-0} = Form.Value;
let DecoderNamespace = "Nios2";
field bits<32> SoftFail = 0;
}
class Nios2Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass Itin = IIPseudo>:
Nios2Inst32<outs, ins, asmstr, pattern, Itin, Pseudo> {
let isCodeGenOnly = 1;
let isPseudo = 1;
}
//===----------------------------------------------------------------------===//
// Base classes for R1 and R2 instructions
//===----------------------------------------------------------------------===//
class Nios2R1Inst32<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format f>:
Nios2Inst32<outs, ins, asmstr, pattern, itin, f> {
let DecoderNamespace = "Nios2";
let InstrPredicates = [isNios2r1];
}
class Nios2R2Inst32<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format f>:
Nios2Inst32<outs, ins, asmstr, pattern, itin, f> {
let DecoderNamespace = "Nios2r2";
let InstrPredicates = [isNios2r2];
}
//===----------------------------------------------------------------------===//
// Format I instruction class in Nios2 : <|A|B|immediate|opcode|>
//===----------------------------------------------------------------------===//
class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>: Nios2R1Inst32<outs, ins, asmstr,
pattern, itin, FrmI> {
bits<5> rA;
bits<5> rB;
bits<16> imm;
let Opcode = op;
let Inst{31-27} = rA;
let Inst{26-22} = rB;
let Inst{21-6} = imm;
}
//===----------------------------------------------------------------------===//
// Format R instruction : <|A|B|C|opx|imm|opcode|>
//===----------------------------------------------------------------------===//
class FR<bits<6> opx, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>: Nios2R1Inst32<outs, ins, asmstr,
pattern, itin, FrmR> {
bits<5> rA;
bits<5> rB;
bits<5> rC;
bits<5> imm = 0;
let Opcode = 0x3a; /* opcode is always 0x3a for R instr. */
let Inst{31-27} = rA;
let Inst{26-22} = rB;
let Inst{21-17} = rC;
let Inst{16-11} = opx; /* opx stands for opcode extension */
let Inst{10-6} = imm; /* optional 5-bit immediate value */
}
//===----------------------------------------------------------------------===//
// Format J instruction class in Nios2 : <|address|opcode|>
//===----------------------------------------------------------------------===//
class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>:
Nios2R1Inst32<outs, ins, asmstr, pattern, itin, FrmJ> {
bits<26> addr;
let Opcode = op;
let Inst{31-6} = addr;
}
//===----------------------------------------------------------------------===//
// Format F3X6 (R2) instruction : <|opx|RSV|C|B|A|opcode|>
//===----------------------------------------------------------------------===//
class F3X6<bits<6> opx, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>:
Nios2R2Inst32<outs, ins, asmstr, pattern, itin, FrmF3X6> {
bits<5> rC;
bits<5> rB;
bits<5> rA;
bits<5> rsv = 0;
let Opcode = 0x20; /* opcode is always 0x20 (OPX group) for F3X6 instr. */
let Inst{31-26} = opx; /* opx stands for opcode extension */
let Inst{25-21} = rsv;
let Inst{20-16} = rC;
let Inst{15-11} = rB;
let Inst{10-6} = rA;
}
//===----------------------------------------------------------------------===//
// Multiclasses for common instructions of both R1 and R2:
//===----------------------------------------------------------------------===//
// Multiclass for instructions that have R format in R1 and F3X6 format in R2
// and their opx values differ between R1 and R2
multiclass CommonInstr_R_F3X6_opx<bits<6> opxR1, bits<6> opxR2, dag outs,
dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin> {
def NAME#_R1 : FR<opxR1, outs, ins, asmstr, pattern, itin>;
def NAME#_R2 : F3X6<opxR2, outs, ins, asmstr, pattern, itin>;
}
// Multiclass for instructions that have R format in R1 and F3X6 format in R2
// and their opx values are the same in R1 and R2
multiclass CommonInstr_R_F3X6<bits<6> opx, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin> :
CommonInstr_R_F3X6_opx<opx, opx, outs, ins, asmstr, pattern, itin>;
// Multiclass for instructions that have I format in R1 and F2I16 format in R2
// and their op code values differ between R1 and R2
multiclass CommonInstr_I_F2I16_op<bits<6> opR1, bits<6> opR2, dag outs, dag ins,
string asmstr, list<dag> pattern,
InstrItinClass itin> {
def NAME#_R1 : FI<opR1, outs, ins, asmstr, pattern, itin>;
}
// Multiclass for instructions that have I format in R1 and F2I16 format in R2
// and their op code values are the same in R1 and R2
multiclass CommonInstr_I_F2I16<bits<6> op, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin> :
CommonInstr_I_F2I16_op<op, op, outs, ins, asmstr, pattern, itin>;

llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.h

//===-- Nios2InstrInfo.h - Nios2 Instruction Information --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Nios2 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2INSTRINFO_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2INSTRINFO_H
#include "Nios2RegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "Nios2GenInstrInfo.inc"
namespace llvm {
class Nios2Subtarget;
class Nios2InstrInfo : public Nios2GenInstrInfo {
const Nios2RegisterInfo RI;
const Nios2Subtarget &Subtarget;
virtual void anchor();
public:
explicit Nios2InstrInfo(Nios2Subtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
const Nios2RegisterInfo &getRegisterInfo() const { return RI; };
bool expandPostRAPseudo(MachineInstr &MI) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;
};
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.cpp

//===-- Nios2InstrInfo.cpp - Nios2 Instruction Information ----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Nios2 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#include "Nios2InstrInfo.h"
#include "Nios2TargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "Nios2GenInstrInfo.inc"
// Pin the vtable to this file.
void Nios2InstrInfo::anchor() {}
Nios2InstrInfo::Nios2InstrInfo(Nios2Subtarget &ST)
: Nios2GenInstrInfo(), RI(ST), Subtarget(ST) {}
/// Expand Pseudo instructions into real backend instructions
bool Nios2InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MachineBasicBlock &MBB = *MI.getParent();
switch (MI.getDesc().getOpcode()) {
default:
return false;
case Nios2::RetRA:
BuildMI(MBB, MI, MI.getDebugLoc(), get(Nios2::RET_R1)).addReg(Nios2::RA);
break;
}
MBB.erase(MI);
return true;
}
void Nios2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, unsigned DestReg,
unsigned SrcReg, bool KillSrc) const {
unsigned opc = Subtarget.hasNios2r2() ? Nios2::ADD_R2 : Nios2::ADD_R1;
BuildMI(MBB, I, DL, get(opc))
.addReg(DestReg, RegState::Define)
.addReg(Nios2::ZERO)
.addReg(SrcReg, getKillRegState(KillSrc));
}

llvm/trunk/lib/Target/Nios2/Nios2InstrInfo.td

//===- Nios2InstrInfo.td - Target Description for Nios2 ------*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Nios2 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
include "Nios2InstrFormats.td"
//===----------------------------------------------------------------------===//
// Nios2 Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
def simm16 : Operand<i32> {
let DecoderMethod= "DecodeSimm16";
}
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
// Custom return SDNode
def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
//===----------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
// Arithmetic and logical instructions with 2 registers and 16-bit immediate
// value.
multiclass ArithLogicRegImm16<bits<6> op, string mnemonic, SDNode opNode,
Operand immOp, PatLeaf immType>:
CommonInstr_I_F2I16<op, (outs CPURegs:$rB),
(ins CPURegs:$rA, immOp:$imm),
!strconcat(mnemonic, "\t$rB, $rA, $imm"),
[(set CPURegs:$rB,
(opNode CPURegs:$rA, immType:$imm))],
IIAlu>;
// Arithmetic and logical instructions with 3 register operands.
// Defines R1 and R2 instruction at the same time.
multiclass ArithLogicReg<bits<6> opx, string mnemonic,
SDNode opNode>:
CommonInstr_R_F3X6<opx, (outs CPURegs:$rC),
(ins CPURegs:$rA, CPURegs:$rB),
!strconcat(mnemonic, "\t$rC, $rA, $rB"),
[(set CPURegs:$rC, (opNode CPURegs:$rA, CPURegs:$rB))],
IIAlu>;
multiclass Return<bits<6> opx, dag outs, dag ins, string mnemonic> {
let rB = 0, rC = 0,
isReturn = 1,
isCodeGenOnly = 1,
hasCtrlDep = 1,
hasExtraSrcRegAllocReq = 1 in {
defm NAME# : CommonInstr_R_F3X6<opx, outs, ins, mnemonic, [], IIBranch>;
}
}
//===----------------------------------------------------------------------===//
// Nios2 Instructions
//===----------------------------------------------------------------------===//
/// Arithmetic instructions operating on registers.
let isCommutable = 1 ,
isReMaterializable = 1 in {
defm ADD : ArithLogicReg<0x31, "add", add>;
defm AND : ArithLogicReg<0x0e, "and", and>;
defm OR : ArithLogicReg<0x16, "or", or>;
defm XOR : ArithLogicReg<0x1e, "xor", xor>;
defm MUL : ArithLogicReg<0x27, "mul", mul>;
}
let isReMaterializable = 1 in {
defm SUB : ArithLogicReg<0x39, "sub", sub>;
}
defm DIVU : ArithLogicReg<0x24, "divu", udiv>;
defm DIV : ArithLogicReg<0x25, "div", sdiv>;
defm SLL : ArithLogicReg<0x13, "sll", shl>;
defm SRL : ArithLogicReg<0x1b, "srl", srl>;
defm SRA : ArithLogicReg<0x3b, "sra", sra>;
/// Arithmetic Instructions (ALU Immediate)
defm ADDI : ArithLogicRegImm16<0x04, "addi", add, simm16, immSExt16>;
// Returns:
defm RET : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
// Return RA.
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
def RetRA : Nios2Pseudo<(outs), (ins), "", [(Nios2Ret)]>;

llvm/trunk/lib/Target/Nios2/Nios2MCInstLower.cpp

//===-- Nios2MCInstLower.cpp - Convert Nios2 MachineInstr to MCInst -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains code to lower Nios2 MachineInstrs to their corresponding
// MCInst records.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/Nios2BaseInfo.h"
#include "MCTargetDesc/Nios2MCExpr.h"
#include "Nios2.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
using namespace llvm;
static MCOperand LowerSymbolOperand(const MachineOperand &MO, AsmPrinter &AP) {
MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
Nios2MCExpr::Nios2ExprKind TargetKind = Nios2MCExpr::CEK_None;
const MCSymbol *Symbol;
switch (MO.getTargetFlags()) {
default:
llvm_unreachable("Invalid target flag!");
case Nios2FG::MO_NO_FLAG:
break;
case Nios2FG::MO_ABS_HI:
TargetKind = Nios2MCExpr::CEK_ABS_HI;
break;
case Nios2FG::MO_ABS_LO:
TargetKind = Nios2MCExpr::CEK_ABS_LO;
break;
}
switch (MO.getType()) {
case MachineOperand::MO_GlobalAddress:
Symbol = AP.getSymbol(MO.getGlobal());
break;
case MachineOperand::MO_MachineBasicBlock:
Symbol = MO.getMBB()->getSymbol();
break;
case MachineOperand::MO_BlockAddress:
Symbol = AP.GetBlockAddressSymbol(MO.getBlockAddress());
break;
case MachineOperand::MO_ExternalSymbol:
Symbol = AP.GetExternalSymbolSymbol(MO.getSymbolName());
break;
case MachineOperand::MO_JumpTableIndex:
Symbol = AP.GetJTISymbol(MO.getIndex());
break;
case MachineOperand::MO_ConstantPoolIndex:
Symbol = AP.GetCPISymbol(MO.getIndex());
break;
default:
llvm_unreachable("<unknown operand type>");
}
const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, Kind, AP.OutContext);
if (TargetKind != Nios2MCExpr::CEK_None)
Expr = Nios2MCExpr::create(TargetKind, Expr, AP.OutContext);
return MCOperand::createExpr(Expr);
}
static MCOperand LowerOperand(const MachineOperand &MO, AsmPrinter &AP) {
switch (MO.getType()) {
default:
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit())
break;
return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
return MCOperand::createImm(MO.getImm());
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_BlockAddress:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ConstantPoolIndex:
return LowerSymbolOperand(MO, AP);
case MachineOperand::MO_RegisterMask:
break;
}
return MCOperand();
}
void llvm::LowerNios2MachineInstToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP) {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp = LowerOperand(MO, AP);
if (MCOp.isValid())
OutMI.addOperand(MCOp);
}
}

llvm/trunk/lib/Target/Nios2/Nios2MachineFunction.h

//===-- Nios2MachineFunctionInfo.h - Private data used for Nios2 --*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the Nios2 specific subclass of MachineFunctionInfo.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2MACHINEFUNCTION_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2MACHINEFUNCTION_H
#include "llvm/CodeGen/MachineFunction.h"
namespace llvm {
/// Nios2FunctionInfo - This class is derived from MachineFunction private
/// Nios2 target-specific information for each MachineFunction.
class Nios2FunctionInfo : public MachineFunctionInfo {
virtual void anchor();
private:
unsigned GlobalBaseReg;
/// VarArgsFrameOffset - Frame offset to start of varargs area.
int VarArgsFrameOffset;
/// SRetReturnReg - Holds the virtual register into which the sret
/// argument is passed.
unsigned SRetReturnReg;
/// IsLeafProc - True if the function is a leaf procedure.
bool IsLeafProc;
public:
Nios2FunctionInfo()
: GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
IsLeafProc(false) {}
explicit Nios2FunctionInfo(MachineFunction &MF)
: GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
IsLeafProc(false) {}
unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; }
unsigned getSRetReturnReg() const { return SRetReturnReg; }
void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
void setLeafProc(bool rhs) { IsLeafProc = rhs; }
bool isLeafProc() const { return IsLeafProc; }
};
} // end of namespace llvm
#endif // NIOS2_MACHINE_FUNCTION_INFO_H

llvm/trunk/lib/Target/Nios2/Nios2MachineFunction.cpp

//===-- Nios2MachineFunctionInfo.cpp - Private data used for Nios2 --------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "Nios2MachineFunction.h"
using namespace llvm;
void Nios2FunctionInfo::anchor() {}

llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.h

//===-- Nios2RegisterInfo.h - Nios2 Register Information Impl ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Nios2 implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2REGISTERINFO_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2REGISTERINFO_H
#include "Nios2.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "Nios2GenRegisterInfo.inc"
namespace llvm {
class Nios2Subtarget;
class TargetInstrInfo;
class Type;
class Nios2RegisterInfo : public Nios2GenRegisterInfo {
protected:
const Nios2Subtarget &Subtarget;
public:
Nios2RegisterInfo(const Nios2Subtarget &Subtarget);
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
BitVector getReservedRegs(const MachineFunction &MF) const override;
/// Stack Frame Processing Methods
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
/// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
/// Return GPR register class.
const TargetRegisterClass *intRegClass(unsigned Size) const;
};
} // end namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.cpp

//===-- Nios2RegisterInfo.cpp - Nios2 Register Information -== ------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Nios2 implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "nios2-reg-info"
#include "Nios2RegisterInfo.h"
#include "Nios2.h"
#include "Nios2Subtarget.h"
#define GET_REGINFO_TARGET_DESC
#include "Nios2GenRegisterInfo.inc"
using namespace llvm;
Nios2RegisterInfo::Nios2RegisterInfo(const Nios2Subtarget &ST)
: Nios2GenRegisterInfo(Nios2::RA), Subtarget(ST) {}
const TargetRegisterClass *Nios2RegisterInfo::intRegClass(unsigned Size) const {
return &Nios2::CPURegsRegClass;
}
const MCPhysReg *
Nios2RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CSR_SaveList;
}
BitVector Nios2RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
static const MCPhysReg ReservedCPURegs[] = {Nios2::ZERO, Nios2::AT, Nios2::SP,
Nios2::RA, Nios2::PC, Nios2::GP};
BitVector Reserved(getNumRegs());
for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
Reserved.set(ReservedCPURegs[I]);
return Reserved;
}
void Nios2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const {}
unsigned Nios2RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return Nios2::SP;
}

llvm/trunk/lib/Target/Nios2/Nios2RegisterInfo.td

//===-- Nios2RegisterInfo.td - Nios2 Register defs ---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// We have bank of 32 registers.
class Nios2Reg<string n> : Register<n> {
field bits<5> Num;
let Namespace = "Nios2";
}
// Nios2 CPU Registers
class Nios2GPRReg<bits<5> num, string n> : Nios2Reg<n> {
let Num = num;
}
//===----------------------------------------------------------------------===//
// Registers
//===----------------------------------------------------------------------===//
let Namespace = "Nios2" in {
// General Purpose Registers
def ZERO : Nios2GPRReg<0, "zero">, DwarfRegNum<[ 0 ]>;
def AT : Nios2GPRReg<1, "at">, DwarfRegNum<[ 1 ]>;
foreach RegNum = 2 - 23 in {
def R #RegNum : Nios2GPRReg<RegNum, "r" #RegNum>, DwarfRegNum<[ RegNum ]>;
}
def ET : Nios2GPRReg<24, "et">, DwarfRegNum<[ 24 ]>;
def BT : Nios2GPRReg<25, "bt">, DwarfRegNum<[ 25 ]>;
def GP : Nios2GPRReg<26, "gp">, DwarfRegNum<[ 26 ]>;
def SP : Nios2GPRReg<27, "sp">, DwarfRegNum<[ 27 ]>;
def FP : Nios2GPRReg<28, "fp">, DwarfRegNum<[ 28 ]>;
def EA : Nios2GPRReg<29, "ea">, DwarfRegNum<[ 29 ]>;
def BA : Nios2GPRReg<30, "ba">, DwarfRegNum<[ 30 ]>;
def RA : Nios2GPRReg<31, "ra">, DwarfRegNum<[ 31 ]>;
def PC : Nios2Reg<"pc">, DwarfRegNum<[ 32 ]>;
}
//===----------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
def CPURegs : RegisterClass<"Nios2", [ i32 ], 32,
(add
// Reserved
ZERO,
AT,
// Return Values and Arguments
(sequence "R%u", 2, 7),
// Not preserved across procedure calls
// Caller saved
(sequence "R%u", 8, 15),
// Callee saved
(sequence "R%u", 16, 23),
// Reserved
ET, BT, GP, SP, FP, EA, BA, RA, PC)>;

llvm/trunk/lib/Target/Nios2/Nios2Schedule.td

//===-- Nios2Schedule.td - Nios2 Scheduling Definitions ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Functional units across Nios2 chips sets. Based on GCC/Nios2 backend files.
//===----------------------------------------------------------------------===//
def ALU : FuncUnit;
def IMULDIV : FuncUnit;
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for Nios2
//===----------------------------------------------------------------------===//
def IIAlu : InstrItinClass;
def IILoad : InstrItinClass;
def IIStore : InstrItinClass;
def IIFlush : InstrItinClass;
def IIIdiv : InstrItinClass;
def IIBranch : InstrItinClass;
def IIPseudo : InstrItinClass;
//===----------------------------------------------------------------------===//
// Nios2 Generic instruction itineraries.
//===----------------------------------------------------------------------===//
//@ http://llvm.org/docs/doxygen/html/structllvm_1_1InstrStage.html
def Nios2GenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
InstrItinData<IIFlush , [InstrStage<1, [ALU]>]>,
InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>
]>;

llvm/trunk/lib/Target/Nios2/Nios2Subtarget.h

//===-- Nios2Subtarget.h - Define Subtarget for the Nios2 -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the Nios2 specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2SUBTARGET_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2SUBTARGET_H
#include "Nios2FrameLowering.h"
#include "Nios2ISelLowering.h"
#include "Nios2InstrInfo.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
#include "Nios2GenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class Nios2TargetMachine;
class Nios2Subtarget : public Nios2GenSubtargetInfo {
virtual void anchor();
public:
// Nios2 R2 features
// Bit manipulation instructions extension
bool HasBMX;
// Code Density instructions extension
bool HasCDX;
// Multi-Processor instructions extension
bool HasMPX;
// New mandatory instructions
bool HasR2Mandatory;
protected:
enum Nios2ArchEnum {
// Nios2 R1 ISA
Nios2r1,
// Nios2 R2 ISA
Nios2r2
};
// Nios2 architecture version
Nios2ArchEnum Nios2ArchVersion;
Triple TargetTriple;
Nios2InstrInfo InstrInfo;
Nios2TargetLowering TLInfo;
SelectionDAGTargetInfo TSInfo;
Nios2FrameLowering FrameLowering;
public:
/// This constructor initializes the data members to match that
/// of the specified triple.
Nios2Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool hasNios2r1() const { return Nios2ArchVersion >= Nios2r1; }
bool isNios2r1() const { return Nios2ArchVersion == Nios2r1; }
bool hasNios2r2() const { return Nios2ArchVersion >= Nios2r2; }
bool isNios2r2() const { return Nios2ArchVersion == Nios2r2; }
Nios2Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
const Nios2InstrInfo *getInstrInfo() const override { return &InstrInfo; }
const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
const Nios2RegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo();
}
const Nios2TargetLowering *getTargetLowering() const override {
return &TLInfo;
}
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
};
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/Nios2Subtarget.cpp

//===-- Nios2Subtarget.cpp - Nios2 Subtarget Information ------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the Nios2 specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
#include "Nios2Subtarget.h"
#include "Nios2.h"
using namespace llvm;
#define DEBUG_TYPE "nios2-subtarget"
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "Nios2GenSubtargetInfo.inc"
void Nios2Subtarget::anchor() {}
Nios2Subtarget::Nios2Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
:
// Nios2GenSubtargetInfo will display features by llc -march=nios2
// -mcpu=help
Nios2GenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
FrameLowering(*this) {}
Nios2Subtarget &Nios2Subtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
if (TargetTriple.getArch() == Triple::nios2) {
if (CPU != "nios2r2") {
CPU = "nios2r1";
Nios2ArchVersion = Nios2r1;
} else {
Nios2ArchVersion = Nios2r2;
}
} else {
errs() << "!!!Error, TargetTriple.getArch() = " << TargetTriple.getArch()
<< "CPU = " << CPU << "\n";
exit(0);
}
// Parse features string.
ParseSubtargetFeatures(CPU, FS);
return *this;
}

llvm/trunk/lib/Target/Nios2/Nios2TargetMachine.h

//===-- Nios2TargetMachine.h - Define TargetMachine for Nios2 ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the Nios2 specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2TARGETMACHINE_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2TARGETMACHINE_H
#include "Nios2Subtarget.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class Nios2TargetMachine : public LLVMTargetMachine {
mutable StringMap<std::unique_ptr<Nios2Subtarget>> SubtargetMap;
std::unique_ptr<TargetLoweringObjectFile> TLOF;
Nios2Subtarget Subtarget;
public:
Nios2TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT);
~Nios2TargetMachine() override;
const Nios2Subtarget *getSubtargetImpl() const { return &Subtarget; }
const Nios2Subtarget *getSubtargetImpl(const Function &F) const override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
};
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/Nios2TargetMachine.cpp

//===-- Nios2TargetMachine.cpp - Define TargetMachine for Nios2 -----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Implements the info about Nios2 target spec.
//
//===----------------------------------------------------------------------===//
#include "Nios2TargetMachine.h"
#include "Nios2.h"
#include "Nios2TargetObjectFile.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
#define DEBUG_TYPE "nios2"
extern "C" void LLVMInitializeNios2Target() {
// Register the target.
RegisterTargetMachine<Nios2TargetMachine> X(getTheNios2Target());
}
static std::string computeDataLayout() {
return "e-p:32:32:32-i8:8:32-i16:16:32-n32";
}
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
if (!RM.hasValue())
return Reloc::Static;
return *RM;
}
Nios2TargetMachine::Nios2TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(), TT, CPU, FS, Options,
getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(make_unique<Nios2TargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}
Nios2TargetMachine::~Nios2TargetMachine() {}
const Nios2Subtarget *
Nios2TargetMachine::getSubtargetImpl(const Function &F) const {
Attribute CPUAttr = F.getFnAttribute("target-cpu");
Attribute FSAttr = F.getFnAttribute("target-features");
std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
? CPUAttr.getValueAsString().str()
: TargetCPU;
std::string FS = !FSAttr.hasAttribute(Attribute::None)
? FSAttr.getValueAsString().str()
: TargetFS;
auto &I = SubtargetMap[CPU + FS];
if (!I) {
// This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<Nios2Subtarget>(TargetTriple, CPU, FS, *this);
}
return I.get();
}
namespace {
/// Nios2 Code Generator Pass Configuration Options.
class Nios2PassConfig : public TargetPassConfig {
public:
Nios2PassConfig(Nios2TargetMachine &TM, PassManagerBase *PM)
: TargetPassConfig(TM, *PM) {}
Nios2TargetMachine &getNios2TargetMachine() const {
return getTM<Nios2TargetMachine>();
}
void addCodeGenPrepare() override;
bool addInstSelector() override;
void addIRPasses() override;
};
} // namespace
TargetPassConfig *Nios2TargetMachine::createPassConfig(PassManagerBase &PM) {
return new Nios2PassConfig(*this, &PM);
}
void Nios2PassConfig::addCodeGenPrepare() {
TargetPassConfig::addCodeGenPrepare();
}
void Nios2PassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); }
// Install an instruction selector pass using
// the ISelDag to gen Nios2 code.
bool Nios2PassConfig::addInstSelector() {
addPass(createNios2ISelDag(getNios2TargetMachine(), getOptLevel()));
return false;
}

llvm/trunk/lib/Target/Nios2/Nios2TargetObjectFile.h

//===-- llvm/Target/Nios2TargetObjectFile.h - Nios2 Object Info -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2TARGETOBJECTFILE_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2TARGETOBJECTFILE_H
#include "Nios2TargetMachine.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
namespace llvm {
class Nios2TargetObjectFile : public TargetLoweringObjectFileELF {
public:
Nios2TargetObjectFile() : TargetLoweringObjectFileELF() {}
void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
};
} // end namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/Nios2TargetObjectFile.cpp

//===-- Nios2TargetObjectFile.cpp - Nios2 Object Files --------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "Nios2TargetObjectFile.h"
using namespace llvm;
void Nios2TargetObjectFile::Initialize(MCContext &Ctx,
const TargetMachine &TM) {
TargetLoweringObjectFileELF::Initialize(Ctx, TM);
InitializeELF(TM.Options.UseInitArray);
}

llvm/trunk/lib/Target/Nios2/Nios2TargetStreamer.h

//===-- Nios2TargetStreamer.h - Nios2 Target Streamer ----------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NIOS2_NIOS2TARGETSTREAMER_H
#define LLVM_LIB_TARGET_NIOS2_NIOS2TARGETSTREAMER_H
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
namespace llvm {
class Nios2TargetStreamer : public MCTargetStreamer {
public:
Nios2TargetStreamer(MCStreamer &S);
};
// This part is for ascii assembly output
class Nios2TargetAsmStreamer : public Nios2TargetStreamer {
public:
Nios2TargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
};
} // namespace llvm
#endif

llvm/trunk/lib/Target/Nios2/TargetInfo/CMakeLists.txt

add_llvm_library(LLVMNios2Info Nios2TargetInfo.cpp)

llvm/trunk/lib/Target/Nios2/TargetInfo/LLVMBuild.txt

;===- ./lib/Target/Nios2/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = Nios2Info
parent = Nios2
required_libraries = Support
add_to_library_groups = Nios2

llvm/trunk/lib/Target/Nios2/TargetInfo/Nios2TargetInfo.cpp

//===-- Nios2TargetInfo.cpp - Nios2 Target Implementation -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "Nios2.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
Target &llvm::getTheNios2Target() {
static Target TheNios2Target;
return TheNios2Target;
}
extern "C" void LLVMInitializeNios2TargetInfo() {
RegisterTarget<Triple::nios2,
/*HasJIT=*/true>
X(getTheNios2Target(), "nios2", "Nios2", "Nios2");
}

llvm/trunk/test/CodeGen/Nios2/add-sub.ll

; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
define i32 @add_reg(i32 %a, i32 %b) nounwind {
entry:
; CHECK: add_reg:
; CHECK: add r2, r4, r5
%c = add i32 %a, %b
ret i32 %c
}
define i32 @sub_reg(i32 %a, i32 %b) nounwind {
entry:
; CHECK: sub_reg:
; CHECK: sub r2, r4, r5
%c = sub i32 %a, %b
ret i32 %c
}

llvm/trunk/test/CodeGen/Nios2/lit.local.cfg

if not 'Nios2' in config.root.targets:
config.unsupported = True

llvm/trunk/test/CodeGen/Nios2/mul-div.ll

; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
define i32 @mul_reg(i32 %a, i32 %b) nounwind {
entry:
; CHECK: mul_reg:
; CHECK: mul r2, r4, r5
%c = mul i32 %a, %b
ret i32 %c
}
define i32 @div_signed(i32 %a, i32 %b) nounwind {
entry:
; CHECK: div_signed:
; CHECK: div r2, r4, r5
%c = sdiv i32 %a, %b
ret i32 %c
}
define i32 @div_unsigned(i32 %a, i32 %b) nounwind {
entry:
; CHECK: div_unsigned:
; CHECK: divu r2, r4, r5
%c = udiv i32 %a, %b
ret i32 %c
}

llvm/trunk/test/CodeGen/Nios2/proc_support.ll

; This tests that llc accepts Nios2 processors.
; RUN: not not llc < %s -asm-verbose=false -march=nios2 -mcpu=nios2r1 2>&1 | FileCheck %s --check-prefix=ARCH
; RUN: not not llc < %s -asm-verbose=false -march=nios2 -mcpu=nios2r2 2>&1 | FileCheck %s --check-prefix=ARCH
; ARCH-NOT: is not a recognized processor
define i32 @f(i32 %i) {
ret i32 %i
}

llvm/trunk/test/CodeGen/Nios2/ret_generated.ll

; This tests that llc generates 'ret' instruction in assembly output.
; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s --check-prefix=ARCH
; ARCH: ret
define i32 @f(i32 %i) {
ret i32 %i
}

llvm/trunk/test/CodeGen/Nios2/shift-rotate.ll

; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
define i32 @sll_reg(i32 %a, i32 %b) nounwind {
entry:
; CHECK: sll_reg:
; CHECK: sll r2, r4, r5
%c = shl i32 %a, %b
ret i32 %c
}
define i32 @srl_reg(i32 %a, i32 %b) nounwind {
entry:
; CHECK: srl_reg:
; CHECK: srl r2, r4, r5
%c = lshr i32 %a, %b
ret i32 %c
}
define i32 @sra_reg(i32 %a, i32 %b) nounwind {
entry:
; CHECK: sra_reg:
; CHECK: sra r2, r4, r5
%c = ashr i32 %a, %b
ret i32 %c
}

llvm/trunk/test/CodeGen/Nios2/target_support.ll

; This tests that llc accepts Nios2 target.
; RUN: not not llc < %s -asm-verbose=false -march=nios2 2>&1 | FileCheck %s --check-prefix=ARCH
; RUN: not not llc < %s -asm-verbose=false -mtriple=nios2 2>&1 | FileCheck %s --check-prefix=TRIPLE
; ARCH-NOT: invalid target
; TRIPLE-NOT: unable to get target
define i32 @f(i32 %i) {
ret i32 %i
}

llvm/trunk/utils/gn/secondary/clang/lib/Basic/BUILD.gn

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines sources = [
"Targets/AVR.cpp", "Targets/AVR.cpp",
"Targets/BPF.cpp", "Targets/BPF.cpp",
"Targets/Hexagon.cpp", "Targets/Hexagon.cpp",
"Targets/Lanai.cpp", "Targets/Lanai.cpp",
"Targets/Le64.cpp", "Targets/Le64.cpp",
"Targets/MSP430.cpp", "Targets/MSP430.cpp",
"Targets/Mips.cpp", "Targets/Mips.cpp",
"Targets/NVPTX.cpp", "Targets/NVPTX.cpp",
"Targets/Nios2.cpp",
"Targets/OSTargets.cpp", "Targets/OSTargets.cpp",
"Targets/PNaCl.cpp", "Targets/PNaCl.cpp",
"Targets/PPC.cpp", "Targets/PPC.cpp",
"Targets/RISCV.cpp", "Targets/RISCV.cpp",
"Targets/SPIR.cpp", "Targets/SPIR.cpp",
"Targets/Sparc.cpp", "Targets/Sparc.cpp",
"Targets/SystemZ.cpp", "Targets/SystemZ.cpp",
"Targets/TCE.cpp", "Targets/TCE.cpp",
Show All 13 Lines
llvm/trunk/test/CodeGen/Nios2/ret_generated.ll