[gn build] Add build files for llvm/lib/Target/ARM + tests

[thakis]

Summary

The ARM target itself is similar to the X86 target added in https://reviews.llvm.org/rL348903.
The llvm-exegesis unittests ARM bits are similar to the X86 bits in https://reviews.llvm.org/rL350413.
Both are similar to the corresponding bits in the AArch64 patch D56364 too.

After this patch, everything in my local GN branch is upstreamed to LLVM.

[phosek]

LGTM

llvm/utils/gn/secondary/llvm/lib/Target/AArch64/Utils/BUILD.gn

 import("//llvm/utils/TableGen/tablegen.gni")
 
 tablegen("AArch64GenSystemOperands") {
   visibility = [ ":Utils" ]
   args = [ "-gen-searchable-tables" ]
   td_file = "../AArch64.td"
 }
 
 static_library("Utils") {
   output_name = "LLVMAArch64Utils"
-  public_deps = [ ":AArch64GenSystemOperands" ]
+  public_deps = [
+    ":AArch64GenSystemOperands",
+  ]
   deps = [
     "//llvm/lib/Support",
     "//llvm/lib/Target/AArch64/MCTargetDesc:tablegen",
   ]
 
   # AArch64BaseInfo.h includes a header from MCTargetDesc :-/
   include_dirs = [ ".." ]
   sources = [
     "AArch64BaseInfo.cpp",
   ]
 }

llvm/utils/gn/secondary/llvm/lib/Target/ARM/AsmParser/BUILD.gn

+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("ARMGenAsmMatcher") {
+  visibility = [ ":AsmParser" ]
+  args = [ "-gen-asm-matcher" ]
+  td_file = "../ARM.td"
+}
+
+static_library("AsmParser") {
+  output_name = "LLVMARMAsmParser"
+  deps = [
+    ":ARMGenAsmMatcher",
+    "//llvm/lib/MC",
+    "//llvm/lib/MC/MCParser",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/ARM/MCTargetDesc",
+    "//llvm/lib/Target/ARM/TargetInfo",
+    "//llvm/lib/Target/ARM/Utils",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "ARMAsmParser.cpp",
+  ]
+}

llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn

+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("ARMGenCallingConv") {
+  visibility = [ ":LLVMARMCodeGen" ]
+  args = [ "-gen-callingconv" ]
+  td_file = "ARM.td"
+}
+
+tablegen("ARMGenDAGISel") {
+  visibility = [ ":LLVMARMCodeGen" ]
+  args = [ "-gen-dag-isel" ]
+  td_file = "ARM.td"
+}
+
+tablegen("ARMGenFastISel") {
+  visibility = [ ":LLVMARMCodeGen" ]
+  args = [ "-gen-fast-isel" ]
+  td_file = "ARM.td"
+}
+
+tablegen("ARMGenGlobalISel") {
+  visibility = [ ":LLVMARMCodeGen" ]
+  args = [ "-gen-global-isel" ]
+  td_file = "ARM.td"
+}
+
+tablegen("ARMGenMCPseudoLowering") {
+  visibility = [ ":LLVMARMCodeGen" ]
+  args = [ "-gen-pseudo-lowering" ]
+  td_file = "ARM.td"
+}
+
+tablegen("ARMGenRegisterBank") {
+  visibility = [ ":LLVMARMCodeGen" ]
+  args = [ "-gen-register-bank" ]
+  td_file = "ARM.td"
+}
+
+static_library("LLVMARMCodeGen") {
+  deps = [
+    ":ARMGenCallingConv",
+    ":ARMGenDAGISel",
+    ":ARMGenFastISel",
+    ":ARMGenGlobalISel",
+    ":ARMGenMCPseudoLowering",
+    ":ARMGenRegisterBank",
+    "InstPrinter",
+    "MCTargetDesc",
+    "TargetInfo",
+    "Utils",
+    "//llvm/include/llvm/Config:llvm-config",
+    "//llvm/lib/Analysis",
+    "//llvm/lib/CodeGen",
+    "//llvm/lib/CodeGen/AsmPrinter",
+    "//llvm/lib/CodeGen/GlobalISel",
+    "//llvm/lib/CodeGen/SelectionDAG",
+    "//llvm/lib/IR",
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target",
+  ]
+  include_dirs = [ "." ]
+  sources = [
+    "A15SDOptimizer.cpp",
+    "ARMAsmPrinter.cpp",
+    "ARMBaseInstrInfo.cpp",
+    "ARMBaseRegisterInfo.cpp",
+    "ARMCallLowering.cpp",
+    "ARMCodeGenPrepare.cpp",
+    "ARMComputeBlockSize.cpp",
+    "ARMConstantIslandPass.cpp",
+    "ARMConstantPoolValue.cpp",
+    "ARMExpandPseudoInsts.cpp",
+    "ARMFastISel.cpp",
+    "ARMFrameLowering.cpp",
+    "ARMHazardRecognizer.cpp",
+    "ARMISelDAGToDAG.cpp",
+    "ARMISelLowering.cpp",
+    "ARMInstrInfo.cpp",
+    "ARMInstructionSelector.cpp",
+    "ARMLegalizerInfo.cpp",
+    "ARMLoadStoreOptimizer.cpp",
+    "ARMMCInstLower.cpp",
+    "ARMMachineFunctionInfo.cpp",
+    "ARMMacroFusion.cpp",
+    "ARMOptimizeBarriersPass.cpp",
+    "ARMParallelDSP.cpp",
+    "ARMRegisterBankInfo.cpp",
+    "ARMRegisterInfo.cpp",
+    "ARMSelectionDAGInfo.cpp",
+    "ARMSubtarget.cpp",
+    "ARMTargetMachine.cpp",
+    "ARMTargetObjectFile.cpp",
+    "ARMTargetTransformInfo.cpp",
+    "MLxExpansionPass.cpp",
+    "Thumb1FrameLowering.cpp",
+    "Thumb1InstrInfo.cpp",
+    "Thumb2ITBlockPass.cpp",
+    "Thumb2InstrInfo.cpp",
+    "Thumb2SizeReduction.cpp",
+    "ThumbRegisterInfo.cpp",
+  ]
+}
+
+# This is a bit different from most build files: Due to this group
+# having the directory's name, "//llvm/lib/Target/AArch64" will refer to this
+# target, which pulls in the code in this directory *and all subdirectories*.
+# For most other directories, "//llvm/lib/Foo" only pulls in the code directly
+# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
+# different behavior.
+group("ARM") {
+  deps = [
+    ":LLVMARMCodeGen",
+    "AsmParser",
+    "Disassembler",
+    "InstPrinter",
+    "MCTargetDesc",
+    "TargetInfo",
+    "Utils",
+  ]
+}

llvm/utils/gn/secondary/llvm/lib/Target/ARM/Disassembler/BUILD.gn

+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("ARMGenDisassemblerTables") {
+  visibility = [ ":Disassembler" ]
+  args = [ "-gen-disassembler" ]
+  td_file = "../ARM.td"
+}
+
+static_library("Disassembler") {
+  output_name = "LLVMARMDisassembler"
+  deps = [
+    ":ARMGenDisassemblerTables",
+    "//llvm/lib/MC",
+    "//llvm/lib/MC/MCDisassembler",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/ARM/MCTargetDesc",
+    "//llvm/lib/Target/ARM/Utils",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "ARMDisassembler.cpp",
+  ]
+}

llvm/utils/gn/secondary/llvm/lib/Target/ARM/InstPrinter/BUILD.gn

+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("ARMGenAsmWriter") {
+  visibility = [ ":InstPrinter" ]
+  args = [ "-gen-asm-writer" ]
+  td_file = "../ARM.td"
+}
+
+static_library("InstPrinter") {
+  output_name = "LLVMARMAsmPrinter"
+  deps = [
+    ":ARMGenAsmWriter",
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+
+    # MCTargetDesc depends on InstPrinter, so we can't depend on the full
+    # MCTargetDesc target here: it would form a cycle.
+    "//llvm/lib/Target/ARM/MCTargetDesc:tablegen",
+    "//llvm/lib/Target/ARM/Utils",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "ARMInstPrinter.cpp",
+  ]
+}

llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn

+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("ARMGenInstrInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-instr-info" ]
+  td_file = "../ARM.td"
+}
+
+tablegen("ARMGenMCCodeEmitter") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-emitter" ]
+  td_file = "../ARM.td"
+}
+
+tablegen("ARMGenRegisterInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-register-info" ]
+  td_file = "../ARM.td"
+}
+
+tablegen("ARMGenSubtargetInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-subtarget" ]
+  td_file = "../ARM.td"
+}
+
+group("tablegen") {
+  visibility = [
+    ":MCTargetDesc",
+    "../InstPrinter",
+    "../TargetInfo",
+    "../Utils",
+  ]
+  public_deps = [
+    ":ARMGenInstrInfo",
+    ":ARMGenMCCodeEmitter",
+    ":ARMGenRegisterInfo",
+    ":ARMGenSubtargetInfo",
+  ]
+}
+static_library("MCTargetDesc") {
+  output_name = "LLVMARMDesc"
+  public_deps = [
+    ":tablegen",
+  ]
+  deps = [
+    "//llvm/lib/MC",
+    "//llvm/lib/MC/MCDisassembler",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/ARM/InstPrinter",
+    "//llvm/lib/Target/ARM/TargetInfo",
+    "//llvm/lib/Target/ARM/Utils",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "ARMAsmBackend.cpp",
+    "ARMELFObjectWriter.cpp",
+    "ARMELFStreamer.cpp",
+    "ARMMCAsmInfo.cpp",
+    "ARMMCCodeEmitter.cpp",
+    "ARMMCExpr.cpp",
+    "ARMMCTargetDesc.cpp",
+    "ARMMachORelocationInfo.cpp",
+    "ARMMachObjectWriter.cpp",
+    "ARMTargetStreamer.cpp",
+    "ARMUnwindOpAsm.cpp",
+    "ARMWinCOFFObjectWriter.cpp",
+    "ARMWinCOFFStreamer.cpp",
+  ]
+}

llvm/utils/gn/secondary/llvm/lib/Target/ARM/TargetInfo/BUILD.gn

+static_library("TargetInfo") {
+  output_name = "LLVMARMInfo"
+  deps = [
+    "//llvm/lib/Support",
+
+    # MCTargetDesc depends on TargetInfo, so we can't depend on the full
+    # MCTargetDesc target here: it would form a cycle.
+    "//llvm/lib/Target/ARM/MCTargetDesc:tablegen",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "ARMTargetInfo.cpp",
+  ]
+}

llvm/utils/gn/secondary/llvm/lib/Target/ARM/Utils/BUILD.gn

+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("ARMGenSystemRegister") {
+  visibility = [ ":Utils" ]
+  args = [ "-gen-searchable-tables" ]
+  td_file = "../ARM.td"
+}
+
+static_library("Utils") {
+  output_name = "LLVMARMUtils"
+  public_deps = [
+    ":ARMGenSystemRegister",
+  ]
+  deps = [
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/ARM/MCTargetDesc:tablegen",
+  ]
+
+  # ARMBaseInfo.h includes a header from MCTargetDesc,
+  # https://reviews.llvm.org/D35209#1075113 :-/
+  include_dirs = [ ".." ]
+  sources = [
+    "ARMBaseInfo.cpp",
+  ]
+}

llvm/utils/gn/secondary/llvm/lib/Target/targets.gni

 declare_args() {
   # The target archs LLVM should support. Defaults to the host arch.
   # Set to a list, e.g. `llvm_targets_to_build = [ "X86", "ARM" ]`,
   # or to the string "all" to get all known targets.
   llvm_targets_to_build = "host"
 }
 
 if (llvm_targets_to_build == "host") {
   if (host_cpu == "arm64") {
     llvm_targets_to_build = [ "AArch64" ]
+  } else if (host_cpu == "arm") {
+    llvm_targets_to_build = [ "ARM" ]
   } else if (host_cpu == "x86" || host_cpu == "x64") {
     llvm_targets_to_build = [ "X86" ]
   } else {
     assert(false, "add your host_cpu above")
   }
 } else if (llvm_targets_to_build == "all") {
   # FIXME: Port the remaining targets.
   llvm_targets_to_build = [
     "AArch64",
+    "ARM",
     "X86",
   ]
 }
 
 # Validate that llvm_targets_to_build is set to a list of valid targets,
 # and remember which targets are built.
 llvm_build_AArch64 = false
+llvm_build_ARM = false
 llvm_build_X86 = false
 foreach(target, llvm_targets_to_build) {
   if (target == "AArch64") {
     llvm_build_AArch64 = true
+  } else if (target == "ARM") {
+    llvm_build_ARM = true
   } else if (target == "X86") {
     llvm_build_X86 = true
   } else {
     # FIXME: Port the remaining targets.
     assert(false, "Unknown target '$target'.")
   }
 }
 
 # FIXME: This should be based off target_cpu once cross compiles work.
 if (host_cpu == "arm64") {
   native_target = "AArch64"
+} else if (host_cpu == "arm") {
+  native_target = "ARM"
 } else if (host_cpu == "x86" || host_cpu == "x64") {
   native_target = "X86"
 } else {
   assert(false, "Unsuppored host_cpu '$host_cpu'.")
 }

llvm/utils/gn/secondary/llvm/unittests/BUILD.gn

group("unittests") {
   # but if we disable an arch after building with it on, this
   # setup leaves behind stale executables.
   if (llvm_build_AArch64) {
     deps += [
       "Target/AArch64:AArch64Tests",
       "tools/llvm-exegesis/AArch64:LLVMExegesisAArch64Tests",
     ]
   }
-
-  # FIXME: Add ARM once the Targets exists.
-  #if (llvm_build_ARM) {
-  #deps += [ "tools/llvm-exegesis/ARM:LLVMExegesisARMTests" ]
-  #}
+  if (llvm_build_ARM) {
+    deps += [ "tools/llvm-exegesis/ARM:LLVMExegesisARMTests" ]
+  }
   if (llvm_build_X86) {
     deps += [ "tools/llvm-exegesis/X86:LLVMExegesisX86Tests" ]
   }
 
   testonly = true
 }

llvm/utils/gn/secondary/llvm/unittests/tools/llvm-exegesis/ARM/BUILD.gn

+import("//llvm/utils/unittest/unittest.gni")
+
+unittest("LLVMExegesisARMTests") {
+  deps = [
+    "//llvm/lib/DebugInfo/Symbolize",
+    "//llvm/lib/MC",
+    "//llvm/lib/MC/MCParser",
+    "//llvm/lib/Object",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/ARM",
+
+    # Exegesis reaches inside the Target/ARM tablegen internals and must
+    # depend on these Target/ARM-internal build targets.
+    "//llvm/lib/Target/ARM/MCTargetDesc",
+    "//llvm/lib/Target/ARM/Utils",
+    "//llvm/tools/llvm-exegesis/lib",
+  ]
+  include_dirs = [
+    "//llvm/lib/Target/ARM",
+    "//llvm/tools/llvm-exegesis/lib",
+  ]
+  sources = [
+    "AssemblerTest.cpp",
+  ]
+}