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Differential D56308

AMDGPU/GlobalISel: Really legalize exts from i1
ClosedPublic

Authored by arsenm on Jan 3 2019, 11:25 PM.

Details

Reviewers
tstellar
rampitec
Summary

There is a combine that was hiding these tests
not actually testing what they should be, although
they were producing the expected end result.

Diff Detail

Event Timeline

arsenm created this revision.Jan 3 2019, 11:25 PM
Herald added subscribers: t-tye, tpr, dstuttard and 7 others. · View Herald TranscriptJan 3 2019, 11:25 PM
tstellar accepted this revision.Jan 7 2019, 9:14 AM

LGTM.

This revision is now accepted and ready to land.Jan 7 2019, 9:14 AM
arsenm closed this revision.Jan 20 2019, 11:28 AM

r351698

Herald added a subscriber: volkan. · View Herald TranscriptJan 20 2019, 11:28 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
3 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
28 lines
16 lines
30 lines

Diff 180200

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
// Must use fadd + fneg // Must use fadd + fneg
setAction({G_FSUB, S64}, Lower); setAction({G_FSUB, S64}, Lower);
setAction({G_FCMP, S1}, Legal); setAction({G_FCMP, S1}, Legal);
setAction({G_FCMP, 1, S32}, Legal); setAction({G_FCMP, 1, S32}, Legal);
setAction({G_FCMP, 1, S64}, Legal); setAction({G_FCMP, 1, S64}, Legal);
getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalFor({{S64, S32}, {S32, S16}, {S64, S16}}) .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
{S32, S1}, {S64, S1}, {S16, S1}})
.fewerElementsIf( .fewerElementsIf(
[](const LegalityQuery &Query) { [](const LegalityQuery &Query) {
return Query.Types[0].isVector(); return Query.Types[0].isVector();
}, },
[](const LegalityQuery &Query) { [](const LegalityQuery &Query) {
return std::make_pair( return std::make_pair(
0, Query.Types[0].getElementType()); 0, Query.Types[0].getElementType());
}); });
▲ Show 20 Lines • Show All 259 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines bb.0.entry:
%2:_(s32) = G_ANYEXT %1 %2:_(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_anyext_i1_to_i32 name: test_anyext_i1_to_i32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_anyext_i1_to_i32 ; CHECK-LABEL: name: test_anyext_i1_to_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s1)
; CHECK: $vgpr0 = COPY [[COPY1]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s1) = G_CONSTANT i1 0
%1:_(s1) = G_TRUNC %0 %1:_(s32) = G_ANYEXT %0
%2:_(s32) = G_ANYEXT %1 $vgpr0 = COPY %1
$vgpr0 = COPY %2 ...
---
name: test_anyext_i1_to_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: test_anyext_i1_to_i64
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s1)
; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
%0:_(s1) = G_CONSTANT i1 0
%1:_(s64) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_anyext_v2s16_to_v2s32 name: test_anyext_v2s16_to_v2s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
▲ Show 20 Lines • Show All 112 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
--- ---
name: test_sext_i1_to_i32 name: test_sext_i1_to_i32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_sext_i1_to_i32 ; CHECK-LABEL: name: test_sext_i1_to_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: $vgpr0 = COPY [[SEXT]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) %0:_(s1) = G_CONSTANT i1 0
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) %1:_(s32) = G_SEXT %0
; CHECK: $vgpr0 = COPY [[ASHR]](s32) $vgpr0 = COPY %1
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2
... ...
--- ---
name: test_sext_v2s16_to_v2s32 name: test_sext_v2s16_to_v2s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines bb.0.entry:
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_zext_i1_to_i32 name: test_zext_i1_to_i32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0
; CHECK-LABEL: name: test_zext_i1_to_i32 ; CHECK-LABEL: name: test_zext_i1_to_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s1)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] %0:_(s1) = G_CONSTANT i1 0
; CHECK: $vgpr0 = COPY [[AND]](s32) %1:_(s32) = G_ZEXT %0
%0:_(s32) = COPY $vgpr0 $vgpr0 = COPY %1
%1:_(s1) = G_TRUNC %0 ...
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2 ---
name: test_zext_i1_to_i64
body: |
bb.0.entry:
; CHECK-LABEL: name: test_zext_i1_to_i64
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s1)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s1) = G_CONSTANT i1 0
%1:_(s64) = G_ZEXT %0
$vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_zext_v2s16_to_v2s32 name: test_zext_v2s16_to_v2s32
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0 liveins: $vgpr0
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines