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[AArch64] Fix operation actions for FP16 vector intrinsics
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Authored by bryanpkc on Thu, Jan 3, 3:16 PM.

Details

Summary

This patch changes the legalization action for some half-precision floating-
point vector intrinsics (FSIN, FLOG, etc.) from Promote to Expand. These ops
are not supported in hardware for half-precision vectors, but promotion is
not always possible (for v8f16 operands). Changing the action to Expand fixes
an assertion failure in the legalizer when the frontend produces such ops.
In addition, a quick microbenchmark shows that, in the v4f16 case,
expanding introduces fewer spills and is therefore slightly faster than
promoting.

Diff Detail

Repository
rL LLVM

Event Timeline

bryanpkc created this revision.Thu, Jan 3, 3:16 PM

Pinging reviewers.

This revision is now accepted and ready to land.Wed, Jan 9, 12:48 AM
bryanpkc updated this revision to Diff 181034.Thu, Jan 10, 5:12 AM

Removed trailing spaces. NFC.

bryanpkc updated this revision to Diff 181052.Thu, Jan 10, 7:04 AM

Rebased on trunk.

This revision was automatically updated to reflect the committed changes.