[RFC] [LLVM] Allocatable Global Register Variables for ARM

[carwil]

Summary

Provides the backend support for using r5-r11 as globally scoped register variables. This will prevent them from being used by the register allocator, and from being saved to the stack.
It should be noted that this does change the behaviour of the old -ffixed-r9 option. This option will now also prevent its register from being spilled to the stack.
Clang patch: https://reviews.llvm.org/D56003

[carwil]

• Re-implementation using subtarget features over metadata.
• Reduction of register range to R5-R11.
• Additional checks to fix issues with spilling registers for stack alignment.

[efriedma]

Please repost this patch with llvm-commits CC'ed.

(I plan to review in detail this week.)

[carwil]

Added llvm-commits.

[carwil]

Added more test coverage, notably those to catch issues with using reserved registers for alignment or making up Thumb reg deficit.

[carwil]

Fixed an oversight where R6 could be used as the base pointer, even with ffixed-r6 specified.

[carwil]

Hi @efriedma, are you still happy to review this?

[efriedma]

Sorry about the delay.

It looks like there's a conflict between reserving r7/r11 and the use of r7/r11 as a frame pointer. (See useR7AsFramePointer.) Similarly, there's a conflict between reserving r6 and its use as a base pointer. It's okay if some combinations print an error, but we shouldn't silently miscompile.

lib/Target/ARM/ARMSubtarget.h

723

Can we handle this in initSubtargetFeatures instead, like we do for rwpi? It's sort of confusing to follow.

test/CodeGen/ARM/reg-alloc-no-alignment.ll

16 ↗

(On Diff #183115)

Newline.

[carwil]

Not at all, thank you your comments.

I believe we have handled the r7/11 (FP) case when using clang (clang patch: https://reviews.llvm.org/D56003). We throw a warning here, as even specifying -fomit-frame-pointer can't seem to *guarantee* that the compiler won't touch them. We could restrict its usage entirely, but on thumb at least, that wouldn't leave you with much choice.

I think the R6/BP problem was resolved in my last diff by disabling the BP (lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 416), when r6 has been reserved.

That said, if you used LLVM directly, without clang... Yes, we will need (a) warning(s) in the backend as well.

[efriedma]

Yes, we should error in the backend, regardless of what clang does, in case some other frontend is missing the appropriate diagnostics.

Dynamically allocating memory on the stack requires a frame pointer... although I guess with -fomit-frame-pointer, we could try to choose a register that isn't reserved instead of unconditionally using the platform default.

lib/Target/ARM/ARMBaseRegisterInfo.cpp

377

In the case where we have stack realignment and VLAs, what happens? IIRC we don't have any code to generate an alternate sequence (although I guess that would be theoretically possible to dynamically allocate stack slots that would otherwise require realignment). Do we print an error message?

[carwil]

Superseded by https://reviews.llvm.org/D68862.

lib/Target/ARM/ARMSubtarget.h

723

I'm not quite sure what you mean. This is just a convenience function for checking which registers have been reserved. We're not actually setting the reservations here, that's handled by the ARM.td/reserve-rN rule(s).

r9 could be reserved either with ffixed-r9/reserve-r9 or with -frwpi, the second case being handled in initTargetSubFeatures.
For the other GPRs we only have the ffixed options, so there is no need.

Am I misunderstanding?

lib/Target/ARM/ARM.td

def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
                                              "Generate calls via indirect call "
                                              "instructions">;
 
 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
                                              "GenExecuteOnly", "true",
                                              "Enable the generation of "
                                              "execute only code.">;
 
-def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
-                                             "Reserve R9, making it unavailable"
-                                             " as GPR">;
+foreach i = {5-11} in
+    def FeatureReserveR#i : SubtargetFeature<"reserve-r"#i,
+                                             "ReserveRRegister["#i#"]", "true",
+                                             "Reserve R"#i#", making it "
+                                             "unavailable as a GPR">;
 
 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
                                              "Don't use movt/movw pairs for "
                                              "32-bit imms">;
 
 def FeatureNoNegativeImmediates
                           : SubtargetFeature<"no-neg-immediates",
                                              "NegativeImmediates", "false",

lib/Target/ARM/ARMAsmPrinter.cpp

if (const Module *SourceModule = MMI->getModule()) {
       }
     }
   }
 
   // We currently do not support using R9 as the TLS pointer.
   if (STI.isRWPI())
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9IsSB);
-  else if (STI.isR9Reserved())
+  else if (STI.isRRegisterReserved(9))
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9Reserved);
   else
     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
                       ARMBuildAttrs::R9IsGPR);
 }
 
 //===----------------------------------------------------------------------===//

lib/Target/ARM/ARMBaseRegisterInfo.cpp

getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, ARM::SP);
   markSuperRegs(Reserved, ARM::PC);
   markSuperRegs(Reserved, ARM::FPSCR);
   markSuperRegs(Reserved, ARM::APSR_NZCV);
   if (TFI->hasFP(MF))
     markSuperRegs(Reserved, getFramePointerReg(STI));
   if (hasBasePointer(MF))
     markSuperRegs(Reserved, BasePtr);
-  // Some targets reserve R9.
-  if (STI.isR9Reserved())
-    markSuperRegs(Reserved, ARM::R9);
+  for (size_t R = 0; R < ARM::GPRRegClass.getNumRegs(); ++R) {
+    if (STI.isRRegisterReserved(R)) {
+      markSuperRegs(Reserved, ARM::R0 + R);
+    }
+  }
   // Reserve D16-D31 if the subtarget doesn't support them.
   if (!STI.hasVFP3() || STI.hasD16()) {
     static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
     for (unsigned R = 0; R < 16; ++R)
       markSuperRegs(Reserved, ARM::D16 + R);
   }
   const TargetRegisterClass &RC = ARM::GPRPairRegClass;
   for (unsigned Reg : RC)
case ARM::tGPRRegClassID: {
     // ScheduleDAGRRList.
     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
                  ? TFI->hasFP(MF) : true;
     return 5 - HasFP;
   }
   case ARM::GPRRegClassID: {
     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
                  ? TFI->hasFP(MF) : true;
-    return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
+    return 10 - HasFP - STI.getNumRRegisterReserved();
   }
   case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
   case ARM::DPRRegClassID:
     return 32 - 10;
   }
 }
 
 // Get the other register in a GPRPair.

 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   const ARMFrameLowering *TFI = getFrameLowering(MF);
 
   // When outgoing call frames are so large that we adjust the stack pointer
   // around the call, we can no longer use the stack pointer to reach the
   // emergency spill slot.
   if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
     return true;
 
   // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
   // negative range for ldr/str (255), and thumb1 is positive offsets only.
   // It's going to be better to use the SP or Base Pointer instead. When there
   // are variable sized objects, we can't reference off of the SP, so we
   // reserve a Base Pointer.
   if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {

lib/Target/ARM/ARMFrameLowering.cpp

void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
   if (RegInfo->hasBasePointer(MF))
     SavedRegs.set(RegInfo->getBaseRegister());
 
   // Don't spill FP if the frame can be eliminated. This is determined
   // by scanning the callee-save registers to see if any is modified.
   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
   for (unsigned i = 0; CSRegs[i]; ++i) {
     unsigned Reg = CSRegs[i];
+    if (STI.isRWPI() && Reg == ARM::R9) {
+      // Paranoid check for use of R9 with RWPI. Clobbering R9 with -frwpi will
+      // emit warnings about undefined behaviour but maybe theres's a valid use
+      // case so on that basis allow it to be pushed/popped in the
+      // prologue/epilogue.
+    } else if (Reg > ARM::R0 && ARM::GPRRegClass.contains(Reg) &&
+        STI.isRRegisterReserved(Reg - ARM::R0)) {
+      LLVM_DEBUG(dbgs()
+                 << printReg(Reg, TRI)
+                 << " has been reserved and"
+                 << " should not be allocatable"
+                 << " or spillable.\n");
+      SavedRegs.reset(Reg);
+      continue;
+    }
     bool Spilled = false;
     if (SavedRegs.test(Reg)) {
       Spilled = true;
       CanEliminateFrame = false;
     }
 
     if (!ARM::GPRRegClass.contains(Reg)) {
       if (Spilled) {
if (AFI->isThumb1OnlyFunction()) {
       // r4-r6 can be used in the prologue if they are pushed by the first push
       // instruction.
       for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
         if (SavedRegs.test(Reg)) {
           --RegDeficit;
           LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
                             << " is saved low register, RegDeficit = "
                             << RegDeficit << "\n");
-        } else {
+        } else if (!STI.isRRegisterReserved(Reg - ARM::R0)) {
           AvailableRegs.push_back(Reg);
           LLVM_DEBUG(
               dbgs()
               << printReg(Reg, TRI)
               << " is non-saved low register, adding to AvailableRegs\n");
         }
       }
 
       // r7 can be used if it is not being used as the frame pointer.
       if (!HasFP) {
         if (SavedRegs.test(ARM::R7)) {
           --RegDeficit;
           LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
                             << RegDeficit << "\n");
-        } else {
+        } else if (!STI.isRRegisterReserved(7)) {
           AvailableRegs.push_back(ARM::R7);
           LLVM_DEBUG(
               dbgs()
               << "%r7 is non-saved low register, adding to AvailableRegs\n");
         }
       }
 
       // Each of r8-r11 needs to be copied to a low register, then pushed.

lib/Target/ARM/ARMISelLowering.cpp

SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
   return FrameAddr;
 }
 
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
 unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
                                               SelectionDAG &DAG) const {
   unsigned Reg = StringSwitch<unsigned>(RegName)
+                       .Case("r5", ARM::R5)
+                       .Case("r6", ARM::R6)
+                       .Case("r7", ARM::R7)
+                       .Case("r8", ARM::R8)
+                       .Case("r9", ARM::R9)
+                       .Case("r10", ARM::R10)
+                       .Case("r11", ARM::R11)
                        .Case("sp", ARM::SP)
-                       .Default(0);
-  if (Reg)
+                       .Default(ARM::NoRegister);
+  if (Reg != ARM::NoRegister)
     return Reg;
   report_fatal_error(Twine("Invalid register name \""
                               + StringRef(RegName)  + "\"."));
 }
 
 // Result is 64 bit value so split into two 32 bit values and return as a
 // pair of values.
 static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,

lib/Target/ARM/ARMSubtarget.h

protected:
   bool UseAA = false;
 
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
 
   /// NoARM - True if subtarget does not support ARM mode execution.
   bool NoARM = false;
 
-  /// ReserveR9 - True if R9 is not available as a general purpose register.
-  bool ReserveR9 = false;
+  // ReserveRRegister[i] - R#i is not available as a general purpose register.
+  BitVector ReserveRRegister;
 
   /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
   /// 32-bit imms (including global addresses).
   bool NoMovt = false;
 
   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
   /// must be able to synthesize call stubs for interworking between ARM and
   /// Thumb.
public:
   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
   bool isThumb2() const { return InThumbMode && HasThumb2; }
   bool hasThumb2() const { return HasThumb2; }
   bool isMClass() const { return ARMProcClass == MClass; }
   bool isRClass() const { return ARMProcClass == RClass; }
   bool isAClass() const { return ARMProcClass == AClass; }
   bool isReadTPHard() const { return ReadTPHard; }
 
-  bool isR9Reserved() const {
-    return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
+  bool isRRegisterReserved(size_t i) const {
+    if (i == 9 && isTargetMachO() && !HasV6Ops) {
+      return true;
+    }
+    return ReserveRRegister[i];
+  }
+  unsigned getNumRRegisterReserved() const {
+    unsigned result = ReserveRRegister.count();
+    if (!ReserveRRegister[9] && isRRegisterReserved(9)) {
+      ++result;
     }
+    return result;
+  }
+
 
   bool useR7AsFramePointer() const {
     return isTargetDarwin() || (!isTargetWindows() && isThumb());
   }
 
   /// Returns true if the frame setup is split into two separate pushes (first
   /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
   /// to lr. This is always required on Thumb1-only targets, as the push and

lib/Target/ARM/ARMSubtarget.cpp

if (STI.isThumb1Only())
     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
 
   return new ARMFrameLowering(STI);
 }
 
 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS,
                            const ARMBaseTargetMachine &TM, bool IsLittle)
-    : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
+    : ARMGenSubtargetInfo(TT, CPU, FS),
+      UseMulOps(UseFusedMulOps),
+      ReserveRRegister(ARM::GPRRegClass.getNumRegs()),
       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
       TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
       // At this point initializeSubtargetDependencies has been called so
       // we can query directly.
       InstrInfo(isThumb1Only()
                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
                     : !isThumb()
                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 
   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
   const FeatureBitset &Bits = getFeatureBits();
   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
       (Options.UnsafeFPMath || isTargetDarwin()))
     UseNEONForSinglePrecisionFP = true;
 
   if (isRWPI())
-    ReserveR9 = true;
+    ReserveRRegister.set(9);
 
   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
   switch (ARMProcFamily) {
   case Others:
   case CortexA5:
     break;
   case CortexA7:
     LdStMultipleTiming = DoubleIssue;

lib/Target/ARM/ARMTargetTransformInfo.h

const FeatureBitset InlineFeatureWhitelist = {
       ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
       ARM::FeatureHasSlowFPVMLx, ARM::FeatureVMLxForwarding,
       ARM::FeaturePref32BitThumb, ARM::FeatureAvoidPartialCPSR,
       ARM::FeatureCheapPredicableCPSR, ARM::FeatureAvoidMOVsShOp,
       ARM::FeatureHasRetAddrStack, ARM::FeatureHasNoBranchPredictor,
       ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
       ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
       ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
-      ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,
+      ARM::FeatureExecuteOnly, ARM::FeatureReserveR5, ARM::FeatureReserveR6,
+      ARM::FeatureReserveR7, ARM::FeatureReserveR8, ARM::FeatureReserveR9,
+      ARM::FeatureReserveR10, ARM::FeatureReserveR11, ARM::FeatureNoMovt,
       ARM::FeatureNoNegativeImmediates
   };
 
   const ARMSubtarget *getST() const { return ST; }
   const ARMTargetLowering *getTLI() const { return TLI; }
 
 public:
   explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)

test/CodeGen/ARM/named-reg-alloc.ll

 ; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s
 ; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s
 
 define i32 @get_stack() nounwind {
 entry:
 ; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name "r5".
+; CHECK: Invalid register name "r3".
   %sp = call i32 @llvm.read_register.i32(metadata !0)
   ret i32 %sp
 }
 
 declare i32 @llvm.read_register.i32(metadata) nounwind
 
-!0 = !{!"r5\00"}
+!0 = !{!"r3\00"}

test/CodeGen/ARM/reg-alloc-with-fixed-reg-r5-r6.ll

+; RUN: llc < %s -mattr=+reserve-r5,+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r5, r6{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r4{{.*}}
+; CHECK-NOT: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+; CHECK: {{.*}}r7{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r5, r6{{.*}}}
+}

test/CodeGen/ARM/reg-alloc-with-fixed-reg-r5.ll

+; RUN: llc < %s -mattr=+reserve-r5 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r5,{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r4{{.*}}
+; CHECK-NOT: {{.*}}r5{{.*}}
+; CHECK: {{.*}}r6{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r5,{{.*}}}
+}

test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll

+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; register unsigned r6 asm("r6");
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     r6 = 10;
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+declare void @llvm.write_register.i32(metadata, i32) nounwind
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  ; r6 = 10
+  call void @llvm.write_register.i32(metadata !0, i32 10)
+; CHECK: {{.*}}mov{{.*}}r6,{{.*}}
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+; CHECK: {{.*}}r7{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r6,{{.*}}}
+}
+
+!llvm.named.register.r6 = !{!0}
+!0 = !{!"r6"}

test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll

+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+; CHECK: {{.*}}r7{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r6,{{.*}}}
+}

test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll

+; RUN: llc < %s -mtriple=arm-linux-gnueabi  -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l +m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK: push {{{.*}}r4, r5{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r4{{.*}}
+; CHECK: {{.*}}r5{{.*}}
+
+; CHECK: pop {{{.*}}r4, r5{{.*}}}
+  ret void
+}