[x86] add load fold patterns for movddup with vzext_load

[spatel]

Summary

The missed load folding noticed in D55898 is visible independent of that change either with an adjusted IR pattern to start or with AVX2 (where the build vector becomes a broadcast first; movddup is not produced until we get into isel via tablegen patterns).

[craig.topper]

Does AVX512 avoid this somehow or do we need these patterns there too?

[spatel]

Patch updated:
Add pattern for AVX512VL. I moved the dedicated test for this bug (rL349920), so we'd have a single file with the relevant RUN lines without adding a bunch of noise.

[RKSimon]

LGTM - thanks.

lib/Target/X86/X86InstrSSE.td

 }
 
 defm MOVDDUP : sse3_replicate_dfp<"movddup", SchedWriteFShuffle>;
 
 
 let Predicates = [HasAVX, NoVLX] in {
   def : Pat<(X86Movddup (loadv2f64 addr:$src)),
             (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
+  def : Pat<(X86Movddup (v2f64 (X86vzload addr:$src))),
+            (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
 }
 
 let Predicates = [UseSSE3] in {
   // No need for aligned memory as this only loads 64-bits.
   def : Pat<(X86Movddup (loadv2f64 addr:$src)),
             (MOVDDUPrm addr:$src)>;
+  def : Pat<(X86Movddup (v2f64 (X86vzload addr:$src))),
+            (MOVDDUPrm addr:$src)>;
 }
 
 //===---------------------------------------------------------------------===//
 // SSE3 - Move Unaligned Integer
 //===---------------------------------------------------------------------===//
 
 let Predicates = [HasAVX] in {
   def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
def : Pat<(v2f64 (X86VBroadcast f64:$src)),
             (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))>;
   def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
             (VMOVDDUPrm addr:$src)>;
 
   def : Pat<(v2f64 (X86VBroadcast v2f64:$src)),
             (VMOVDDUPrr VR128:$src)>;
   def : Pat<(v2f64 (X86VBroadcast (loadv2f64 addr:$src))),
             (VMOVDDUPrm addr:$src)>;
+  def : Pat<(v2f64 (X86VBroadcast (v2f64 (X86vzload addr:$src)))),
+            (VMOVDDUPrm addr:$src)>;
 }
 
 let Predicates = [HasAVX1Only] in {
   def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
             (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)>;
   def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
             (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
               (v4f32 (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)), sub_xmm),

test/CodeGen/X86/build-vector-128.ll

 ; SSE2-64-LABEL: movddup_load_fold:
 ; SSE2-64:       # %bb.0:
 ; SSE2-64-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE2-64-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE2-64-NEXT:    retq
 ;
 ; SSE41-32-LABEL: movddup_load_fold:
 ; SSE41-32:       # %bb.0:
-; SSE41-32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE41-32-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
+; SSE41-32-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
 ; SSE41-32-NEXT:    retl
 ;
 ; SSE41-64-LABEL: movddup_load_fold:
 ; SSE41-64:       # %bb.0:
 ; SSE41-64-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
 ; SSE41-64-NEXT:    movddup {{.*#+}} xmm0 = xmm0[0,0]
 ; SSE41-64-NEXT:    retq
 ;
 ; AVX-32-LABEL: movddup_load_fold:
 ; AVX-32:       # %bb.0:
-; AVX-32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-32-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-32-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
 ; AVX-32-NEXT:    retl
 ;
 ; AVX1-64-LABEL: movddup_load_fold:
 ; AVX1-64:       # %bb.0:
 ; AVX1-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
 ; AVX1-64-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX1-64-NEXT:    retq
 ;

 ; AVX1-64:       # %bb.0:
 ; AVX1-64-NEXT:    vinsertps {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[2,3]
 ; AVX1-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]
 ; AVX1-64-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
 ; AVX1-64-NEXT:    retq
 ;
 ; AVX2-32-LABEL: PR37502:
 ; AVX2-32:       # %bb.0:
-; AVX2-32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX2-32-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX2-32-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
 ; AVX2-32-NEXT:    retl
 ;
 ; AVX2-64-LABEL: PR37502:
 ; AVX2-64:       # %bb.0:
 ; AVX2-64-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; AVX2-64-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
 ; AVX2-64-NEXT:    retq
   %i0 = insertelement <4 x float> undef, float %x, i32 0
   %i1 = insertelement <4 x float> %i0, float %y, i32 1
   %i2 = insertelement <4 x float> %i1, float %x, i32 2
   %i3 = insertelement <4 x float> %i2, float %y, i32 3
   ret <4 x float> %i3
 }
 

test/CodeGen/X86/vector-shuffle-combining-xop.ll

 ; X86AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
 ; X86AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
 ; X86AVX-NEXT:    vmovaps %xmm0, (%eax)
 ; X86AVX-NEXT:    retl
 ;
 ; X86AVX2-LABEL: buildvector_v4f32_0404:
 ; X86AVX2:       # %bb.0:
 ; X86AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86AVX2-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; X86AVX2-NEXT:    vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; X86AVX2-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
 ; X86AVX2-NEXT:    vmovapd %xmm0, (%eax)
 ; X86AVX2-NEXT:    retl
 ;
 ; X64AVX-LABEL: buildvector_v4f32_0404:
 ; X64AVX:       # %bb.0:
 ; X64AVX-NEXT:    vpermil2ps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[0],xmm1[0]
 ; X64AVX-NEXT:    vmovaps %xmm0, (%rdi)
 ; X64AVX-NEXT:    retq