This is an archive of the discontinued LLVM Phabricator instance.

GlobalISel: Verify g_zextload and g_sextload
ClosedPublic

Authored by arsenm on Dec 17 2018, 10:33 PM.

Download Raw Diff

Details

Reviewers

reames
aemerson
aditya_nandakumar
dsanders

Diff Detail

Event Timeline

arsenm created this revision.Dec 17 2018, 10:33 PM

Herald added subscribers: javed.absar, kristof.beyls, rovka, wdng. · View Herald TranscriptDec 17 2018, 10:33 PM

arsenm added reviewers: reames, aemerson, aditya_nandakumar.Dec 20 2018, 7:08 PM

ping

LGTM

This revision is now accepted and ready to land.Jan 18 2019, 10:31 AM

Herald added a subscriber: volkan. · View Herald TranscriptJan 18 2019, 10:31 AM

r351584

Revision Contents

Path

Size

lib/

CodeGen/

MachineVerifier.cpp

15 lines

test/

CodeGen/

MIR/

AArch64/

invalid-extload.mir

23 lines

Diff 178593

lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 974 Lines • ▼ Show 20 Lines	if (!TII->verifyInstruction(*MI, ErrorInfo))
report(ErrorInfo.data(), MI);		report(ErrorInfo.data(), MI);

// Verify properties of various specific instruction types		// Verify properties of various specific instruction types
switch(MI->getOpcode()) {		switch(MI->getOpcode()) {
default:		default:
break;		break;
case TargetOpcode::G_LOAD:		case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE:		case TargetOpcode::G_STORE:
		case TargetOpcode::G_ZEXTLOAD:
		case TargetOpcode::G_SEXTLOAD:
// Generic loads and stores must have a single MachineMemOperand		// Generic loads and stores must have a single MachineMemOperand
// describing that access.		// describing that access.
if (!MI->hasOneMemOperand())		if (!MI->hasOneMemOperand()) {
report("Generic instruction accessing memory must have one mem operand",		report("Generic instruction accessing memory must have one mem operand",
MI);		MI);
		} else {
		if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD \|\|
		MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
		const MachineMemOperand &MMO = **MI->memoperands_begin();
		LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
		if (MMO.getSize() * 8 >= DstTy.getSizeInBits()) {
		report("Generic extload must have a narrower memory type", MI);
		}
		}
		}

break;		break;
case TargetOpcode::G_PHI: {		case TargetOpcode::G_PHI: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());		LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
if (!DstTy.isValid() \|\|		if (!DstTy.isValid() \|\|
!std::all_of(MI->operands_begin() + 1, MI->operands_end(),		!std::all_of(MI->operands_begin() + 1, MI->operands_end(),
[this, &DstTy](const MachineOperand &MO) {		[this, &DstTy](const MachineOperand &MO) {
if (!MO.isReg())		if (!MO.isReg())
return true;		return true;
▲ Show 20 Lines • Show All 1,448 Lines • Show Last 20 Lines

test/CodeGen/MIR/AArch64/invalid-extload.mir

This file was added.

				# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s 2>&1 \| FileCheck %s

				# CHECK: * Bad machine code: Generic extload must have a narrower memory type *
				# CHECK: * Bad machine code: Generic extload must have a narrower memory type *
				# CHECK: * Bad machine code: Generic extload must have a narrower memory type *
				# CHECK: * Bad machine code: Generic extload must have a narrower memory type *
				# CHECK: * Bad machine code: Generic instruction accessing memory must have one mem operand *
				# CHECK: * Bad machine code: Generic instruction accessing memory must have one mem operand *

				---
				name: invalid_extload_memory_sizes
				body: \|
				bb.0:

				%0:_(p0) = COPY $x0
				%1:_(s64) = G_ZEXTLOAD %0(p0) :: (load 8)
				%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 16)
				%3:_(s64) = G_SEXTLOAD %0(p0) :: (load 8)
				%4:_(s64) = G_SEXTLOAD %0(p0) :: (load 16)
				%5:_(s64) = G_ZEXTLOAD %0(p0)
				%6:_(s64) = G_SEXTLOAD %0(p0)

				...