[PowerPC] Implement the ”isSelectSupported()“ target hook

[ZhangKang]

Summary

PowerPC has scalar selects (isel) and vector mask selects (xxsel). But PowerPC doesn't have vector CR selects, PowerPC does not support scalar condition selects on vectors.
In addition to implementing this hook,, isSelectSupported() should return false when the SelectSupportKind is ScalarCondVectorVal, so that predictable selects are converted into branch sequences.

[ZhangKang]

Add space on the right of !=. So that the Kind !=SelectSupportKind::ScalarCondVectorVal will be modified to Kind != SelectSupportKind::ScalarCondVectorVal.

[steven.zhang]

llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll

933

Does this mean that, your fix will remove the "vmr 3, 2" ?

[ZhangKang]

llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll

933

Yes, it will remove vmr 3, 2.
In fact, before the fix, the dag will generate the following nodes when making the selection.

315 SelectionDAG has 22 nodes:
 316   t0: ch = EntryToken
 317           t2: f32,ch = CopyFromReg t0, Register:f32 %0
 318           t4: f32,ch = CopyFromReg t0, Register:f32 %1
 319         t15: i1 = setcc t2, t4, setoeq:ch
 320           t6: f32,ch = CopyFromReg t0, Register:f32 %2
 321           t8: f32,ch = CopyFromReg t0, Register:f32 %3
 322         t14: i1 = setcc t6, t8, setoeq:ch
 323       t17: i1 = setcc t15, t14, seteq:ch
 324       t10: v4f32,ch = CopyFromReg t0, Register:v4f32 %4
 325       t12: v4f32,ch = CopyFromReg t0, Register:v4f32 %5
 326     t18: v4f32 = select t17, t10, t12
 327   t20: ch,glue = CopyToReg t0, Register:v4f32 $v2, t18
 328   t21: ch = PPCISD::RET_FLAG t20, Register:v4f32 $v2, t20:1

the corresponding assembly generated is

# %bb.0:                                # %entry
	fcmpu 0, 3, 4
	fcmpu 1, 1, 2
	crxor 20, 6, 2
	bc 12, 20, .LBB0_2
# %bb.1:                                # %entry
	vmr	3, 2
.LBB0_2:                                # %entry
	vmr	2, 3
	blr

after the fix, the dag will generate the following nodes when making the selection.

343 SelectionDAG has 17 nodes:
 344   t0: ch = EntryToken
 345         t2: f32,ch = CopyFromReg t0, Register:f32 %1
 346         t4: f32,ch = CopyFromReg t0, Register:f32 %2
 347       t15: i1 = setcc t2, t4, setoeq:ch
 348         t6: f32,ch = CopyFromReg t0, Register:f32 %3
 349         t8: f32,ch = CopyFromReg t0, Register:f32 %4
 350       t14: i1 = setcc t6, t8, setoeq:ch
 351     t22: ch = br_cc t0, seteq:ch, t15, t14, BasicBlock:ch<select.end 0x1001bacf748>
 352   t21: ch = br t22, BasicBlock:ch<select.false 0x1001bacf680>

the corresponding assembly generated is

# %bb.0:                                # %entry
	fcmpu 0, 3, 4
	fcmpu 1, 1, 2
	creqv 20, 6, 2
	bclr 12, 20, 0
# %bb.1:                                # %select.false
	vmr	2, 3
	blr

[steven.zhang]

LGTM. However, please hold on until another reviewer accept this patch,

[hfinkel]

LGTM too.

llvm/lib/Target/PowerPC/PPCISelLowering.h

namespace llvm {
   public:
     explicit PPCTargetLowering(const PPCTargetMachine &TM,
                                const PPCSubtarget &STI);
 
     /// getTargetNodeName() - This method returns the name of a target specific
     /// DAG node.
     const char *getTargetNodeName(unsigned Opcode) const override;
 
+    bool isSelectSupported(SelectSupportKind Kind) const override {
+      // PowerPC does not support scalar condition selects on vectors.
+      return (Kind != SelectSupportKind::ScalarCondVectorVal);
+    }
+
     /// getPreferredVectorAction - The code we generate when vector types are
     /// legalized by promoting the integer element type is often much worse
     /// than code we generate if we widen the type for applicable vector types.
     /// The issue with promoting is that the vector is scalaraized, individual
     /// elements promoted and then the vector is rebuilt. So say we load a pair
     /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
     /// loads, moves back into VSR's (or memory ops if we don't have moves) and
     /// then the VPERM for the shuffle. All in all a very slow sequence.

llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll

entry:
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floateq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB1:[0-9_]+]]
-; CHECK: vmr 3, 2
-; CHECK: .LBB[[BB1]]
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB]]
+; CHECK: bclr 12, 2, 0
 ; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB]]
+; CHECK: bclr 4, 2, 0
 ; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
entry:
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleeq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]]
-; CHECK: vmr 3, 2
-; CHECK: .LBB[[BB55]]
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
entry:
   %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doublesgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB]]
+; CHECK: bclr 4, 2, 0
 ; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB]]
+; CHECK: bclr 12, 2, 0
 ; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4