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Differential D55367

[AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.
ClosedPublic

Authored by sheredom on Dec 6 2018, 5:47 AM.

Details

Reviewers
nhaehnle
arsenm
Commits
rGe448351b7714: [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.
rL348771: [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.
Summary

This commit changes which l1 flush instruction is used for AMDPAL/MESA3D workloads to flush the entire l1 cache instead of just the volatile lines.

Diff Detail

Event Timeline

sheredom created this revision.Dec 6 2018, 5:47 AM
Herald added subscribers: llvm-commits, jfb, t-tye and 6 others. · View Herald TranscriptDec 6 2018, 5:47 AM
nhaehnle added a comment.Dec 7 2018, 7:54 AM

Please make the change apply to Mesa3D as well.

sheredom updated this revision to Diff 177480.Dec 10 2018, 3:35 AM
sheredom retitled this revision from [AMDGPU] Change the l1 flush instruction for AMDPAL. to [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D..
sheredom edited the summary of this revision. (Show Details)

Made the l1 flush change happen for MESA3D too (like Nicolai asked for).

nhaehnle accepted this revision.Dec 10 2018, 7:43 AM

LGTM

This revision is now accepted and ready to land.Dec 10 2018, 7:43 AM
Closed by commit rL348771: [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. (authored by sheredom). · Explain WhyDec 10 2018, 8:42 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
test/
CodeGen/
AMDGPU/
222 lines
222 lines

Diff 177480

lib/Target/AMDGPU/SIMemoryLegalizer.cpp

Show First 20 Lines • Show All 806 Lines • ▼ Show 20 Linesbool SIGfx7CacheControl::insertCacheInvalidate(MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, SIAtomicAddrSpace AddrSpace,
Position Pos) const { Position Pos) const {
bool Changed = false; bool Changed = false;
MachineBasicBlock &MBB = *MI->getParent(); MachineBasicBlock &MBB = *MI->getParent();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
const GCNSubtarget &STM = MBB.getParent()->getSubtarget<GCNSubtarget>();
const unsigned Flush = STM.isAmdPalOS() || STM.isMesa3DOS()
? AMDGPU::BUFFER_WBINVL1
: AMDGPU::BUFFER_WBINVL1_VOL;
if (Pos == Position::AFTER) if (Pos == Position::AFTER)
++MI; ++MI;
if ((AddrSpace & SIAtomicAddrSpace::GLOBAL) != SIAtomicAddrSpace::NONE) { if ((AddrSpace & SIAtomicAddrSpace::GLOBAL) != SIAtomicAddrSpace::NONE) {
switch (Scope) { switch (Scope) {
case SIAtomicScope::SYSTEM: case SIAtomicScope::SYSTEM:
case SIAtomicScope::AGENT: case SIAtomicScope::AGENT:
BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_WBINVL1_VOL)); BuildMI(MBB, MI, DL, TII->get(Flush));
Changed = true; Changed = true;
break; break;
case SIAtomicScope::WORKGROUP: case SIAtomicScope::WORKGROUP:
case SIAtomicScope::WAVEFRONT: case SIAtomicScope::WAVEFRONT:
case SIAtomicScope::SINGLETHREAD: case SIAtomicScope::SINGLETHREAD:
// No cache to invalidate. // No cache to invalidate.
break; break;
default: default:
▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/memory-legalizer-amdpal.ll

  • This file was added.
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx800 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; FUNC-LABEL: {{^}}system_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_acquire() {
entry:
fence acquire
ret void
}
; FUNC-LABEL: {{^}}system_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_release() {
entry:
fence release
ret void
}
; FUNC-LABEL: {{^}}system_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_acq_rel() {
entry:
fence acq_rel
ret void
}
; FUNC-LABEL: {{^}}system_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_seq_cst() {
entry:
fence seq_cst
ret void
}
; FUNC-LABEL: {{^}}singlethread_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_acquire() {
entry:
fence syncscope("singlethread") acquire
ret void
}
; FUNC-LABEL: {{^}}singlethread_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_release() {
entry:
fence syncscope("singlethread") release
ret void
}
; FUNC-LABEL: {{^}}singlethread_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_acq_rel() {
entry:
fence syncscope("singlethread") acq_rel
ret void
}
; FUNC-LABEL: {{^}}singlethread_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_seq_cst() {
entry:
fence syncscope("singlethread") seq_cst
ret void
}
; FUNC-LABEL: {{^}}agent_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_acquire() {
entry:
fence syncscope("agent") acquire
ret void
}
; FUNC-LABEL: {{^}}agent_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_release() {
entry:
fence syncscope("agent") release
ret void
}
; FUNC-LABEL: {{^}}agent_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_acq_rel() {
entry:
fence syncscope("agent") acq_rel
ret void
}
; FUNC-LABEL: {{^}}agent_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_seq_cst() {
entry:
fence syncscope("agent") seq_cst
ret void
}
; FUNC-LABEL: {{^}}workgroup_acquire:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_acquire() {
entry:
fence syncscope("workgroup") acquire
ret void
}
; FUNC-LABEL: {{^}}workgroup_release:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_release() {
entry:
fence syncscope("workgroup") release
ret void
}
; FUNC-LABEL: {{^}}workgroup_acq_rel:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_acq_rel() {
entry:
fence syncscope("workgroup") acq_rel
ret void
}
; FUNC-LABEL: {{^}}workgroup_seq_cst:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_seq_cst() {
entry:
fence syncscope("workgroup") seq_cst
ret void
}
; FUNC-LABEL: {{^}}wavefront_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_acquire() {
entry:
fence syncscope("wavefront") acquire
ret void
}
; FUNC-LABEL: {{^}}wavefront_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_release() {
entry:
fence syncscope("wavefront") release
ret void
}
; FUNC-LABEL: {{^}}wavefront_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_acq_rel() {
entry:
fence syncscope("wavefront") acq_rel
ret void
}
; FUNC-LABEL: {{^}}wavefront_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_seq_cst() {
entry:
fence syncscope("wavefront") seq_cst
ret void
}

test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll

  • This file was added.
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx800 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; RUN: llc -mtriple=amdgcn--mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN %s
; FUNC-LABEL: {{^}}system_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_acquire() {
entry:
fence acquire
ret void
}
; FUNC-LABEL: {{^}}system_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_release() {
entry:
fence release
ret void
}
; FUNC-LABEL: {{^}}system_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_acq_rel() {
entry:
fence acq_rel
ret void
}
; FUNC-LABEL: {{^}}system_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @system_seq_cst() {
entry:
fence seq_cst
ret void
}
; FUNC-LABEL: {{^}}singlethread_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_acquire() {
entry:
fence syncscope("singlethread") acquire
ret void
}
; FUNC-LABEL: {{^}}singlethread_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_release() {
entry:
fence syncscope("singlethread") release
ret void
}
; FUNC-LABEL: {{^}}singlethread_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_acq_rel() {
entry:
fence syncscope("singlethread") acq_rel
ret void
}
; FUNC-LABEL: {{^}}singlethread_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @singlethread_seq_cst() {
entry:
fence syncscope("singlethread") seq_cst
ret void
}
; FUNC-LABEL: {{^}}agent_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_acquire() {
entry:
fence syncscope("agent") acquire
ret void
}
; FUNC-LABEL: {{^}}agent_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_release() {
entry:
fence syncscope("agent") release
ret void
}
; FUNC-LABEL: {{^}}agent_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_acq_rel() {
entry:
fence syncscope("agent") acq_rel
ret void
}
; FUNC-LABEL: {{^}}agent_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_waitcnt vmcnt(0){{$}}
; GCN: buffer_wbinvl1{{$}}
; GCN: s_endpgm
define amdgpu_kernel void @agent_seq_cst() {
entry:
fence syncscope("agent") seq_cst
ret void
}
; FUNC-LABEL: {{^}}workgroup_acquire:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_acquire() {
entry:
fence syncscope("workgroup") acquire
ret void
}
; FUNC-LABEL: {{^}}workgroup_release:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_release() {
entry:
fence syncscope("workgroup") release
ret void
}
; FUNC-LABEL: {{^}}workgroup_acq_rel:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_acq_rel() {
entry:
fence syncscope("workgroup") acq_rel
ret void
}
; FUNC-LABEL: {{^}}workgroup_seq_cst:
; GCN: %bb.0
; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @workgroup_seq_cst() {
entry:
fence syncscope("workgroup") seq_cst
ret void
}
; FUNC-LABEL: {{^}}wavefront_acquire:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_acquire() {
entry:
fence syncscope("wavefront") acquire
ret void
}
; FUNC-LABEL: {{^}}wavefront_release:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_release() {
entry:
fence syncscope("wavefront") release
ret void
}
; FUNC-LABEL: {{^}}wavefront_acq_rel:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_acq_rel() {
entry:
fence syncscope("wavefront") acq_rel
ret void
}
; FUNC-LABEL: {{^}}wavefront_seq_cst:
; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE
; GCN: s_endpgm
define amdgpu_kernel void @wavefront_seq_cst() {
entry:
fence syncscope("wavefront") seq_cst
ret void
}