This commit changes which l1 flush instruction is used for AMDPAL/MESA3D workloads to flush the entire l1 cache instead of just the volatile lines.
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[AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. ClosedPublic Authored by sheredom on Dec 6 2018, 5:47 AM.
Details Summary This commit changes which l1 flush instruction is used for AMDPAL/MESA3D workloads to flush the entire l1 cache instead of just the volatile lines.
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Event TimelineHerald added subscribers: llvm-commits, jfb, t-tye and 6 others. · View Herald TranscriptDec 6 2018, 5:47 AM sheredom retitled this revision from [AMDGPU] Change the l1 flush instruction for AMDPAL. to [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D.. Comment ActionsMade the l1 flush change happen for MESA3D too (like Nicolai asked for). This revision is now accepted and ready to land.Dec 10 2018, 7:43 AM Closed by commit rL348771: [AMDGPU] Change the l1 flush instruction for AMDPAL/MESA3D. (authored by sheredom). · Explain WhyDec 10 2018, 8:42 AM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 177526 llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-amdpal.ll
llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-mesa3d.ll
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