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[DAGCombiner] narrow truncated vector binops when legal
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Authored by spatel on Nov 30 2018, 8:04 AM.

Details

Summary

This is the smallest vector enhancement I could find to D54640. Here, we're allowing narrowing to only legal vector ops because we'll see regressions without that. All of the test diffs are wins from what I can tell. With AVX/AVX512, we can shrink ymm/zmm ops to xmm.

x86 vector multiplies are the problem case due to the patchwork ISA, and it's not clear to me if we can dance around those regressions using TLI hooks or if we need preliminary patches to plug those holes.

This patch probably makes some of the custom x86 code in "combineTruncatedArithmetic" unnecessary, but I'd rather wait to try removing anything from there until we're sure this code doesn't cause regressions for other targets and evolves to handle more cases.

Diff Detail

Event Timeline

spatel created this revision.Nov 30 2018, 8:04 AM
RKSimon accepted this revision.Dec 3 2018, 1:53 AM

LGTM - if you're not going to work on simplifying/removing X86's combineTruncatedArithmetic immediately please add a TODO comment.

This revision is now accepted and ready to land.Dec 3 2018, 1:53 AM
This revision was automatically updated to reflect the committed changes.