AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts

[pendingchaos]

This fixes a selection error I came across:

LLVM ERROR: Cannot select: t16: v4f16 = bitcast t15

t15: v4i16,ch = CopyFromReg t0, Register:v4i16 %3
  t14: v4i16 = Register %3

I'm not too familiar with LLVM, so I'm not 100% certain of the correctness or
completeness of this.

I don't have commit access.

[arsenm]

Needs test case, but this is correct

[pendingchaos]

Adds a test for the bug.

[arsenm]

test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll

4 ↗

(On Diff #176282)

probably should use amdgpu_ps to avoid the waterfall

9 ↗

(On Diff #176282)

Can you add the inverse too?

[pendingchaos]

Update test.

[arsenm]

LGTM

lib/Target/AMDGPU/SIInstructions.td

 def : BitConvert <i64, v2i32, VReg_64>;
 def : BitConvert <v2i32, i64, VReg_64>;
 def : BitConvert <i64, v2f32, VReg_64>;
 def : BitConvert <v2f32, i64, VReg_64>;
 def : BitConvert <f64, v2f32, VReg_64>;
 def : BitConvert <v2f32, f64, VReg_64>;
 def : BitConvert <f64, v2i32, VReg_64>;
 def : BitConvert <v2i32, f64, VReg_64>;
+def : BitConvert <v4i16, v4f16, VReg_64>;
+def : BitConvert <v4f16, v4i16, VReg_64>;
 
 // FIXME: Make SGPR
 def : BitConvert <v2i32, v4f16, VReg_64>;
 def : BitConvert <v4f16, v2i32, VReg_64>;
 def : BitConvert <v2i32, v4f16, VReg_64>;
 def : BitConvert <v2i32, v4i16, VReg_64>;
 def : BitConvert <v4i16, v2i32, VReg_64>;
 def : BitConvert <v2f32, v4f16, VReg_64>;