AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts

[pendingchaos]

This fixes a selection error I came across:

LLVM ERROR: Cannot select: t16: v4f16 = bitcast t15

t15: v4i16,ch = CopyFromReg t0, Register:v4i16 %3
  t14: v4i16 = Register %3

I'm not too familiar with LLVM, so I'm not 100% certain of the correctness or
completeness of this.

I don't have commit access.

[arsenm]

Needs test case, but this is correct

[pendingchaos]

Adds a test for the bug.

[arsenm]

test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll

4 ↗

(On Diff #176282)

probably should use amdgpu_ps to avoid the waterfall

9 ↗

(On Diff #176282)

Can you add the inverse too?

[pendingchaos]

Update test.

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

 def : BitConvert <i64, v2i32, VReg_64>;
 def : BitConvert <v2i32, i64, VReg_64>;
 def : BitConvert <i64, v2f32, VReg_64>;
 def : BitConvert <v2f32, i64, VReg_64>;
 def : BitConvert <f64, v2f32, VReg_64>;
 def : BitConvert <v2f32, f64, VReg_64>;
 def : BitConvert <f64, v2i32, VReg_64>;
 def : BitConvert <v2i32, f64, VReg_64>;
+def : BitConvert <v4i16, v4f16, VReg_64>;
+def : BitConvert <v4f16, v4i16, VReg_64>;
 
 // FIXME: Make SGPR
 def : BitConvert <v2i32, v4f16, VReg_64>;
 def : BitConvert <v4f16, v2i32, VReg_64>;
 def : BitConvert <v2i32, v4f16, VReg_64>;
 def : BitConvert <v2i32, v4i16, VReg_64>;
 def : BitConvert <v4i16, v2i32, VReg_64>;
 def : BitConvert <v2f32, v4f16, VReg_64>;

llvm/trunk/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
+
+; creating v4i16->v4f16 and v4f16->v4i16 bitcasts in the selection DAG is rather
+; difficult, so this test has to throw in some llvm.amdgcn.wqm to get them
+
+; LABEL: {{^}}test_to_i16:
+; CHECK: s_endpgm
+define amdgpu_ps void @test_to_i16(<4 x i32> inreg, <4 x half> inreg) #0 {
+  %a_tmp = call <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half> %1)
+  %a_i16_tmp = bitcast <4 x half> %a_tmp to <4 x i16>
+  %a_i16 = call <4 x i16> @llvm.amdgcn.wqm.v4i16(<4 x i16> %a_i16_tmp)
+
+  %a_i32 = bitcast <4 x i16> %a_i16 to <2 x i32>
+  call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %a_i32, <4 x i32> %0, i32 0, i32 0, i32 0)
+  ret void
+}
+
+; LABEL: {{^}}test_to_half:
+; CHECK: s_endpgm
+define amdgpu_ps void @test_to_half(<4 x i32> inreg, <4 x i16> inreg) #0 {
+  %a_tmp = call <4 x i16> @llvm.amdgcn.wqm.v4i16(<4 x i16> %1)
+  %a_half_tmp = bitcast <4 x i16> %a_tmp to <4 x half>
+  %a_half = call <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half> %a_half_tmp)
+
+  %a_i32 = bitcast <4 x half> %a_half to <2 x i32>
+  call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %a_i32, <4 x i32> %0, i32 0, i32 0, i32 0)
+  ret void
+}
+
+declare <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half>) #1
+declare <4 x i16> @llvm.amdgcn.wqm.v4i16(<4 x i16>) #1
+declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32) #0
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }