[PPC64] Support toc-optimization for '@got' relocations

[sfertile]

Summary

Extends the toc-optimizations to the '@got' relocations.

[ruiu]

LGTM

lld/trunk/ELF/Arch/PPC64.cpp

static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
   case R_PPC64_DTPREL64:
     return {R_PPC64_ADDR64, DTPBiasedVal};
 
   default:
     return {Type, Val};
   }
 }
 
-static bool isTocRelType(RelType Type) {
-  return Type == R_PPC64_TOC16_HA || Type == R_PPC64_TOC16_LO_DS ||
-         Type == R_PPC64_TOC16_LO;
+static bool isTocOptType(RelType Type) {
+  switch (Type) {
+  case R_PPC64_GOT16_HA:
+  case R_PPC64_GOT16_LO_DS:
+  case R_PPC64_TOC16_HA:
+  case R_PPC64_TOC16_LO_DS:
+  case R_PPC64_TOC16_LO:
+    return true;
+  default:
+    return false;
+  }
 }
 
 void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   // We need to save the original relocation type to determine if we should
   // toc-optimize the instructions being relocated.
-  bool IsTocRelType = isTocRelType(Type);
+  bool ShouldTocOptimize =  isTocOptType(Type);
   // For TOC-relative and GOT-indirect relocations, proceed in terms of the
   // corresponding ADDR16 relocation type.
   std::tie(Type, Val) = toAddr16Rel(Type, Val);
 
   switch (Type) {
   case R_PPC64_ADDR14: {
     checkAlignment(Loc, Val, 4, Type);
     // Preserve the AA/LK bits in the branch instruction
case R_PPC64_TPREL16_DS: {
     // DS-form instructions only use bits 30-31.
     uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 0xF : 0x3;
     checkAlignment(Loc, lo(Val), Mask + 1, Type);
     write16(Loc, (read16(Loc) & Mask) | lo(Val));
   } break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
   case R_PPC64_TPREL16_HA:
-    if (Config->TocOptimize && IsTocRelType && ha(Val) == 0)
+    if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0)
       writeInstrFromHalf16(Loc, 0x60000000);
     else
       write16(Loc, ha(Val));
     break;
   case R_PPC64_ADDR16_HI:
   case R_PPC64_REL16_HI:
   case R_PPC64_TPREL16_HI:
     write16(Loc, hi(Val));
case R_PPC64_TPREL16_HIGHESTA:
     write16(Loc, highesta(Val));
     break;
   case R_PPC64_ADDR16_LO:
   case R_PPC64_REL16_LO:
   case R_PPC64_TPREL16_LO:
     // When the high-adjusted part of a toc relocation evalutes to 0, it is
     // changed into a nop. The lo part then needs to be updated to use the
     // toc-pointer register r2, as the base register.
-    if (Config->TocOptimize && IsTocRelType && ha(Val) == 0) {
+    if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
       uint32_t Instr = readInstrFromHalf16(Loc);
       if (isInstructionUpdateForm(Instr))
         error(getErrorLocation(Loc) +
               "can't toc-optimize an update instruction: 0x" +
               utohexstr(Instr));
       Instr = (Instr & 0xFFE00000) | 0x00020000;
       writeInstrFromHalf16(Loc, Instr);
     }
     write16(Loc, lo(Val));
     break;
   case R_PPC64_ADDR16_LO_DS:
   case R_PPC64_TPREL16_LO_DS: {
     // DQ-form instructions use bits 28-31 as part of the instruction encoding
     // DS-form instructions only use bits 30-31.
     uint32_t Inst = readInstrFromHalf16(Loc);
     uint16_t Mask = isDQFormInstruction(Inst) ? 0xF : 0x3;
     checkAlignment(Loc, lo(Val), Mask + 1, Type);
-    if (Config->TocOptimize && IsTocRelType && ha(Val) == 0) {
+    if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
       // When the high-adjusted part of a toc relocation evalutes to 0, it is
       // changed into a nop. The lo part then needs to be updated to use the toc
       // pointer register r2, as the base register.
       if (isInstructionUpdateForm(Inst))
         error(getErrorLocation(Loc) +
               "Can't toc-optimize an update instruction: 0x" +
               Twine::utohexstr(Inst));
       Inst = (Inst & 0xFFE0000F) | 0x00020000;

lld/trunk/test/ELF/ppc64-got-off.s

 # REQUIRES: ppc
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
 # RUN: ld.lld -shared --no-toc-optimize %t.o -o %t
 # RUN: llvm-objdump -d %t | FileCheck %s
 
 # RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
 # RUN: ld.lld -shared --no-toc-optimize %t.o -o %t
 # RUN: llvm-objdump -d %t | FileCheck %s
 
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
+# RUN: ld.lld -shared %t.o -o %t
+# RUN: llvm-objdump -d %t | FileCheck --check-prefix=OPT %s
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
+# RUN: ld.lld -shared %t.o -o %t
+# RUN: llvm-objdump -d %t | FileCheck --check-prefix=OPT %s
+
         .abiversion 2
         .section ".text"
 
         .p2align 2
         .global func
         .type func, @function
 func:
 .Lfunc_gep:

 # CHECK:         addis 3, 2, 0
 # CHECK-NEXT:    ld 3, -32760(3)
 # CHECK-NEXT:    ld 4, -32760(2)
 # CHECK-NEXT:    lis 5, -1
 # CHECK-NEXT:    ori 5, 5, 32776
 # CHECK-NEXT:    li  6, 0
 # CHECK-NEXT:    ori 6, 6, 32776
 
+# OPT-LABEL: func
+# OPT:         nop
+# OPT-NEXT:    ld 3, -32760(2)
+# OPT-NEXT:    ld 4, -32760(2)
+# OPT-NEXT:    lis 5, -1
+# OPT-NEXT:    ori 5, 5, 32776
+# OPT-NEXT:    li  6, 0
+# OPT-NEXT:    ori 6, 6, 32776
+
 # Since the got entry for a is .got[1] and the TOC base points to
 # .got + 0x8000, the offset for a@got is -0x7FF8 --> -32760
 
         .section ".data"
         .global a
         .type a, @object
         .size a, 4
         .p2align 2
 a:
         .long 0x1000