[PPC][PPC64] PPC_REL14 and PPC64_REL14 relocations

[martell]

Summary

When linking the linux kernel on ppc64 and probably ppc
ld.lld: error: built-in.a(arch/powerpc/kernel/head_64.o):(.head.text.virt_vectors+0x53C): unrecognized reloc 11
11 is PPC_REL14 and PPC64_REL14

[MaskRay]

ELF/Arch/PPC.cpp

41 ↗

(On Diff #175158)

14 24 32 may feel more natural

ELF/Arch/PPC64.cpp

425 ↗

(On Diff #175158)

ditto here

[ruiu]

LGTM with these changes.

ELF/Arch/PPC.cpp

41 ↗

(On Diff #175158)

Yup, please sort.

70–72 ↗

(On Diff #175158)

Add this before REL24, instead of adding to the end of the existing code.

ELF/Arch/PPC64.cpp

703 ↗

(On Diff #175158)

Ditto

721 ↗

(On Diff #175158)

Ditto

[joel]

ELF/Arch/PPC64.cpp

720 ↗

(On Diff #175158)

This comment is now stale

739 ↗

(On Diff #175158)

This introduces a warning:

lld/ELF/Arch/PPC64.cpp:739:57: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses]
   assert(Type == R_PPC64_REL24 || Type == R_PPC64_REL14 &&
                                   ~~~~~~~~~~~~~~~~~~~~~~^~

[martell]

update to address comments

[martell]

This probably needs another approval based on the small changes I made to address the warning

[sfertile]

Other then my one comment it LGTM.

ELF/Arch/PPC64.cpp

743 ↗

(On Diff #176306)

inBranchRange is either called from the end of PPC64::needsThunk in which case the type must be either REL14 or REL24, or from the thunk creation framework which means that PPC64::needsThunk must have been true (and the type must have been REL14/REL24) . Because of that I think an llvm_unreachable is more appropriate than an error message.

[ruiu]

ELF/Arch/PPC64.cpp

743 ↗

(On Diff #176306)

Error messages should start with a lowercase letter.

[ruiu]

lld/trunk/ELF/Arch/PPC64.cpp

744

Please do not write any code after llvm_unreachable as the code is literally unreachable.

lld/trunk/ELF/Arch/PPC.cpp

PPC::PPC() {
   NoneRel = R_PPC_NONE;
   GotBaseSymOff = 0x8000;
   GotBaseSymInGotPlt = false;
 }
 
 RelExpr PPC::getRelExpr(RelType Type, const Symbol &S,
                         const uint8_t *Loc) const {
   switch (Type) {
+  case R_PPC_REL14:
   case R_PPC_REL24:
   case R_PPC_REL32:
     return R_PC;
   case R_PPC_PLTREL24:
     return R_PLT_PC;
   default:
     return R_ABS;
   }
case R_PPC_ADDR16_HI:
     break;
   case R_PPC_ADDR16_LO:
     write16be(Loc, Val);
     break;
   case R_PPC_ADDR32:
   case R_PPC_REL32:
     write32be(Loc, Val);
     break;
+  case R_PPC_REL14:
+    write32be(Loc, read32be(Loc) | (Val & 0xFFFC));
+    break;
   case R_PPC_PLTREL24:
   case R_PPC_REL24:
     write32be(Loc, read32be(Loc) | (Val & 0x3FFFFFC));
     break;
   default:
     error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
   }
 }
 
 TargetInfo *elf::getPPCTargetInfo() {
   static PPC Target;
   return &Target;
 }

lld/trunk/ELF/Arch/PPC64.cpp

RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
   case R_PPC64_TOC16_DS:
   case R_PPC64_TOC16_HA:
   case R_PPC64_TOC16_HI:
   case R_PPC64_TOC16_LO:
   case R_PPC64_TOC16_LO_DS:
     return R_GOTREL;
   case R_PPC64_TOC:
     return R_PPC_TOC;
+  case R_PPC64_REL14:
   case R_PPC64_REL24:
     return R_PPC_CALL_PLT;
   case R_PPC64_REL16_LO:
   case R_PPC64_REL16_HA:
   case R_PPC64_REL32:
   case R_PPC64_REL64:
     return R_PC;
   case R_PPC64_GOT_TLSGD16:
case R_PPC64_REL32:
     checkInt(Loc, Val, 32, Type);
     write32(Loc, Val);
     break;
   case R_PPC64_ADDR64:
   case R_PPC64_REL64:
   case R_PPC64_TOC:
     write64(Loc, Val);
     break;
+  case R_PPC64_REL14: {
+    uint32_t Mask = 0x0000FFFC;
+    checkInt(Loc, Val, 16, Type);
+    checkAlignment(Loc, Val, 4, Type);
+    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
+    break;
+  }
   case R_PPC64_REL24: {
     uint32_t Mask = 0x03FFFFFC;
     checkInt(Loc, Val, 26, Type);
     checkAlignment(Loc, Val, 4, Type);
     write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
     break;
   }
   case R_PPC64_DTPREL64:
     write64(Loc, Val - DynamicThreadPointerOffset);
     break;
   default:
     error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
   }
 }
 
 bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                        uint64_t BranchAddr, const Symbol &S) const {
-  // The only call relocation we currently support is the REL24 type.
-  if (Type != R_PPC64_REL24)
+  if (Type != R_PPC64_REL14 && Type != R_PPC64_REL24)
     return false;
 
   // If a function is in the Plt it needs to be called with a call-stub.
   if (S.isInPlt())
     return true;
 
   // If a symbol is a weak undefined and we are compiling an executable
   // it doesn't need a range-extending thunk since it can't be called.
   if (S.isUndefWeak() && !Config->Shared)
     return false;
 
   // If the offset exceeds the range of the branch type then it will need
   // a range-extending thunk.
   return !inBranchRange(Type, BranchAddr, S.getVA());
 }
 
 bool PPC64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
-  assert(Type == R_PPC64_REL24 && "Unexpected relocation type used in branch");
   int64_t Offset = Dst - Src;
+  if (Type == R_PPC64_REL14)
+    return isInt<16>(Offset);
+  if (Type == R_PPC64_REL24)
     return isInt<26>(Offset);
+  llvm_unreachable("unsupported relocation type used in branch");
+  return false;
 }
 
 RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
                                RelExpr Expr) const {
   if (Expr == R_RELAX_TLS_GD_TO_IE)
     return R_RELAX_TLS_GD_TO_IE_GOT_OFF;
   if (Expr == R_RELAX_TLS_LD_TO_LE)
     return R_RELAX_TLS_LD_TO_LE_ABS;

lld/trunk/test/ELF/ppc-relocs.s

.FR_PPC_REL24:
   b .Lfoox
 .section .R_PPC_REL24_2,"ax",@progbits
 .Lfoox:
 
 # CHECK: Disassembly of section .R_PPC_REL24:
 # CHECK: .FR_PPC_REL24:
 # CHECK:    1101c:       48 00 00 04     b .+4
 
+.section .R_PPC_REL14,"ax",@progbits
+.globl .FR_PPC_REL14
+.FR_PPC_REL14:
+  beq .Lfooy
+.section .R_PPC_REL14_2,"ax",@progbits
+.Lfooy:
+
+# CHECK: Disassembly of section .R_PPC_REL14:
+# CHECK: .FR_PPC_REL14:
+# CHECK:    11020: {{.*}} bt 2, .+4
+
 .section .R_PPC_REL32,"ax",@progbits
 .globl .FR_PPC_REL32
 .FR_PPC_REL32:
   .long .Lfoox3 - .
 .section .R_PPC_REL32_2,"ax",@progbits
 .Lfoox3:
 
 # CHECK: Disassembly of section .R_PPC_REL32:
 # CHECK: .FR_PPC_REL32:
-# CHECK:    11020:       00 00 00 04
+# CHECK:    11024:       00 00 00 04
 
 .section .R_PPC_ADDR32,"ax",@progbits
 .globl .FR_PPC_ADDR32
 .FR_PPC_ADDR32:
   .long .Lfoox2
 .section .R_PPC_ADDR32_2,"ax",@progbits
 .Lfoox2:
 
 # CHECK: Disassembly of section .R_PPC_ADDR32:
 # CHECK: .FR_PPC_ADDR32:
-# CHECK:    11024:       00 01 10 28
+# CHECK:    11028:       00 01 10 2c
 
 .align  2
 .section .R_PPC_PLTREL24,"ax",@progbits
 .globl .R_PPC_PLTREL24
 .FR_PPC_PLTREL24:
   b .Lfoox4@PLT
 .section .R_PPC_PLTREL24_2,"ax",@progbits
 .Lfoox4:
 
 # CHECK: Disassembly of section .R_PPC_PLTREL24:
 # CHECK: .R_PPC_PLTREL24:
-# CHECK:    11028:       48 00 00 04     b .+4
+# CHECK:    1102c:       48 00 00 04     b .+4

lld/trunk/test/ELF/ppc64-relocs.s

.FR_PPC64_REL24:
   b .Lfoox
 .section .R_PPC64_REL24_2,"ax",@progbits
 .Lfoox:
 
 # CHECK: Disassembly of section .R_PPC64_REL24:
 # CHECK: .FR_PPC64_REL24:
 # CHECK: 1001001c: {{.*}} b .+4
 
+.section .R_PPC64_REL14,"ax",@progbits
+.globl .FR_PPC64_REL14
+.FR_PPC64_REL14:
+  beq .Lfooy
+.section .R_PPC64_REL14_2,"ax",@progbits
+.Lfooy:
+
+# CHECK: Disassembly of section .R_PPC64_REL14:
+# CHECK: .FR_PPC64_REL14:
+# CHECK: 10010020: {{.*}} bt 2, .+4
+
 .section .R_PPC64_ADDR16_LO,"ax",@progbits
 .globl .FR_PPC64_ADDR16_LO
 .FR_PPC64_ADDR16_LO:
   li 1, .Lfoo@l
 
 # CHECK: Disassembly of section .R_PPC64_ADDR16_LO:
 # CHECK: .FR_PPC64_ADDR16_LO:
-# CHECK: 10010020: {{.*}} li 1, 0
+# CHECK: 10010024: {{.*}} li 1, 0
 
 .section .R_PPC64_ADDR16_HI,"ax",@progbits
 .globl .FR_PPC64_ADDR16_HI
 .FR_PPC64_ADDR16_HI:
   li 1, .Lfoo@h
 
 # CHECK: Disassembly of section .R_PPC64_ADDR16_HI:
 # CHECK: .FR_PPC64_ADDR16_HI:
-# CHECK: 10010024: {{.*}} li 1, 4097
+# CHECK: 10010028: {{.*}} li 1, 4097
 
 .section .R_PPC64_ADDR16_HA,"ax",@progbits
 .globl .FR_PPC64_ADDR16_HA
 .FR_PPC64_ADDR16_HA:
   li 1, .Lfoo@ha
 
 # CHECK: Disassembly of section .R_PPC64_ADDR16_HA:
 # CHECK: .FR_PPC64_ADDR16_HA:
-# CHECK: 10010028: {{.*}} li 1, 4097
+# CHECK: 1001002c: {{.*}} li 1, 4097
 
 .section .R_PPC64_ADDR16_HIGHER,"ax",@progbits
 .globl .FR_PPC64_ADDR16_HIGHER
 .FR_PPC64_ADDR16_HIGHER:
   li 1, .Lfoo@higher
 
 # CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHER:
 # CHECK: .FR_PPC64_ADDR16_HIGHER:
-# CHECK: 1001002c: {{.*}} li 1, 0
+# CHECK: 10010030: {{.*}} li 1, 0
 
 .section .R_PPC64_ADDR16_HIGHERA,"ax",@progbits
 .globl .FR_PPC64_ADDR16_HIGHERA
 .FR_PPC64_ADDR16_HIGHERA:
   li 1, .Lfoo@highera
 
 # CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHERA:
 # CHECK: .FR_PPC64_ADDR16_HIGHERA:
-# CHECK: 10010030: {{.*}} li 1, 0
+# CHECK: 10010034: {{.*}} li 1, 0
 
 .section .R_PPC64_ADDR16_HIGHEST,"ax",@progbits
 .globl .FR_PPC64_ADDR16_HIGHEST
 .FR_PPC64_ADDR16_HIGHEST:
   li 1, .Lfoo@highest
 
 # CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHEST:
 # CHECK: .FR_PPC64_ADDR16_HIGHEST:
-# CHECK: 10010034: {{.*}} li 1, 0
+# CHECK: 10010038: {{.*}} li 1, 0
 
 .section .R_PPC64_ADDR16_HIGHESTA,"ax",@progbits
 .globl .FR_PPC64_ADDR16_HIGHESTA
 .FR_PPC64_ADDR16_HIGHESTA:
   li 1, .Lfoo@highesta
 
 # CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHESTA:
 # CHECK: .FR_PPC64_ADDR16_HIGHESTA:
-# CHECK: 10010038: {{.*}} li 1, 0
+# CHECK: 1001003c: {{.*}} li 1, 0
 
 .section  .R_PPC64_REL32, "ax",@progbits
 .globl .FR_PPC64_REL32
 .FR_PPC64_REL32:
   addis 5, 2, .LC0@toc@ha
   ld 5, .LC0@toc@l(5)
 .LBB0_2:
   add 3, 3, 4
 
 # DATALE: Disassembly of section .rodata:
 # DATALE: .rodata:
-# DATALE: 10000190: b4 fe 00 00
+# DATALE: 10000190: b8 fe 00 00
 
 # DATABE: Disassembly of section .rodata:
 # DATABE: .rodata:
-# DATABE: 10000190: 00 00 fe b4
+# DATABE: 10000190: 00 00 fe b8
 
 # Address of rodata + value stored at rodata entry
 # should equal address of LBB0_2.
 # 0x10000190 + 0xfeb4 = 0x10010044
 # CHECK: Disassembly of section .R_PPC64_REL32:
 # CHECK: .FR_PPC64_REL32:
-# CHECK: 1001003c: {{.*}} nop
-# CHECK: 10010040: {{.*}} ld 5, -32736(2)
-# CHECK: 10010044: {{.*}} add 3, 3, 4
+# CHECK: 10010040: {{.*}} nop
+# CHECK: 10010044: {{.*}} ld 5, -32736(2)
+# CHECK: 10010048: {{.*}} add 3, 3, 4
 
 .section .R_PPC64_REL64, "ax",@progbits
 .globl  .FR_PPC64_REL64
 .FR_PPC64_REL64:
         .cfi_startproc
         .cfi_personality 148, __foo
         li 0, 1
         li 3, 55
         sc
         .cfi_endproc
 __foo:
   li 3,0
 
 # Check that address of eh_frame entry + value stored
 # should equal the address of foo. Since it is not aligned,
-# the entry is not stored exactly at 100001a8. It starts at
-# address 0x100001aa and has the value 0xfeaa.
-# 0x100001aa + 0xfeaa = 0x10010054
+# the entry is not stored exactly at 10000198. It starts at
+# address 0x1000019a and has the value 0xfeaa.
+# 0x100001aa + 0xfeae = 0x10010058
 # DATALE: Disassembly of section .eh_frame:
 # DATALE: .eh_frame:
-# DATALE: 100001a8: {{.*}} aa fe
+# DATALE: 100001a8: {{.*}} ae fe
 
 # DATABE: Disassembly of section .eh_frame:
 # DATABE: .eh_frame:
-# DATABE: 100001b0: fe aa {{.*}}
+# DATABE: 100001b0: fe ae {{.*}}
 
 # CHECK: __foo
-# CHECK-NEXT: 10010054: {{.*}} li 3, 0
+# CHECK-NEXT: 10010058: {{.*}} li 3, 0