Page MenuHomePhabricator

[LLD][AArch64] Cortex-a53-843419 erratum should not apply to relaxed TLS.
ClosedPublic

Authored by peter.smith on Nov 23 2018, 3:56 AM.

Details

Summary

The changes to the instructions performed by TLS relaxation and the errata patching are performed with relocations. As these are applied so late the errata scanning won't see the changes in the section data made by the TLS relaxation. This can lead to a TLS relaxed sequence being patched when it doesn't need to be.

The fix checks to see if there is a R_RELAX_TLS_IE_TO_LE instruction at the same address as the ADRP as this indicates the presence of a relaxation of a sequence that might get recognised as a patch. None of the other TLS code sequences that can be relaxed by LLD will match the erratum so I've not tested for them.

This fix was inspired by a recently reported GNU ld assertion failure https://sourceware.org/bugzilla/show_bug.cgi?id=23904 . I don't think that LLD's errata scanner will match any of the TLS code sequences in that PR as LLD checks that the 2nd instruction doesn't write to the destination register of the ADRP and ld.bfd does not. However as the fix is simple I've made the change to be safe.

Diff Detail

Repository
rL LLVM

Event Timeline

peter.smith created this revision.Nov 23 2018, 3:56 AM
grimar accepted this revision.Nov 23 2018, 4:12 AM

Looks good to me.

This revision is now accepted and ready to land.Nov 23 2018, 4:12 AM
ruiu accepted this revision.Nov 26 2018, 10:08 AM

LGTM

This revision was automatically updated to reflect the committed changes.