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Differential D54718

Restored selection of scalar_to_vector (v2x16)
ClosedPublic

Authored by rampitec on Nov 19 2018, 11:58 AM.

Details

Reviewers
arsenm
kzhuravl
scott.linder
Commits
rG8bafbae88963: [AMDGPU] Restored selection of scalar_to_vector (v2x16)
rL347259: [AMDGPU] Restored selection of scalar_to_vector (v2x16)
Summary

This works if DAG combiner is enabled, but without combining
we cannot select scalar_to_vector of <2 x half> and <2 x i16>.

Diff Detail

Repository
rL LLVM

Event Timeline

rampitec created this revision.Nov 19 2018, 11:58 AM
Herald added subscribers: nhaehnle, wdng, jvesely. · View Herald TranscriptNov 19 2018, 11:58 AM
rampitec mentioned this in D54358: [AMDGPU] Disable DAG combine at -O0.Nov 19 2018, 11:58 AM
arsenm accepted this revision.Nov 19 2018, 11:59 AM

LGTM

This revision is now accepted and ready to land.Nov 19 2018, 11:59 AM
kzhuravl accepted this revision.Nov 19 2018, 11:59 AM

LGTM

Closed by commit rL347259: [AMDGPU] Restored selection of scalar_to_vector (v2x16) (authored by rampitec). · Explain WhyNov 19 2018, 12:01 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
18 lines
test/
CodeGen/
AMDGPU/
26 lines

Diff 174664

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 1,531 Lines • ▼ Show 20 Lines
def : GCNPat < def : GCNPat <
(v2f16 (build_vector f16:$src0, f16:$src1)), (v2f16 (build_vector f16:$src0, f16:$src1)),
(v2f16 (S_PACK_LL_B32_B16 $src0, $src1)) (v2f16 (S_PACK_LL_B32_B16 $src0, $src1))
>; >;
} // End SubtargetPredicate = HasVOP3PInsts } // End SubtargetPredicate = HasVOP3PInsts
// def : GCNPat < def : GCNPat <
// (v2f16 (scalar_to_vector f16:$src0)), (v2f16 (scalar_to_vector f16:$src0)),
// (COPY $src0) (COPY $src0)
// >; >;
// def : GCNPat < def : GCNPat <
// (v2i16 (scalar_to_vector i16:$src0)), (v2i16 (scalar_to_vector i16:$src0)),
// (COPY $src0) (COPY $src0)
// >; >;
def : GCNPat < def : GCNPat <
(v4i16 (scalar_to_vector i16:$src0)), (v4i16 (scalar_to_vector i16:$src0)),
(INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0) (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
>; >;
def : GCNPat < def : GCNPat <
(v4f16 (scalar_to_vector f16:$src0)), (v4f16 (scalar_to_vector f16:$src0)),
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll

; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-OPT %s
; RUN: llc -march=amdgcn -mcpu=fiji -O0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-NOOPT %s
; GCN-LABEL: {{^}}scalar_to_vector_i16:
; GCN-NOOPT: s_mov_b32 [[S:s[0-9]+]], 42
; GCN-NOOPT: v_mov_b32_e32 [[V:v[0-9]+]], [[S]]
; GCN-OPT: v_mov_b32_e32 [[V:v[0-9]+]], 42
; GCN: buffer_store_short [[V]],
define void @scalar_to_vector_i16() {
%tmp = load <2 x i16>, <2 x i16> addrspace(5)* undef
%tmp1 = insertelement <2 x i16> %tmp, i16 42, i64 0
store <2 x i16> %tmp1, <2 x i16> addrspace(5)* undef
ret void
}
; GCN-LABEL: {{^}}scalar_to_vector_f16:
; GCN-NOOPT: s_movk_i32 [[S:s[0-9]+]], 0x3c00
; GCN-NOOPT: v_mov_b32_e32 [[V:v[0-9]+]], [[S]]
; GCN-OPT: v_mov_b32_e32 [[V:v[0-9]+]], 0x3c00
; GCN: buffer_store_short [[V]],
define void @scalar_to_vector_f16() {
%tmp = load <2 x half>, <2 x half> addrspace(5)* undef
%tmp1 = insertelement <2 x half> %tmp, half 1.0, i64 0
store <2 x half> %tmp1, <2 x half> addrspace(5)* undef
ret void
}